Ordering number : ENA1156A LC87F7DC8A CMOS IC FROM 128K byte, RAM 4K byte on-chip http://onsemi.com 8-bit 1-chip Microcontroller Overview The LC87F7DC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard programmable), 4K-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-of-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, two UART ports (full duplex), an 12-bit 15-channel AD converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, two remote control receive functions, and a 31-source 10-vector interrupt feature. Features Flash ROM • Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source. • Block-erasable in 2-byte units • 131072 × 8 bits RAM • 4096 × 9 bits Minimum Bus Cycle Time • 83.3ns (12MHz) VDD=3.0 to 5.5V • 125ns (8MHz) VDD=2.5 to 5.5V • 250ns (4MHz) VDD=2.2 to 5.5V Note: The bus cycle time here refers to the ROM read speed. * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.0.10 22410HKIM 20100217-S00003 No.A1156-1/26 LC87F7DC8A Minimum Instruction Cycle Time (tCYC) • 250ns (12MHz) VDD=3.0 to 5.5V • 375ns (8MHz) VDD=2.5 to 5.5V • 750ns (4MHz) VDD=2.2 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units 29 (P0n, P1n, P70 to P73, P8n, XT2) • Normal withstand voltage input port 1 (XT1) • LCD ports Segment output 54 (S00 to S53) Common output 4 (COM0 to COM3) Bias terminals for LCD driver 3 (V1 to V3) Other functions Input/output ports 54 (P3n, PAn, PBn, PCn, PDn, PEn, PFn,) Input ports 7 (PLn) • Dedicated oscillator ports 2 (CF1, CF2) • Reset pin 1 (RES) • Power pins 6 (VSS1 to VSS3, VDD1 to VDD3) LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports Small Signal Detection (MIC signals etc) 1) Counts pulses with the level which is greater than a preset value 2) 2-bit counter Timers • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels Mode 1: 16-bit timer with an 8-bit prescaler • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes • Day and time counter 1) Using with a base timer, it can be used as 65000 day + minute + second counter. No.A1156-2/26 LC87F7DC8A High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) UART1 • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator UART2 • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator AD Converter: 12 bits × 15 channels PWM: Multi frequency 12-bit PWM × 2 channels Remote Control Receiver Circuit1 1) Noise rejection function (Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.) 2) Supporting reception formats with a guide-pulse of half-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) 4) X’tal HOLD mode release function Remote Control Receiver Circuit2 1) Noise rejection function (Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.) 2) Supporting reception formats with a guide-pulse of half-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) 4) X’tal HOLD mode release function Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. No.A1156-3/26 LC87F7DC8A Interrupts • 31 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/remote control receiver1 4 0001BH H or L INT3/base timer/INT5/remote control receiver2 5 00023H H or L T0H/INT6 6 0002BH H or L T1L/T1H/INT7 7 00033H H or L SIO0/UART1 receive/UART2 receive/T8L/T8H 8 0003BH H or L SIO1/UART1 transmit/UART2 transmit 9 00043H H or L ADC/MIC/T6/T7/PWM4/PWM5 10 0004BH H or L Port 0/T4/T5 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the diagram above). Subroutine Stack Levels: 2048 levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • RC oscillation circuit (internal): For system clock • CF oscillation circuit: For system clock, with internal Rf • Crystal oscillation circuit: For low-speed system clock, with internal Rf • Frequency variable RC oscillation circuit (internal): For system clock 1) Adjustable in ±4% (typ.) step from a selected center frequency. 2) Measures oscillation clock using a input signal from XT1 as a reference. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (Some parts of the serial transfer function stops operation.) 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt Continued on next page. No.A1156-4/26 LC87F7DC8A Continued from preceding page. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and the remote control receiver circuit. 1) The CF, RC, and frequency variable RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the remote control receiver circuit On-chip Debugger • Supports software debugging with the IC mounted on the target board. Package Form • QIP100E(14×20): Lead-free type • TQFP100(14×14): Lead-free type/Halogen-free type Development Tools • On-chip debugger: TCB87-TypeB + LC87F7DC8A Flash ROM Programming Boards Package Programming boards QIP100E(14×20) W87FQ100 TQFP100(14×14) W87FSQ100 Flash ROM Programmer Maker Model Supported version Device (Note 2) LC87F7DC8A AF9708 Single AF9709/AF9709B/AF9709C (Including product of Ando Electric Co., Ltd) Flash Support Group, Inc. AF9723/AF9723B(Main body) (FSG) (Including product of Ando Gang (Note 2) Electric Co., Ltd) LC87F7DC8A AF9833(Unit) (Including product of Ando (Note 2) Electric Co., Ltd) AF9101/AF9103(Main body) Flash Support Group, Inc. (FSG) Onboard (FSG) + Single/Gang SIB87(interface driver) Our company (Note 1) LC87F7DC8A (Our company model) Single/Gang Our company (Note 2) SKK/SKK Type B Application Version (SANYO FWS) After 1.04 Onboard SKK-DBG Type B Chip Data Version Single/Gang (SANYO FWS) After 2.16 LC87F7DC8A Note 1: With the FSG onboard programmer (AF9101/AF9103) and the serial interface driver provided by Our company, PC-less standalone onboard programming is possible Note 2: Depending on programming conditions, it is necessary to use a dedicated programming device and a program. Please contact Our company or FSG if you have any questions or difficulties regarding this matter. No.A1156-5/26 LC87F7DC8A Package Dimensions unit : mm (typ) 3151A 23.2 0.8 20.0 51 50 100 31 14.0 81 1 17.2 80 30 0.65 0.15 0.3 0.1 3.0max (2.7) (0.58) SANYO : QIP100E(14X20) Package Dimensions unit : mm (typ) 3274 75 0.5 16.0 14.0 51 50 100 26 14.0 16.0 76 1 0.5 0.2 25 0.125 1.2max 0.1 (1.0) (1.0) SANYO : TQFP100(14X14) No.A1156-6/26 V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52 P35/INT5/T1IN/URX2/S53 P00/DGBP0 P01/DGBP1 P02/DGBP2 P03/INT6 P04/INT7 P05/CKO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN/RMIN S0/PA0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3/PL6/AN14/DBGP2 S47/PF7/INT7 S46/PF6/INT6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5 LC87F7DC8A Pin Assignments LC87F7DC8A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 Top view QIP100E(14×20) “Lead-free Type” No.A1156-7/26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 LC87F7DC8A LC87F7DC8A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN/RMIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN S47/PF7 V3/PL6/AN14/DBGP2 V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/S52 P35/INT5/T1IN/S52 P00/DGBP0 P01/DGBP1 P02/T8LO/DGBP2 P03/T8HO P04 P05/CKO P06/T6O P07/T7O P10/SO0 Top view TQFP100(14×14) “Lead-free type/Halogen-free type” No.A1156-8/26 LC87F7DC8A System Block Diagram Interrupt control IR PLA Standby control Flash ROM RC VMRC Clock generator CF PC X’tal ACC B register C register ALU SIO0 Bus interface SIO1 Port 0 Timer 0 (High speed clock counter) Port 1 Timer 1 Port 3 PSW RAR Base timer Port 7 LCD Controller Port 8 INT0 to 7 Noise Rejection Filter ADC Timer 4 Small signal detector Timer 5 Timer 6 UART1 UART2 PWM4/5 Timer 7 Remote control receiver circuit 1 Timer 8 Remote control receiver circuit 2 Day and time counter RAM Stack pointer Watchdog timer On-chip debugger No.A1156-9/26 LC87F7DC8A Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 I/O Description Option - - power supply pin No - + power supply pin No • 8-bit I/O port Yes VDD2 VDD3 Port 0 I/O • I/O specifiable in 1-bit units P00 to P07 • Pull-up resistors can be turned on and off in 1-bit units. • Input for HOLD release • Input for port 0 interrupt • Shared pins P03: INT6 input P04: INT7 input P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output On chip debugger pins: DBGP0 to DBGP2(P00 to P02) Port 1 I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 3 P30 to P35 I/O • 6-bit I/O port Yes • Segment output for LCD • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P30: PWM4 output/INT6 input/timer 0L capture 1 input P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit/INT7 input/timer 0H capture 1 input P35: UART2 receive Interrupt acknowledge type Rising Falling INT4 enable enable INT5 enable enable INT6 enable INT7 enable Rising & H level L level enable disable disable enable disable disable enable enable disable disable enable enable disable disable Falling Continued on next page. No.A1156-10/26 LC87F7DC8A Continued from preceding page. Pin Name Port 7 I/O I/O Description Option • 4-bit I/O port No • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71) Interrupt acknowledge type Port 8 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling • 8-bit I/O port No • I/O specifiable in 1-bit units P80 to P87 • Shared pins AD converter input ports: AN0 to AN7 Small signal detector input port: MICIN (P87) S0/PA0 to I/O I/O I/O I/O I/O No • Segment output for LCD No • Segment output for LCD No • Can be used as general-purpose I/O port (PE) S39/PE7 S40/PF0 to • Segment output for LCD • Can be used as general-purpose I/O port (PD) S31/PD7 S32/PE0 to No • Can be used as general-purpose I/O port (PC) S23/PC7 S24/PD0 to • Segment output for LCD • Can be used as general-purpose I/O port (PB) S15/PB7 S16/PC0 to No • Can be used as general-purpose I/O port (PA) S7/PA7 S8/PB0 to • Segment output for LCD I/O • Segment output for LCD No • Can be used as general-purpose I/O port (PF) S47/PF7 PF6: INT6 input PF7: INT7 input COM0/PL0 to I/O No • Can be used as general-purpose input port (PL) COM3/PL3 V1/PL4 to • Common output for LCD I/O • LCD output bias power supply No • Can be used as general-purpose input port (PL) V3/PL6 • Shared pins AD converter input ports: AN12 (V1) to AN14 (V3) On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3) RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin No • Shared pins General-purpose input port AD converter input port: AN10 XT2 I/O Must be connected to VDD1 if not to be used. • 32.768kHz crystal oscillator output pin No • Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. CF1 Input CF2 Output Ceramic resonator input pin No Ceramic resonator output pin No No.A1156-11/26 LC87F7DC8A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor P00 to P07 each bit 1 2 Nch-open drain Programmable P10 to P17 each bit 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable Programmable P30 to P35 each bit CMOS Programmable P70 - No Nch-open drain P71 to P73 - No CMOS Programmable P80 to P87 - No Nch-open drain No S0/PA0 to S47/PF7 - No CMOS Programmable COM0/PL0 to - No Input only No COM3/PL3 V1/PL4 to V3/PL6 - No Input only No XT1 - No Input only No XT2 - No Output for 32.768kHz crystal oscillator No (Nch-open drain when in general-purpose output mode) User Option List Option Name Option Type P00 to P07 Mask Version *1 Flash Version Option Selected in Specified item Units of CMOS each bit Nch-open drain Port output form P10 to P17 CMOS each bit Nch-open drain P30 to P35 CMOS each bit Nch-open drain Program start address - × *2 00000H 1FF00H *1: Mask option selection - No change possible after the mask is completed. *2: Program start address of the mask version is 00000h. LSI VDD1 Power supply For backup *2 VDD2 VDD3 VSS1 VSS2 VSS3 *1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. *2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. No.A1156-12/26 LC87F7DC8A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply VDD max VDD1, VDD2, VDD3 VDD1=VDD2=VDD3 V1/PL4, V2/PL5, VDD1=VDD2=VDD3 voltage supply voltage for VLCD LCD V3/PL6 Input voltage VI(1) Port L XT1, CF1, RES Input/output VIO(1) voltage min typ max -0.3 +6.5 -0.3 VDD -0.3 VDD+0.3 -0.3 VDD+0.3 unit V Ports 0, 1, 3, 7, 8 Ports A, B, C Ports D, E, F XT2 Peak output IOPH(1) Ports 0, 1, 32 to 35 current • CMOS output selected • Current at each pin IOPH(2) Ports 30, 31 • CMOS output selected • Current at each pin IOPH(3) Ports 71 to 73 Current at each pin IOPH(4) Ports A, B, C Current at each pin Ports D, E, F High level output current Mean output IOMH(1) Ports 0, 1, 32 to 35 current (Note 1-1) • CMOS output selected • Current at each pin IOMH(2) Ports 30, 31 • CMOS output selected • Current at each pin IOMH(3) Ports 71 to 73 Current at each pin IOMH(4) Ports A, B, C Current at each pin Ports D, E, F -20 -5 -5 -7.5 -15 -3 -3 Total output ΣIOAH(1) Ports 0, 1, 32 to 35 Total of all pins -25 current ΣIOAH(2) Ports 30, 31 Total of all pins -25 -45 ΣIOAH(3) Ports 0, 1, 3 Total of all pins ΣIOAH(4) Ports 71 to 73 Total of all pins -5 ΣIOAH(5) Ports A, B, C Total of all pins -25 ΣIOAH(6) Ports D, E, F Total of all pins -25 ΣIOAH(7) Ports A, B, C Total of all pins Ports D, E, F -45 mA Peak output IOPL(1) Ports 0, 1, 32 to 35 Current at each pin 20 current IOPL(2) Ports 30, 31 Current at each pin 30 IOPL(3) Ports 7, 8 Current at each pin XT2 IOPL(4) Ports A, B, C Current at each pin Ports D, E, F Low level output current -10 10 10 Mean output IOML(1) Ports 0, 1, 32 to 35 Current at each pin 15 current IOML(2) Ports 30, 31 Current at each pin 20 Ports 7, 8 Current at each pin (Note 1-1) IOML(3) XT2 IOML(4) Ports A, B, C Current at each pin Ports D, E, F 7.5 7.5 Total output ΣIOAL(1) Ports 0, 1, 32 to 35 Total of all pins 45 current ΣIOAL(2) Ports 30, 31 Total of all pins 45 ΣIOAL(3) Ports 0, 1, 3 Total of all pins 80 ΣIOAL(4) Ports 7, 8 Total of all pins XT2 ΣIOAL(5) Ports A, B, C Total of all pins 45 ΣIOAL(6) Ports D, E, F Total of all pins 45 ΣIOAL(7) Ports A, B, C Total of all pins Ports D, E, F Maximum power dissipation 20 Pd max QIP100E(14×20) Ta=-40 to +85°C TQFP100(14×14) Ta=-40 to +85°C 80 mW Note 1-1: The mean output current is a mean value measured over 100ms. Continued on next page. No.A1156-13/26 LC87F7DC8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Operating ambient Topr temperature Storage ambient min typ max -40 +85 -55 +125 unit °C Tstg temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Range at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] unit VDD(2) 0.356μs ≤ tCYC ≤ 200μs 2.5 5.5 VDD(3) 0.712μs ≤ tCYC ≤ 200μs 2.2 5.5 2.0 5.5 VHD VDD1=VDD2=VDD3 VDD1 supply voltage High level input max 5.5 supply voltage Memory sustaining typ 3.0 VDD(1) (Note 2-1) min 0.237μs ≤ tCYC ≤ 200μs Operating RAM and register contents sustained in HOLD mode. VIH(1) voltage Ports 0, 3, 8 Output disabled 2.2 to 5.5 0.3VDD 2.2 to 5.5 0.3VDD 2.2 to 5.5 0.85VDD VDD 2.2 to 5.5 0.75VDD VDD 2.2 to 5.5 0.9VDD VDD 2.2 to 5.5 0.75VDD 4.0 to 5.5 VSS VDD 0.15VDD +0.4 2.2 to 4.0 VSS 4.0 to 5.5 VSS 2.2 to 4.0 VSS 0.2VDD 2.2 to 5.5 VSS 0.45VDD 2.2 to 5.5 VSS 0.25VDD 2.2 to 5.5 VSS 2.2 to 5.5 VSS 0.25VDD 3.0 to 5.5 0.237 200 2.5 to 5.5 0.356 200 2.2 to 5.5 0.712 200 • CF2 pin open 3.0 to 5.5 0.1 12 • System clock frequency 2.5 to 5.5 0.1 8 2.2 to 5.5 0.1 4 • CF2 pin open 3.0 to 5.5 0.2 24.4 • System clock frequency 2.5 to 5.5 0.2 16 2.2 to 5.5 0.2 8 Ports A, B, C, D, E, F Port L VIH(2) Port 1 • Output disabled Ports 71 to 73 • When INT1VTSL=0 (P71 only) P70 port input/ +0.7 +0.7 VDD VDD interrupt side VIH(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIH(4) P87 small signal Output disabled input side VIH(5) P70 watchdog timer Output disabled side Low level input VIH(6) XT1,XT2,CF1, RES VIL(1) Ports 0, 3, 8 voltage Output disabled Ports A, B, C, D, E, F Port L VIL(2) Port 1 • Output disabled Ports 71 to 73 • When INT1VTSL=0 (P71 only) P70 port input/ interrupt side VIL(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIL(4) P87 small signal Output disabled input side VIL(5) P70 watchdog timer Output disabled side VIL(6) Instruction cycle XT1,XT2,CF1,RES tCYC time (Note 2-2) External system clock frequency FEXCF(1) CF1 V 0.2VDD 0.1VDD +0.4 0.8VDD -1.0 μs division ratio=1/1 • External system clock MHz duty=50±5% division ratio=1/2 Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. No.A1156-14/26 LC87F7DC8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Oscillation FmCF(1) CF1, CF2 frequency range • 12MHz ceramic oscillation • See Fig. 1. FmCF(2) CF1, CF2 (Note 2-3) • 8MHz ceramic oscillation • See Fig. 1. FmCF(3) CF1, CF2 • 4MHz ceramic oscillation • See Fig. 1. FmRC Internal RC oscillation FmVMRC(1) • Frequency variable RC min typ max 3.0 to 5.5 12 2.5 to 5.5 8 2.2 to 5.5 4 2.2 to 5.5 0.3 1.0 unit 2.0 source oscillation MHz • When VMRAJ2 to 0=4, 2.2 to 5.5 10 2.2 to 5.5 4 2.2 to 5.5 32.768 VMFAJ2 to 0=0, VMSL4M=0 FmVMRC(2) • Frequency variable RC source oscillation • When VMRAJ2 to 0=4, VMFAJ2 to 0=0, VMSL4M=1 FsX’tal XT1, XT2 • 32.768kHz crystal oscillation • See Fig. 2. Frequency OpVMRC(1) When VMSL4M=0 variable RC OpVMRC(2) When VMSL4M=1 oscillation kHz 2.2 to 5.5 8 10 12 2.2 to 5.5 3.5 4 4.5 2.2 to 5.5 8 24 64 2.2 to 5.5 1 4 8 MHz usable range Frequency VmADJ(1) Each step of VMRAJn (Wide range) variable RC oscillation VmADJ(2) % Each step of VMFAJn adjustment (Small range) range Note 2-3: See Tables 1 and 2 for the oscillation constants. Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 3, 7, 8 • Output disabled Ports A, B, C • Pull-up resistor off Ports D, E, F • VIN=VDD (Including output Tr's Port L typ max unit 2.2 to 5.5 1 2.2 to 5.5 1 2.2 to 5.5 1 off leakage current) IIH(2) RES VIN=VDD IIH(3) XT1, XT2 • For input port specification • VIN=VDD Low level input min IIH(4) CF1 VIN=VDD 2.2 to 5.5 IIH(5) P87 small signal 4.5 to 5.5 4.2 8.5 15 input side VIN=VBIS+0.5V (VBIS: Bias voltage) 2.2 to 4.5 1.5 5.5 10 Ports 0, 1, 3, 7, 8 • Output disabled Ports A, B, C • Pull-up resistor off Ports D, E, F • VIN=VSS (Including output Tr's 2.2 to 5.5 -1 2.2 to 5.5 -1 2.2 to 5.5 -1 IIL(1) current Port L 15 off leakage current) IIL(2) RES VIN=VSS IIL(3) XT1, XT2 • For input port specification • VIN=VSS IIL(4) CF1 VIN=VSS 2.2 to 5.5 -15 IIL(5) P87 small signal VIN=VBIS-0.5V (VBIS : Bias voltage) 4.5 to 5.5 -15 -8.5 -4.2 2.2 to 4.5 -10 -5.5 -1.5 input side µA Continued on next page. No.A1156-15/26 LC87F7DC8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ High level output VOH(1) Ports 0, 1, IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) 32 to 35 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 IOH=-10mA 4.5 to 5.5 VDD-1.5 VOH(5) IOH=-1.6mA 3.0 to 5.5 VDD-0.4 VOH(6) IOH=-1mA 2.2 to 5.5 VDD-0.4 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 VOH(3) VOH(4) VOH(7) Ports 30, 31 Ports 71 to 73 VOH(8) VOH(9) Ports A, B, C IOH=-1mA 4.5 to 5.5 VDD-1 VOH(10) Ports D, E, F IOH=-0.4mA 3.0 to 5.5 VDD-0.4 VDD-0.4 VOH(11) Low level output voltage max IOH=-0.2mA 2.2 to 5.5 VOL(1) Ports 0, 1, IOL=10mA 4.5 to 5.5 1.5 VOL(2) 32 to 35 IOL=1.6mA 3.0 to 5.5 0.4 2.2 to 5.5 0.4 VOL(3) Ports 30,31 (PWM function IOL=1mA output mode) VOL(4) Ports 30, 31 IOL=30mA 4.5 to 5.5 1.5 VOL(5) (Port function IOL=5mA 3.0 to 5.5 0.4 IOL=2.5mA 2.2 to 5.5 0.4 VOL(6) LCD output voltage output mode) VOL(7) Ports 7, 8 IOL=1.6mA 3.0 to 5.5 0.4 VOL(8) XT2 IOL=1mA 2.2 to 5.5 0.4 VOL(9) Ports A, B, C IOL=1.6mA 3.0 to 5.5 0.4 VOL(10) Ports D, E, F IOL=1mA 2.2 to 5.5 0.4 VODLS S0 to S53 • IO=0mA regulation unit • VLCD, 2/3VLCD,1/3VLCD level output 2.2 to 5.5 0 ±0.2 2.2 to 5.5 0 ±0.2 V • See Fig. 8. VODLC COM0 to COM3 • IO=0mA • VLCD, 2/3VLCD,1/2VLCD, 1/3VLCD level output • See Fig. 8. LCD bias resistor RLCD(1) Resistance per See Fig. 8. one bias resister RLCD(2) Resistance per 2.2 to 5.5 60 2.2 to 5.5 30 See Fig. 8. one bias resister kΩ 1/2 mode Resistance of Rpu(1) Ports 0, 1, 3, 7 pull-up MOS Tr. Rpu(2) Ports A, B, C VOH=0.9VDD Ports D, E, F Hysterisis voltage VHYS(1) Ports 1, 7 RES VHYS(2) P87 small signal CP All pins 15 35 80 2.2 to 5.5 18 50 150 2.2 to 5.5 0.1VDD 2.2 to 5.5 0.1VDD 2.2 to 5.5 10 V input side Pin capacitance 4.5 to 5.5 • For pins other than that under test: VIN=VSS • f=1MHz pF • Ta=25°C Input sensitivity Vsen P87 small signal input side 2.2 to 5.5 0.12VDD Vp-p No.A1156-16/26 LC87F7DC8A Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions Input clock VDD[V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. tSCKH(1) 2.2 to 5.5 pulse width tSCKHA(1) tCYC 4 • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.2 to 5.5 pulse width tSCKHA(2) 1/2 • Continuous data tSCKH(2) transmission/reception mode +2tCYC • CMOS output selected • See Fig. 6. Data setup time Serial input unit 1 • Continuous data transmission/reception mode tsDI(1) SB0(P11), SI0(P11) tSCKH(2) +(10/3) tCYC tCYC • Must be specified with respect to rising edge of 2.2 to 5.5 0.03 2.2 to 5.5 0.03 SIOCLK. Data hold time Output clock Input clock Output delay Serial output max 1 • See Fig. 6. Serial clock typ 2 pulse width High level min • See Fig. 6. thDI(1) tdD0(1) time SO0(P10), SB0(P11) • Continuous data transmission/reception mode 2.2 to 5.5 • (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode • (Note 4-1-3) tdD0(3) 2.2 to 5.5 (1/3)tCYC +0.05 μs 1tCYC +0.05 (Note 4-1-3) 2.2 to 5.5 (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.A1156-17/26 LC87F7DC8A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) typ See Fig. 6. tCYC 1 tSCK(4) SCK1(P15) • CMOS output selected 2 • See Fig. 6. Low level tSCKL(4) 2.2 to 5.5 pulse width High level 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time unit 1 tSCKH(3) Frequency max 2 2.2 to 5.5 pulse width High level min pulse width Output clock Serial clock VDD[V] tsDI(2) SB1(P14), SI1(P14) • Must be specified with respect to rising edge of 2.2 to 5.5 0.03 2.2 to 5.5 0.03 SIOCLK. Data hold time • See Fig. 6. thDI(2) Output delay time tdD0(4) SO1(P13), Serial output SB1(P14) • Must be specified with μs respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output (1/3)tCYC 2.2 to 5.5 +0.05 state change in open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 INT2(P72), min typ max unit are enabled. INT4(P30 to P33), 2.2 to 5.5 1 2.2 to 5.5 2 2.2 to 5.5 64 2.2 to 5.5 256 2.2 to 5.5 1 2.2 to 5.5 4 2.2 to 5.5 200 INT5(P34 to P35), INT6(P30), INT7(P34) tPIH(2) INT3(P73) when • Interrupt source flag can be set. tPIL(2) noise filter time • Event inputs for timer 0 are constant is 1/1 tPIH(3) INT3(P73) when • Interrupt source flag can be set. tPIL(3) noise filter time • Event inputs for timer 0 are constant is 1/32 enabled. tPIH(4) INT3(P73) when • Interrupt source flag can be set. tPIL(4) noise filter time • Event inputs for timer 0 are constant is 1/128 tPIH(5) MICIN(P87) tPIL(5) tPIH(6) tPIL(7) enabled. Condition that signal is accepted to small signal detection counter. RMIN(P73) tPIL(6) Condition that signal is accepted to remote control receiver circuit. RES tCYC enabled. Resetting is enabled. RMCK (Note5-1) μs Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit. No.A1156-18/26 LC87F7DC8A AD Converter Characteristics at VSS1 = VSS2 = VSS3 =0V <12bits AD Converter Mode at Ta =-xx to +xx°C> To be determined after evaluation Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P80) to Absolute ET AN7(P87), AN8(P70), accuracy AN9(P71), Conversion AN10(XT1), tCAD AN11(XT2) time min typ max unit 12 bit (Note 6-1) LSB (Note 6-1) Ta =-10 to +50°C • See Conversion time calculation formulas. (Note 6-2) μs Ta =-10 to +50°C • See Conversion time calculation formulas. (Note 6-2) Analog input VAIN VSS voltage range Analog port IAINH VAIN=VDD input current IAINL VAIN=VSS VDD 1 -1 V μA <8bits AD Converter Mode at Ta =-30 to +70°C> Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(P80) to Absolute ET AN7(P87), accuracy AN8(P70), Conversion AN9(P71), TCAD time Analog input min typ 3.0 to 5.5 (Note 6-1) formulas. AN11(XT2) (Note 6-2) unit bit 3.0 to 5.5 • See Conversion time calculation AN10(XT1), max 8 1.5 4.0 to 5.5 μs 3.0 to 5.5 VAIN 3.0 to 5.5 voltage range LSB Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 VSS VDD 1 -1 V μA <Conversion time calculation formulas> 12bits AD Converter Mode: TCAD(Conversion time)=((52/(division ratio)) + 2) × (1/3) ×tCYC 8bits AD Converter Mode: TCAD(Conversion time)=((32/(division ratio)) + 2) × (1/3) ×tCYC <Recommended Operating Conditions> External Operating supply oscillation voltage range FmCF [MHz] VDD [V] System division ratio Cycle time (SYSDIV) tCYC [ns] 4.0 to 5.5 1/1 3.0 to 5.5 1/1 AD division AD conversion time (tCAD) [μs] ratio (ADDIV) 12bit AD 8bit AD 250 1/8 TBD 21.5 250 1/16 TBD 42.8 12 Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1156-19/26 LC87F7DC8A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode Symbol Specification Conditions VDD[V] • FmCF=12MHz ceramic oscillation mode consumption VDD1 =VDD2 current =VDD3 • System clock set to 12MHz side (Note 7-1) IDDOP(1) Pin/ Remarks IDDOP(2) • FmX’tal=32.768kHz crystal oscillation mode min typ max 4.5 to 5.5 7.4 19.9 3.0 to 3.6 4.8 10.9 4.5 to 5.5 5.9 14.9 3.0 to 3.6 3.9 8.8 2.5 to 3.0 3 6.8 4.5 to 5.5 3.4 8.5 3.0 to 3.6 2.4 5.3 2.2 to 3.0 2.0 4.4 4.5 to 5.5 0.6 3.1 3.0 to 3.6 0.4 1.7 2.2 to 3.0 0.3 1.35 4.5 to 5.5 6.5 20.0 3.0 to 3.6 4.2 12.0 4.5 to 5.5 3.1 11.5 3.0 to 3.6 2.0 6.6 2.2 to 3.0 1.6 3.5 4.5 to 5.5 44.4 128.7 3.0 to 3.6 26.1 56.9 2.2 to 3.0 13.0 43.3 unit • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(3) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDOP(4) • System clock set to 8MHz side • Internal RC oscillation stopped. IDDOP(5) • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(6) • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDOP(7) • System clock set to 4MHz side • Internal RC oscillation stopped. IDDOP(8) • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(9) • FmCF=0Hz (oscillation stopped) mA • FmX’tal=32.768kHz crystal oscillation mode IDDOP(10) IDDOP(11) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(12) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. IDDOP(13) • System clock set to 10MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(14) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(15) • Internal RC oscillation stopped. • System clock set to 4MHz with IDDOP(16) frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(17) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped. IDDOP(19) • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio μA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1156-20/26 LC87F7DC8A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) Specification Pin/ Conditions Remarks VDD[V] • HALT mode consumption VDD1 =VDD2 current =VDD3 • FmX’tal=32.768kHz crystal oscillation mode (Note 7-1) • FmCF=12MHz ceramic oscillation mode min typ max 4.5 to 5.5 3.2 8.5 3.0 to 3.6 1.9 4.4 4.5 to 5.5 2.3 6.2 3.0 to 3.6 1.4 3.1 2.5 to 3.0 1.0 2.5 4.5 to 5.5 1.4 3.9 3.0 to 3.6 0.8 1.8 2.2 to 3.0 0.6 1.3 unit • System clock set to 12MHz side IDDHALT(2) • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(3) • HALT mode • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(4) • System clock set to 8MHz side • Internal RC oscillation stopped. IDDHALT(5) • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(6) • HALT mode • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(7) • System clock set to 4MHz side • Internal RC oscillation stopped. IDDHALT(8) • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(9) • HALT mode 4.5 to 5.5 0.3 1.3 3.0 to 3.6 0.18 0.75 2.2 to 3.0 0.14 0.54 4.5 to 5.5 2.7 7.1 3.0 to 3.6 1.7 4.6 4.5 to 5.5 1.3 3.5 3.0 to 3.6 0.8 1.75 2.2 to 3.0 0.6 1.2 4.5 to 5.5 19.0 100.3 3.0 to 3.6 7.9 38.0 2.2 to 3.0 4.9 26.0 • HOLD mode 4.5 to 5.5 0.14 32.5 • CF1=VDD or open (External clock mode) 3.0 to 3.6 0.03 12.0 14.0 • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(10) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped. IDDHALT(11) • 1/2 frequency division ratio IDDHALT(12) mA • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. IDDHALT(13) • System clock set to 10MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDHALT(14) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(15) • Internal RC oscillation stopped. • System clock set to 4MHz with IDDHALT(16) frequency variable RC oscillation • 1/1 frequency division ratio IDDHALT(17) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped. IDDHALT(19) • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) VDD1 IDDHOLD(3) 2.2 to 3.0 0.01 Timer HOLD IDDHOLD(4) • Timer HOLD mode 4.5 to 5.5 15.5 58.0 mode IDDHOLD(5) • CF1=VDD or open (External clock mode) 3.0 to 3.6 6.3 32.0 2.2 to 3.0 3.6 20.0 consumption current IDDHOLD(6) μA • FmX’tal=32.768kHz crystal oscillation mode Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.A1156-21/26 LC87F7DC8A F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Parameter Onboard Symbol IDDFW(1) Specification Pin/Rem Conditions arks VDD1 programming VDD[V] min typ max unit • 128-byte programming • Erasing current included 3.0 to 5.5 25 40 mA 3.0 to 5.5 22.5 45 ms current Programming tFW(1) • 128-byte programming time • Erasing current included • Time for setting up 128-byte data is excluded. UART (Full Duplex) Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Transfer ate UBR UTX(P32), 2.2 to 5.5 URX(P33) min typ max 16/3 8192/3 unit tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR No.A1156-22/26 LC87F7DC8A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Vendor Frequency Name 12MHz MURATA 8MHz MURATA 4MHz Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time C1 C2 Rf1 Rd1 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE12M0G52-R0 (10) (10) Open CSTCE8M00G52-R0 (10) (10) Open CSTLS8M00G52-R0 (15) (15) Open CSTCR4M00F53-R0 (15) (15) Open CSTLS4M0053-B0 (15) (15) Open Remarks Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator MURATA The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Vendor Name Frequency Name EPSON 32.768kHz Circuit Constant Oscillator Operating C3 C4 Rf2 Rd2 [pF] [pF] [Ω] [Ω] Voltage Range [V] Oscillation Stabilization Time typ max [s] [s] Remarks MC-306 TOYOCOM The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. XT1 CF2 CF1 Rf1 Rf2 Rd1 C1 C2 XT2 Rd2 C3 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit No.A1156-23/26 LC87F7DC8A 0.5VDD Figure 3 AC Timing Measurement Point VDD Operating VDD lower limit 0V Power supply Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Reset Unpredictable Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal VALID HOLD reset signal absent Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.A1156-24/26 LC87F7DC8A VDD RRES Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200μs after the supply voltage goes beyond the lower limit of the IC's operating voltage. RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1156-25/26 LC87F7DC8A VDD SW : ON/OFF (programmable) RLCD RLCD SW: ON (VLCD=VDD) RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND Figure 8 LCD Bias Resistor ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1156-26/26