Ordering number : ENA1535A LC87F0A08A CMOS LSI 8-bit Microcontroller http://onsemi.com 8K-byte Flash ROM / 256-byte RAM / 36-pin Overview The LC87F0A08A is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 12ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM, 256-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter, a 16-bit timer/counter, a 16-bit timer with a prescaler, a base timer serving as a realtime clock, an asynchronous/synchronous SIO interface, a 12-bit 8-channel AD converter with 12-/8-bit resolution selector, a 20 amplifier, constant-voltage detect interrupt, a comparator, a system clock frequency divider, an internal reset circuit, and a 16-source 9-vector interrupt feature. Features Flash ROM 8192 8 bits Capable of on-board programming with a wide range of supply voltage 2.7 to 5.5V Block-erasable in 128-byte units Writes data in 2-byte units 27 19 28 18 7.0 9.0 RAM 256 9 bits 36 10 1 9 0.65 0.3 0.15 0.1 (1.5) (0.9) 1.7max Package Form QFP36 (77): Lead-free and halogen-free type 0.5 9.0 7.0 QFP36(7X7) * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 24 of this data sheet. Semiconductor Components Industries, LLC, 2013 July, 2013 Ver.1.03 70313HK/61913HKIM 20090907-S00001 No.A1535-1/24 LC87F0A08A Minimum Bus Cycle Time 125ns (8MHz at VDD=2.5V to 5.5V) 250ns (4MHz at VDD=2.5V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) 375ns (8MHz VDD=2.5V to 5.5V) 750ns (4MHz VDD=2.5V to 5.5V) Ports Normal withstand voltage I/O ports whose I/O direction specifiable in 1-bit units: Oscillation/input dedicated ports: External reset pins: Power supply pins: Reference voltage outputs: 28 (P0n, P1n, P2n, P30 to P32, P70) 2 (CF1/XT1, CF2/XT2) 1 (RES) 4 (VSS1, AVSS, VDD1, VDD2) 1 (VREF) Timers Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as PWM outputs) Timer A: 16-bit timer Mode 0: 8-bit timer with an 8-bit programmable prescaler 2 channels Mode 1: 16-bit timer with an 8-bit programmable prescaler Base timer 1) The input clock is selectable from the subclock (32.768kHz crystal oscillation), low-speed RC oscillator clock, system clock, and timer 0 prescaler output. (Release of the X'tal HOLD mode is enabled when the subclock or low-speed RC oscillator clock is selected.) 2) Provided with an 8-bit programmable prescaler. 3) Interrupts programmable in 5 different time schemes. SIO SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) AD Converter AD converter input port with a 20 operational amplifier (1 channel) AD converter input ports (8 channels) 12/8 bits AD converter resolution selectable Constant Voltage Detection Interrupt (CVD) Function 1) Detects VDD voltage fluctuations and generates an interrupt request. 2) The CVD detection level can be selected from 12 levels (2.6V, 2.8V, 3.0V, 3.2V, 3.4V, 3.6V, 3.8V, 4.0V, 4.2V, 4.4V, 4.6V, and 4.8V) through a register. No.A1535-2/24 LC87F0A08A Comparator Comparator input pin (1 channel) Comparator output pin (1 channel) Comparator output set high when (comparator input level) < 1.22V Comparator output set low when (comparator input level) > 1.22V Clock Output Function Generates clocks with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillation clock that is selected as the system clock. Watchdog Timer Generates an internal reset on an overflow occurring in the timer running on the low-speed RC oscillator clock (approx. 30kHz) or subclock. Operating mode at standby is selectable from 3 modes (continue counting/suspend operation/suspend counting with the count value retained) Interrupts 16 sources, 9 vectors 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address is given priority. No. Vector Address Level Interrupt Source 1 00003H X or L INT0/CVD 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/TAL 4 0001BH H or L INT3/BT 5 00023H H or L T0H/TAH 6 0002BH H or L T1L/T1H 7 00033H H or L 8 0003BH H or L SIO1 9 00043H H or L ADC 10 0004BH H or L P0 Priority levels X > H > L When interrupts of the same level occur at the same time, an interrupt with a smaller vector address is given priority. Subroutine Stack Levels: Up to 128levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions 16 bits 8 bits (5 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) 16 bits 8 bits (8 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) Oscillation Circuits Internal oscillation circuits 1) Low-speed RC oscillation circuit: For system clock (approx.30kHz) 2) Medium-speed RC oscillation circuit: For system clock (1MHz) 3) Hi-speed RC oscillation circuit: For system clock (8MHz) System Clock Divider Function Can run on low consumption current. Minimum instruction cycle selectable from 375ns, 750ns, 1.5s, 3.0s, 6.0s, 12.0s, 24.0s, 48.0s, and 96.0s (at 8MHz main clock) No.A1535-3/24 LC87F0A08A Internal Reset Circuit Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level can be selected from 7 levels (1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V and 4.28V). through option configuration. Standby Function HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) Having the watchdog timer or LVD function generate a reset (3) Having an interrupt generated HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC and crystal oscillators automatically stop operation. Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. 2) There are five ways of resetting the HOLD mode: (1) Setting the reset pin to the lower level (2) Having the watchdog timer or LVD function generate a reset (3) Having an interrupt source established at one of the INT0, INT1, INT2 and INT4 pins * INT0 and INT1 can be used in the level sense mode only. (4) Having an interrupt source established at port 0. (5) Having an interrupt source established in the CVD circuit X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. (when X’tal oscillation or low-speed RC oscillation is selected). 1) The CF, low-speed, and medium-speed RC oscillators automatically stop operation. Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. Note: If the base timer is run with low-speed RC oscillation selected as the base timer input clock source and the X’tal HOLD mode is entered, the low-speed RC oscillator retains the state that is established when the X’tal HOLD mode is entered. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Having the watchdog timer or LVD function generate a reset (3) Having an interrupt source established at one of the INT0, INT1, INT2, and INT4 pins * INT0 and INT1 can be used in the level sense mode only. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit (6) Having an interrupt source established in the CVD circuit On-chip Debugger Function Supports software debugging with the IC mounted on the target board. Provides 1 channel of on-chip debugger pin. DBGP0 (P0) Data Security Function Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. No.A1535-4/24 LC87F0A08A Development Tools On-chip debugger: TCB87 type B + LC87F0A08A or TCB87 Type C (3-wire interface cable) + LC87F0A08A Programming Board Package Programming board QFP36(77) W87F0AQ Flash ROM Programmer Vendor Model Single AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) Flash Support Group, Inc. AF9723/AF9723B(Main body) (FSG) (Including Ando Electric Co., Ltd. models) Gang AF9833(Unit) (Including Ando Electric Co., Ltd. models) Supported version Device Rev .02. xx or later LC87F0A08A - - - - (Note 2) LC87F0A08A AF9101/AF9103(Main body) Flash Support Group, Inc. + Onboard (FSG) Our company Single/Gang SIB87(Interface Driver) (Note 1) (Our company model) SKK/SKK Type B Single/Gang Application Version (SANYO FWS) 1.16 or later Onboard SKK-DBG Type B Chip Data Version Single/Gang (SANYO FWS) 2.13 or later Our company LC87F0A08A Note1: PC-less standalone onboard programming is possible using the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87) provided by Our company in pair. Note2: Dedicated programming device and program are required depending on the programming conditions. Contact Our company or FSG if you have any questions or difficulties regarding this matter. Package Dimensions unit : mm (typ) 3162C 27 0.5 9.0 7.0 19 28 7.0 9.0 18 36 10 1 9 0.65 0.3 0.15 (1.5) 0.1 1.7max (0.9) SANYO : QFP36(7X7) No.A1535-5/24 LC87F0A08A 27 26 25 24 23 22 21 20 19 P06/DBGP01 P05/CKO/DBGP00 P04/AN4 P03/AN3 P02/AN2/CPIM P01/APIP P00/APIM VREF AVSS Pin Assignment 28 29 30 31 32 33 34 35 36 18 17 16 15 14 13 12 11 10 LC87F0A08A P32/AN8 P31/AN7 P30/AN6 P17/T1PWMH/BUZ/INT1/T0HCP P16/T1PWML/INT2/T0IN/CPOUT P15/INT3/T0IN/AN5 P14/INT4/T1IN P13/INT4/T1IN P12/SCK1 P27 P70/INT0/T0LCP/AN9 RES VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO1 P11/SI1/SB1 1 2 3 4 5 6 7 8 9 P07/DBGP02 VDD2 P20 P21 P22 P23 P24 P25 P26 Top view QFP36 (77) “Lead-free and halogen-free Type” QFP36 NAME QFP36 NAME 1 P27 19 AVSS 2 P70/INT0/T0LCP 20 VREF 3 RES 21 P00/AN0 4 VSS1 22 P01/AN1 5 CF1/XT1 23 P02/AN2/CPIM 6 CF2/XT2 24 P03/AN3 7 VDD1 25 P04/AN4 8 P10/SO1 26 P05/CKO/DBGP00 9 P11/SI1/SB1 27 P06/DBGP01 10 P12/SCK1 28 P07/DBGP02 11 P13/INT4/T1IN 29 VDD2 12 P14/INT4/T1IN 30 P20 13 P15/INT3/T0IN/AN5 31 P21 14 P16/T1PWML/INT2/T0IN/CPOUT 32 P22 15 P17/T1PWMH/BUZ/INT1/T0HCP 33 P23 16 P30/AN6 34 P24 17 P31/AN7 35 P25 18 P32/AN8 36 P26 No.A1535-6/24 LC87F0A08A System Block Diagram Interrupt control IR Standby control PLA Flash ROM Low-spee d RC Mediumspeed RC Clock generator CF/XT PC High-spee d RC RES Reset circuit (LVD/POR) ACC Reset control WDT (Low-speed RC) B register C register SIO 1 Bus interface ALU Timer 0 Port 0 Timer 1 Port 1 PSW Timer A Port 2 RAR Base timer Port 3 RAM CVD Port 7 Stack pointer INT0-INT4 (INT3 with noise filter) On-chip debugger ADC 20x amplifier (1 channel) + - Vref Comparator No.A1535-7/24 LC87F0A08A Pin Description Pin Name I/O Description Option VSS1 - - power supply pin No VDD1 - + power supply pin No VDD2 - + power supply pin No AVSS - - power supply pin No VREF O Reference voltage output No Port 0 I/O 8-bit I/O port I/O specifiable in 1-bit units. P00 to P07 Pull-up resistors can be turned on and off in 1-bit units. Pin functions P00 (AN0), P01 (AN1): AD converter input port with 20x operational amplifier Yes P02: AD converter input port (AN2)/comparator input (CPIM) P03: AD converter input port (AN3) P04: AD converter input port (AN4) P05: System clock output/on-chip debugger pin (DBGP00) P06: On-chip debugger pin (DBGP01) P07: On-chip debugger pin (DBGP02) Port 1 I/O 8-bit I/O port I/O specifiable in 1-bit units. P10 to P17 Pull-up resistors can be turned on and off in 1-bit units. Current controllable in 1-bit units. 5mA (default), 10mA, 15mA, no current control Pin functions P10: SIO1 data output P11: SIO1 data input/bus input/output P10, P11 P12: SIO1 clock input/output options P13, P14: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ not available timer 0H capture input P15: INT3 input(with noise filter)/timer 0 event input/timer 0H capture input/ AD converter input port (AN5) P12 to P17 P16: Timer 1 PWML output/INT2 input/HOLD release input/timer 0 event input/ options timer 0L capture input/comparator output (CPOUT) P17: Timer 1 PWMH output/beeper output/INT1 input/HOLD release input/timer 0H capture input available Interrupt acknowledge type Port 2 I/O Rising & Rising Falling INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable INT4 enable enable enable disable disable Falling H level L level 8-bit I/O port I/O specifiable in 1-bit units. Pull-up resistors can be turned on and off in 1-bit units. Yes Current controllable in 1-bit units. 5mA (default), 10mA, 15mA, no current control Port 3 I/O 3-bit I/O port I/O specifiable in 1-bit units. Pull-up resistors can be turned on and off in 1-bit units. Pin functions Yes P30: AD converter input port (AN6) P31: AD converter input port (AN7) P32: AD converter input port (AN8) Continued on next page. No.A1535-8/24 LC87F0A08A Continued from preceding page. Pin Name Port 7 I/O Description Option 1-bit I/O port I/O I/O specifiable P70 Pull-up resistors can be turned on and off. Pin functions P70 : INT0 input/HOLD release input/timer 0L capture input/AD converter input port (AN9) No Interrupt acknowledge type INT0 RES CF1/XT1 I/O Rising Falling enable enable Rising & Falling disable H level L level enable enable External reset input/internal reset output pin No Ceramic oscillator/32.768kHz crystal oscillator input pin I Pin functions No General-purpose input port CF2/XT2 Ceramic oscillator/32.768kHz crystal oscillator output pin I/O Pin functions No General-purpose input port Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option selected in units of 1 bit Option type Output type Pull-up resistor 1 CMOS Programmable 2 Nch-open drain Programmable P10 to P11 - No CMOS Programmable P12 to P177 1 bit 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable No Nch-open drain Programmable P20 to P27 P30 to P32 P70 1 bit 1 bit - No.A1535-9/24 LC87F0A08A Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 =0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply VDD max VDD1=VDD2 voltage Input voltage VI CF1, CF2 Input/output VIO Ports 0, 1, 2 voltage Peak output Ports 3, 7 IOPH(1) Ports 0, 3 current IOPH(2) High level output current CMOS output type selected Per 1 applicable pin Ports 1, 2 CMOS output type selected Per 1 applicable pin Average IOMH(1) Ports 0, 3 output current (Note 1-1) CMOS output type selected Per 1 applicable pin IOMH(2) Ports 1, 2 CMOS output type selected Per 1 applicable pin Total output IOAH(1) Ports 0, 1, 3 current Total current of all applicable pins IOAH(2) Port 2 Total current of all applicable pins IOAH(3) Ports 0, 1, 2, 3 Total current of all applicable Low level output current pins min typ max -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 -20 -7.5 -15 -30 -30 mA -50 IOPL(1) Ports 0, 3 Per 1 applicable pin 20 current IOPL(2) Ports 1, 2 Per 1 applicable pin 20 IOPL(3) Port 7 Per 1 applicable pin 10 Average IOML(1) Ports 0, 3 Per 1 applicable pin 15 output current IOML(2) Ports 1, 2 Per 1 applicable pin 15 IOML(3) Port 7 Per 1 applicable pin 7.5 IOAL(1) Ports 0, 1, 2, 3, 7 Total current of all applicable Total output current Allowable power 80 pins Pd max (1) dissipation QFP36 V -10 Peak output (Note 1-1) unit Ta=-40 to +85C Package alone Pd max (2) Ta=-40 to +85C mW Mounted on thermal resistance test board (Note 1-2) Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 C Note 1-1: The average output current is an average of current values measured over 100ms intervals. Note 1-2: Thermal resistance test board used conforms to SEMI (size: 76.1×114.3×1.6tmm, glass epoxy board). No.A1535-10/24 LC87F0A08A Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Operating supply voltage VDD(1) (Note 2-1) VDD(2) Memory sustaining VHD VDD1=VDD2 VDD1=VDD2 supply voltage High level VIH(1) Low level VIL(1) input voltage unit 5.5 0.735s tCYC 200s 2.5 5.5 RAM and register contents Ports 0, 1, 2, 3 2.0 2.5 to 5.5 CF1, RES Ports 1, 2, 3 P70 VIL(4) max 2.5 P70 VIH(4) typ 0.367s tCYC 200s sustained in HOLD mode input voltage min CF1, RES 0.3VDD VDD +0.7 2.5 to 5.5 0.75VDD 4.0 to 5.5 VSS 2.5 to 4.0 VSS 0.2VDD +0.4 2.5 to 5.5 VSS 0.25VDD Instruction cycle tCYC 2.7 to 5.5 0.245 200 time (Note 2-2) 2.5 to 5.5 0.367 200 2.5 to 5.5 0.735 200 2.7 to 5.5 0.1 12 2.5 to 5.5 0.1 8 (Note 2-1) External system FEXCF CF1 CF2 pin open V VDD 0.1VDD s System clock frequency clock frequency MHz division ratio=1/1 External system clock duty=505% Oscillation FmCF(1) CF1, CF2 frequency range (Note 2-3) 8MHz ceramic oscillation See Fig. 1. FmCF(2) CF1, CF2 4MHz ceramic oscillation See Fig. 1. FmMRC 2.5 to 5.5 8 2.5 to 5.5 4 1/2 of high-speed RC oscillation frequency (RCCTD=0) MHz 2.5 to 5.5 7.44 8.0 8.56 2.5 to 5.5 0.5 1.0 2.0 2.5 to 5.5 15 30 60 (Note 2-4) FmRC Internal medium-speed RC oscillation FmSRC Internal low-speed RC oscillation FsX’tal XT1, XT2 32.768kHz crystal oscillation See Fig. 2. kHz 2.5 to 5.5 32.768 Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: An oscillation stabilization time of 100s or longer must be provided before switching the system clock source after the state of the high-speed RC oscillation circuit is switched from “oscillation stopped” to “oscillation enabled” . No.A1535-11/24 LC87F0A08A Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 2, 3 Port 7, RES min typ max unit Output disabled Pull-up resistor off VIN=VDD (including output TR’s off leakage 2.5 to 5.5 1 2.5 to 5.5 15 current) Low level input IIH(2) CF1 VIN=VDD IIL(1) Ports 0, 1, 2, 3 Port 7, RES Output disabled current A Pull-up resistor off VIN=VSS (including output TR’s off leakage 2.5 to 5.5 -1 current) IIL(2) CF1 VIN=VSS 2.5 to 5.5 -15 High level output VOH(1) Ports 0, 3 IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) IOH=-0.2mA 2.5 to 5.5 VDD-0.4 IOH=-6mA 4.5 to 5.5 VDD-1 IOH=-1.0mA 2.5 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 IOL=1.0mA 2.5 to 5.5 0.4 IOL=8mA 4.5 to 5.5 1.5 IOL=1.0mA 2.5 to 5.5 0.4 VOH(3) Ports 1, 2 VOH(4) Low level output VOL(1) voltage VOL(2) VOL(3) Ports 0, 1, 2, 3 P70 VOL(4) Constant current VOCC V Ports 1, 2 operation enabled VDD -1.0 2.5 to 5.5 1 2.7 to 5.5 4 5 6 2.5 to 2.7 3 5 6 2.7 to 5.5 8 10 12 2.5 to 2.7 6 10 12 pin voltage Constant current ILED(1) port current ILED(2) Ports 1, 2 Per 1 applicable pin only ON time (5mA setting) VO=1.0 to (VDD-1.0) Constant current ILED(3) port current ILED(4) mA (10mA setting) Constant current port current (15mA setting) Pull-up resistance Hysteresis voltage ILED(5) 2.7 to 5.5 LED(1)+LED(3) ILED(6) 2.5 to 2.7 LED(2)+LED(4) Rpu(1) Ports 0, 1, 2, 3 Rpu(2) Port 7 VHYS(1) VOH=0.9VDD CP 4.5 to 5.5 15 35 80 2.5 to 4.5 18 50 230 k Ports 0, 1, 2, 3 P70 RES Pin capacitance V All pins 2.5 to 5.5 0.1VDD V 2.5 to 5.5 10 pF For pins other than that under test VIN=VSS f=1MHz Ta=25C No.A1535-12/24 LC87F0A08A SIO1 Serial I/O Characteristics (Note 4-1) Input clock Symbol Frequency tSCK(1) Low level tSCKL(1) Specification Pin/ Conditions Remarks SCK1(P12) VDD[V] See Fig. 5. 2.5 to 5.5 pulse width High level tSCK(2) SCK1(P12) CMOS output type selected tSCKL(2) 2 1/2 tSCK tSCKH(2) 1/2 pulse width Serial input Data setup time tsDI(1) SI1(P11), SB1(P11) Specified with respect to rising edge of SIOCLK. See Fig. 5. Data hold time unit 1 2.5 to 5.5 pulse width High level max 1 See Fig. 5. Low level typ tCYC tSCKH(1) Frequency min 2 pulse width Output clock Serial clock Parameter thDI(1) 0.05 2.5 to 5.5 0.05 tdDO(1) SO1(P10), Serial output Output delay time SB1(P11) s Specified with respect to falling edge of SIOCLK Specified as the time up to the beginning of output change in (1/3)tCYC 2.5 to 5.5 +0.08 open drain output mode. See Fig. 5. Note 4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), Event inputs for timer 0 or 1 are INT2(P16), enabled. min typ 2.5 to 5.5 1 2.5 to 5.5 2 max unit INT4(P13, P14) tPIH(2) INT3(P15) when noise Interrupt source flag can be set. tPIL(2) filter time constant is Event inputs for timer 0 are 1/1 enabled. tPIH(3) INT3(P15) when noise Interrupt source flag can be set. tPIL(3) filter time constant is Event inputs for timer 0 are 1/32 INT3(P15) when noise Interrupt source flag can be set. tPIL(4) filter time constant is Event inputs for timer 0 are tPIL(5) RES 2.5 to 5.5 64 2.5 to 5.5 256 2.5 to 5.5 200 enabled. tPIH(4) 1/128 tCYC enabled. Resetting is enabled. s No.A1535-13/24 LC87F0A08A AD Converter Characteristics at VSS1 = AVSS = 0V <12bits AD Converter Mode/Ta = -40C to +85C > Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN2(P02) Absolute ET AN3(P03) accuracy AN4(P04) Conversion time AN5(P15) TCAD AN6(P30) (Note 6-1) VAIN See conversion time calculation method. (Note 6-2) AN8(P32) voltage range typ max unit 12 bit 16 3.0 to 5.5 AN7(P31) Analog input min 3.0 to 5.5 4.0 to 5.5 32 115 3.0 to 5.5 64 115 3.0 to 5.5 VSS VREF LSB s V AN9(P70) Analog port IAINH input current IAINL (Note 6-3) VAIN=VDD 3.0 to 5.5 VAIN=VSS 3.0 to 5.5 1 A -1 <8bits AD Converter Mode/Ta = -40C to +85C > Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN2(P02) Absolute ET AN3(P03) (Note 6-1) Conversion time AN5(P15) See “Conversion time AN6(P30) calculation method”. AN7(P31) (Note 6-2) VAIN Analog port IAINH input current IAINL unit bit 1.5 4.0 to 5.5 20 90 3.0 to 5.5 40 90 3.0 to 5.5 VSS VREF LSB s AN8(P32) AN9(P70) voltage range max 8 3.0 to 5.5 AN4(P04) Analog input typ 3.0 to 5.5 accuracy TCAD min (Note 6-3) VAIN=VDD 3.0 to 5.5 VAIN=VSS 3.0 to 5.5 1 V A -1 <Conversion time calculation method> 12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)(1/3)tCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2) (1/3)tCYC <Recommended Operating Conditions> External Operating supply oscillation voltage range (FmCF) (VDD) System division ratio Cycle time (SYSDIV) (tCYC) 4.0V to 5.5V 1/1 3.0V to 5.5V 3.0V to 5.5V AD division AD conversion time (TCAD) ratio (ADDIV) 12bit AD 8bit AD 375ns 1/8 52.3s 32.3s 1/1 375ns 1/16 104.5s 64.5s 1/1 750ns 1/8 104.5s 64.5s CF-8MHz CF-4MHz Note 6-1: The quantization error (1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured when no change occurs in the I/O state of the pins that are adjacent to the analog input channel during AD conversion processing. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: The first AD conversion executed in the 12-bit AD conversion mode after a system reset The first AD conversion executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode Note 6-3: See section 8, “20× amplifier characteristics”, for analog channel 0 (20× amplifier output). No.A1535-14/24 LC87F0A08A Reference Voltage Generator Circuit (VREF) Characteristics at Ta = -40C to +85C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] VREF voltage VREFVO accuracy VREF Ta=-40 to +85C (Note 7-2) Ta=-40 to +60C VREF output Ta=-40 to +85C VREFIO current Operation min typ max unit 2.5 to 4.0 VDD-0.1 VDD 4.0 to 5.5 3.92 4.5 to 5.5 3.96 4.04 2.5 to 5.5 VSS 1 mA 10 s 4.00 4.08 V tVREFW stabilization time 2.5 to 5.5 (Note 7-1) Note 7-1: Refers to the interval between the time VRONZ is set to 0 and the time operation gets stabilized. Note 7-2: An external 4.7F capacitor must be connected to the VREF pin to stabilize the VREF voltage. 20x Amplifier Characteristics at Ta = -40C to +85C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Amplifier gain Operation APGAIN P00/APIM Ta=-40 to +85C See Fig. 7. P01/APIP VREF=4.0V min typ max unit 20 P01=0V, P000V tAPW or P00=0V, P010V stabilization time 1.0 s (Note 8-1) Amplifier input VAPFUL 5.0 voltage full scale 0.16 0.19 (Note 8-1) V Amplifier input VAPIM P00/APIM P01/APIP=0V -VAPFUL 0 voltage range VAPIP P01/APIP P00/APIM=0V 0 VAPFUL Amplifier input port IAPINL P00/APIM P00/APIM=VSS-0.2V input current IAPINH P01/APIP P01/APIP=VDD -1 A 1 Note 8-1: Refers to the interval between the time APON is set to 1 and the time operation gets stabilized. Comparator Characteristics at Ta = -40C to +85C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Comparator VCMVT min typ max unit P02/CPIM threshold voltage 2.5 to 5.5 1.12 2.5 to 5.5 VSS 1.22 1.32 V VDD-1.5 V (Note 9-1) Common mode VCMIN input voltage range Offset voltage VOFF Within common mode input voltage range Response time tRT 2.5 to 5.5 ±10 ±30 mV 2.5 to 5.5 200 600 ns 1.0 s Within common mode input voltage range Input amplitude=100mV Overdrive=50mV Operation stabilization time tCMW 2.5 to 5.5 (Note 9-2) Note 9-1: Comparator output=High level when (P02/CPIM voltage) < VCMVT Comparator output=Low level when (P02/CPIM voltage) > (VCMVT +VOFF) Note 9-2: Refers to the interval between the time CPONZ is set to 0 and the time operation gets stabilized. No.A1535-15/24 LC87F0A08A Power-on Reset (POR) Characteristics at Ta = -40C to +85C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin / Remarks Conditions Option Selected Voltage POR release PORRL voltage Detection voltage POUKS max Option selected 1.67V 1.55 1.67 1.79 1.97V 1.85 1.97 2.09 2.07V 1.95 2.07 2.19 2.37V 2.25 2.37 2.49 2.57V 2.45 2.57 2.69 2.87V 2.75 2.87 2.99 3.86V 3.73 3.86 3.99 4.35V 4.21 4.35 4.49 0.7 0.95 (Note 10-2) PORIS typ (Note 10-1) See Fig. 8. unpredictable area Power supply rise min Power startup time time 100 from VDD=0V to 1.6V unit V ms Note 10-1: The POR release voltage can be selected from 8 levels when the low-voltage detection feature is deselected. Note 10-2: There is an unpredictable area before the transistor starts to turn on. Low-voltage Detection (LVD) Reset Characteristics at Ta = -40C to +85C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin/Remarks Conditions Option Selected Voltage LVD reset voltage LVDET (Note 11-2) 1.91V 1.81 1.91 2.01 2.01V 1.91 2.01 2.11 2.31V 2.21 2.31 2.41 2.51V 2.41 2.51 2.61 2.81V 2.71 2.81 2.91 3.79V 3.69 3.79 3.89 4.28V 4.18 4.28 4.38 LVHYS hysteresis LVUKS unpredictable area Minimum low voltage detection width (response 1.91V 55 2.01V 55 2.31V 55 2.51V 55 2.81V 60 3.79V 65 4.28V 65 See Fig. 9. 0.7 (Note 11-4) TLVDW max Option selected (Note 11-3) Detection voltage typ See Fig. 9. (Note 11-1) LVD voltage min unit V mV 0.95 V LVDET-0.5V See Fig. 10. 0.2 ms sensitivity) Note 11-1: The LVD reset voltage can be selected from 7 levels when the low-voltage detection feature is selected. Note 11-2: The hysteresis voltage is not included in the LVD reset voltage specification value. Note 11-3: There are cases when the LVD reset voltage specification value is exceeded when a greater change in the output level or large current is applied to the port. Note 11-4: There is an unpredictable area before the transistor starts to turn on. No.A1535-16/24 LC87F0A08A Constant Voltage Detection (CVD) Interrupt Characteristics at Ta = -40 to +85C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin/Remarks Conditions Register Selected Voltage CVD detection CVDET min typ max Register selected 2.6V 2.5 2.6 2.7 voltage (Note 12-1) 2.8V 2.7 2.8 2.9 (Note 12-2) (Note 12-3) 3.0V 2.9 3.0 3.1 3.2V 3.1 3.2 3.4 3.4V 3.3 3.4 3.6 3.6V 3.5 3.6 3.8 3.8V 3.7 3.8 4.0 4.0V 3.9 4.0 4.2 4.2V 4.1 4.2 4.4 4.4V 4.3 4.4 4.6 4.6V 4.5 4.6 4.8 4.8V 4.7 4.8 5.0 unit V CVD detection CVHYS voltage hysteresis 2.6V 50 2.8V 50 3.0V 50 3.2V 50 3.4V 50 3.6V 50 3.8V 50 4.0V 50 4.2V 50 4.4V 50 4.6V 50 4.8V 55 mV Detection voltage CVUKS (Note 12-4) TCVDW CVDET-0.5V 0.7 unpredictable area Minimum CVD detection width 0.95 0.8 (response V ms sensitivity) Operation stabilization time tCVDON VDD=2.5 to 5.5V 100 s (Note 12-5) Note 12-1: The CVD detection voltage can be selected from 16 levels. Note 12-2: The hysteresis voltage is not included in the CVD detection voltage specification value. Note 12-3: There are cases when the CVD detection voltage specification value is exceeded when a greater change in the output level or large current is applied to the port. Note 12-4: There is an unpredictable period before the CVD-related transistor starts to turn on. Note 12-5: Refers to the interval between the time CVDRUN is set to 1 and the time operation gets stabilized. No.A1535-17/24 LC87F0A08A Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter Normal mode Symbol IDDOP(1) consumption Specification Pin/ Conditions Remarks VDD1 =VDD2 VDD[V] min typ max unit FmCF=8MHz ceramic oscillation mode System clock set to 8MHz mode 4.5 to 5.5 5.5 11.3 2.5 to 4.5 3.4 9.0 4.5 to 5.5 2.8 6.8 2.5 to 4.5 2.1 5.4 Internal low-/medium-speed RC oscillation current stopped (Note 13-1) Internal high-speed RC oscillation stopped (Note 13-2) Frequency division ratio set to 1/1 FmCF=4MHz ceramic oscillation mode IDDOP(2) System clock set to 4MHz mode Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 mA FsX’tal=32.768kHz crystal oscillation mode IDDOP(3) Internal low-speed RC oscillation stopped 4.5 to 5.5 0.6 1.9 2.5 to 4.5 0.3 1.4 4.5 to 5.5 5.0 9.9 2.5 to 4.5 3.5 8.6 4.5 to 5.5 21.3 89.4 2.5 to 4.5 13.6 64.8 System clock set to internal medium-speed RC oscillation mode Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 FsX’tal=32.768kHz crystal oscillation mode IDDOP(4) Internal low-/medium-speed RC oscillation stopped System clock set to internal high-speed RC oscillation mode Frequency division ratio set to 1/1 External oscillation FsX’tal/FmCF stopped IDDOP(5) System clock set to internal low-speed RC oscillation mode Internal medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 A FsX’tal=32.768kHz crystal oscillation mode IDDOP(6) System clock set to 32.768kHz mode 4.5 to 5.5 22.8 101.5 2.5 to 4.5 10.9 70.0 4.5 to 5.5 2.0 3.2 2.5 to 4.5 1.0 2.3 4.5 to 5.5 1.3 2.2 Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 HALT mode IDDHALT(1) consumption VDD1 =VDD2 HALT mode FmCF=8MHz ceramic oscillation mode current System clock set to 8MHz mode (Note 13-1) Internal low-/medium-speed RC oscillation stopped (Note 13-2) Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDHALT(2) HALT mode FmCF=4MHz ceramic oscillation mode System clock set to 4MHz mode Internal low-/medium-speed RC oscillation mA stopped Internal high-speed RC oscillation stopped 2.5 to 4.5 0.6 1.5 4.5 to 5.5 0.3 1.2 2.5 to 4.5 0.2 0.8 Frequency division ratio set to 1/1 IDDHALT(3) HALT mode FsX’tal=32.768kHz crystal oscillation mode Internal low-speed RC oscillation stopped System clock set to internal medium-speed RC oscillation mode Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 Note 13-1: The consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. Note 13-2: Unless otherwise specified, the consumption current for the LVD circuit is not included. Continued on next page. No.A1535-18/24 LC87F0A08A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(4) consumption Specification Pin/ Conditions Remarks VDD1 =VDD2 VDD[V] FsX’tal=32.768kHz crystal oscillation mode Internal low-/medium-speed RC oscillation current min typ max unit HALT mode 4.5 to 5.5 1.6 2.2 2.5 to 4.5 1.1 1.8 4.5 to 5.5 5.6 43 2.5 to 4.5 3.3 30.4 stopped (Note 13-1) System clock set to internal high-speed RC (Note 13-2) oscillation mode Frequency division ratio set to 1/1 IDDHALT(5) HALT mode External oscillation FsX’tal/FmCF stopped System clock set to internal low-speed RC oscillation mode Internal medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDHALT(6) A HALT mode FsX’tal=32.768kHz crystal oscillation mode 4.5 to 5.5 12.0 69.8 2.5 to 4.5 4.4 44.7 HOLD mode 4.5 to 5.5 0.024 41.0 2.5 to 4.5 0.010 27.2 HOLD mode 4.5 to 5.5 2.9 30.2 System clock set to 32.768kHz mode Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 HOLD mode IDDHOLD(1) consumption current (Note 13-1) VDD1 =VDD2 IDDHOLD(2) LVD option selected (Note 13-2) Timer HOLD IDDHOLD(3) mode consumption current VDD1 =VDD2 IDDHOLD(4) 2.5 to 4.5 2.3 22.3 4.5 to 5.5 9.9 63.2 FsX’tal=32.768kHz crystal oscillation mode 2.5 to 4.5 3.2 39.6 Timer HOLD mode 4.5 to 5.5 2.1 31.6 2.5 to 4.5 1.2 8.4 4.5 to 5.5 29.3 110.2 2.5 to 4.5 20.1 86.3 A FmSRC=30kHz internal low-speed RC (Note 13-1) (Note 13-2) Timer HOLD mode oscillation mode IDDHOLD(5) Timer HOLD mode FmSRC=30kHz internal low-speed RC oscillation mode CVD active mode Note 13-1: The consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. Note 13-2: Unless otherwise specified, the consumption current for the LVD circuit is not included. F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = AVSS = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Onboard IDDFW(1) programming VDD1 min typ max unit Excluding power dissipation in the microcontroller block 2.7 to 5.5 5 10 mA 20 30 ms 40 60 s current Programming tFW(1) Erase mode time tFW(2) Programming mode 2.7 to 5.5 No.A1535-19/24 LC87F0A08A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator MURATA Manufacturing Co., Ltd. Nominal Frequency Circuit Constant Type Oscillator Name C1 C2 Rf Operating Voltage Range Rd Oscillation Stabilization Time [V] typ max [ms] [ms] [pF] [pF] [] [] 4MHz SMD CSTCR4M00G53-R0 (10) (10) Open 3.3k 2.5 to 5.5 0.03 8MHz SMD CSTCE8M00G52-R0 (10) (10) Open 1.5k 2.5 to 5.5 0.02 Remarks C1 and C2 integrated type Characteristics of a Sample Subsystem Clock Oscillation Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit that Uses a Crystal Oscillator EPSON TOYOCOM Nominal Frequency 32.768kHz Circuit Constant Type SMD Oscillator Name MC-306 Operating C1 C2 Rf Rd [pF] [pF] [] [] 7 7 Open 330k Voltage Range [V] 2.5 to 5.5 Oscillation Stabilization Time typ max [ms] [ms] 0.85 Remarks CL value applied: 7pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 3): Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed Till the oscillation gets stabilized after the HOLD mode is released. Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF2/XT2 CF1/XT1 Rf Rd C1 CF/X’tal C2 Figure 1 CF/XT Oscillator Circuit 0.5VDD Figure 2 AC Timing Measurement Point No.A1535-20/24 LC87F0A08A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal medium speed RC oscillation tmsCF/tmsX’tal CF1, CF2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD release signal absent HOLD release signal valid Internal medium speed RC oscillation or internal low speed RC oscillation tmsCF/tmsX’tal CF1, CF2 (Note) State HOLD HALT HOLD Release Signal and Oscillation Stabilization Time Note: When an external oscillation circuit is selected. Figure 3 Oscillation Stabilization Time No.A1535-21/24 LC87F0A08A VDD Note: The external circuit for reset may vary depending on the usage of POR and LVD. See “Reset Function” in the user's manual. RRES RES CRES Figure 4 Sample Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 5 Serial I/O Waveform tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform No.A1535-22/24 LC87F0A08A AMP output AMP output VREF VREF APGAIN APGAIN 0 0 0V -VAPFUL (a) +VAPFUL (b) P00/APIM input P01/APIP input Figure 7 20 Amplifier Characteristics (a) When P01/APIP is 0V, P00/APIM 0V. (b) When P00/APIM is 0V, P01/APIP 0V. (a) POR release voltage (PORRL) (b) VDD Reset period 100s or longer Reset period Reset unknown area (POUKS) RES Figure 8 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) The POR function generates a reset only when the power voltage goes up from the VSS level. No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit as shown below. A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100s or longer. No.A1535-23/24 LC87F0A08A LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset period Reset period Reset unknown area (LVUKS) RES Figure 9 Example of POR + LVD Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) Resets are generated both when power is turned on and when the power level lowers. A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. VDD LVD release voltage LVD detect voltage LVDET-0.5V TLVDW VSS Figure 10 Minimum Low Voltage Detection Width (Example of Voltage Sag/Fluctuation Waveform) ORDERING INFORMATION Device LC87F0A08AU-EB-TLM-H Package QFP36(7X7) (Pb-Free / Halogen Free) LC87F0A08AUEB-NH QFP36(7X7) (Pb-Free / Halogen Free) Shipping (Qty / Packing) 1000 / Tape & Reel 1000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1535-24/24