Ordering number : ENA1335A LC87F2708A CMOS IC FROM 8K byte, RAM 512 byte on-chip 8-bit 1-chip Microcontroller Overview The LC87F2708A is an 8-bit microcotroller that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (onboard programmable), 512-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers or PWMs), a synchronous SIO interface, a high-speed 12-bit PWM, two high-speed pulse width/period counters, a 7-channel AD converter with 12-/8-bit resolution selector, an analog comparator, a watchdog timer, an internal reset circuit, a system clock frequency divider, and a 16-source 10-vector interrupt feature. Features Flash ROM • Capable of on-board programming of voltage source (3.0 to 5.5V) • Block-erasable in 128 byte units • 8192 × 8 bits RAM • 512 × 9 bits * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.01 91609HKIM 20090831-S00003 No.A1335-1/21 LC87F2708A Minimum Bus Cycle Time Note1 • 100ns (10MHz) VDD=2.7 to 5.5V Note2 Minimum Instruction Cycle Time • 300ns (10MHz) VDD=2.7 to 5.5V Note2 Note1: The bus cycle time here refers to the ROM read speed. Note2: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the power-on reset (POR) circuit is 2.87V±0.12V. Ports • I/O ports Ports whose I/O direction can be designated in 1-bit units 11 (P10 to P16, P30 to P33) • Reset pins 1 (RES) • Power pins 2 (VSS1, VDD1) Timers • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter that can provide with PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle output also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (Lower-order 8 bits may be used as PWM) Serial Interface • SIO7: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC) High-Speed 12-bit PWM • System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable • Duty/period programmable • Continuous PWM output/specific count PWM output (automatic stop) selectable High-speed Pulse/Period Counter • HCT1: High-speed pulse width/period counter 1 1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable 2) H-level width/L-level width/period measurement modes selectable 3) Input triggering noise filter • HCT2: High-speed pulse width/period counter 2 1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable 2) Can measure both L-level width and period simultaneously. 3) Input triggering noise filter 4) Input trigger selectable (from 3 signals, i.e., P11/HCT2IN, P31/HCT2IN, and analog comparator output) AD Converter: 12 bits × 7 channels • 12-/8-bits AD converter resolution selectable Analog Comparator • Sends output to the P32/CMPO port (polarity selectable). • Edge detection function (shared with INTC and also allows the selection of the noise filter function) No.A1335-2/21 LC87F2708A Watchdog Timer • Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed RC oscillation clock (30kHz). • Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/ HOLD mode. Interrupts Source Flags • 16 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L Interrupt Source 2 0000BH X or L INTB 3 00013H H or L INTC/T0L/INTE 4 0001BH H or L INTD/INTF 5 00023H H or L T0H/SIO7 6 0002BH H or L T1L/T1H 7 00033H H or L HCT1 8 0003BH H or L HCT2 INTA 9 00043H H or L ADC/HPWM automatic stop/HPWM cycle 10 0004BH H or L None • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 256levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • Medium speed RC oscillation circuit (internal): For system clock (1MHz) • Low speed RC oscillation circuit (internal): For watchdog timer (30kHz) • High speed RC oscillation circuit (internal): For system clock (20MHz or 40MHz) 1) 2 source oscillation frequencies (20MHz or 40MHz) selectable for the high-speed RC oscillation circuit by optional configuration. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (when high speed RC oscillation is selected for system clock.). Internal reset circuit • Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 3 levels (2.87V, 3.86V, and 4.35V) by optional configuration. • Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V and 4.28V). can be selected by optional configuration. No.A1335-3/21 LC87F2708A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are the following three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) Generating a reset signal via the watchdog timer or brown-out detector (3) Having an interrupt generated • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The medium- and high-speed RC oscillation circuits automatically stop operation. 2) There are the following four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Generating a reset signal via the watchdog timer or brown-out detector (3) Setting at least one of the INTA, INTB, INTC, INTD, INTE, and INTF pins to the specified level (INTA and INTB HOLD mode reset is available only when level detection is set.) (4) Applying input signals to the IN+ and IN- pins so that the analog comparator output is set to the specified level (when the analog comparator output is assigned to the INTC input) On-chip Debugger Function • Supports software debugging with the IC mounted on the target board (LC87D2708A). LC87F2708A has an On-chip debugger but its function is limited. • 3 channels of on-chip debugger pins are available. Data Security Function Note3 • Protects the program data stored in flash memory from unauthorized read or copy. Note3: This data security function does not necessarily provide absolute data security. Package Form • MFP14S(225mil): Lead-free Type Development Tools On-chip debugger: 1) TCB87-Type B + LC87D2708A 2) TCB87-Type B + LC87F2708A 3) TCB87-Type C (3 wire version) + LC87D2708A 4) TCB87-Type C (3 wire version) + LC87F2708A Programming Board Package Programming Board MFP14S(225mil) W87F27M-DBG Flash ROM Programming Board Maker Model Flash Support Group, Inc. (FSG) + SANYO In-circuit Programmer Device (Note 5) LC87F2708A (FSG models) SIB87 (Inter Face Driver) (SANYO model) (Note 4) Single/Gang Programmer SANYO Version AF9101/AF9103 (Main body) In-circuit/ Gang Programmer Application Version SKK-DBG Type B 1.04 or later (SANYO FWS) Chip Data Version LC87F2708A 2.10 or later For information about AF-series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] Note4: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from SANYO (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note5: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or SANYO for the information. No.A1335-4/21 LC87F2708A Package Dimensions unit : mm (typ) 3111A 8.0 14 0.63 4.4 6.4 8 1 7 0.35 0.15 0.1 (1.5) 1.0 1.7MAX (1.0) SANYO : MFP14S(225mil) Pin Assignment P31/INTB/HCT2IN/DBGP01 1 14 VDD1 P30/INTA/HCT1IN/DBGPX0 2 13 P32/INTC/CMPO/DBGP11 RES 3 12 P33/INTD/HPWM/DBGP12 P10/SO7/INTE/AN0/DBGP02 4 11 P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1 VSS1 5 10 P12/SCK7/INTF/IN0-/AN2 P16/INTF/IN1-/AN6 6 9 P13/INTF/T1PWML/AN3/DBGP20 P15/INTE/IN1+/AN5/DBGP22 7 8 P14/INTE/T1PWMH/AN4/DBGP21 LC87F2708A Top view SANYO: MFP14S(225mil) “Lead-free Type” MFP14S NAME MFP14S NAME 1 P31/INTB/HCT2IN/DBGP01 8 P14/INTE/T1PWMH/AN4/DBGP21 2 P30/INTA/HCT1IN/DBGPX0 9 P13/INTF/T1PWML/AN3/DBGP20 3 RES 10 P12/SCK7/INTF/IN0-/AN2 4 P10/SO7/INTE/AN0/DBGP02 11 P11/SI7/SB7/INTE/IN0+/HCT2IN/AN1 5 VSS1 12 P33/INTD/HPWM/DBGP12 6 P16/INTF/IN1-/AN6 13 P32/INTC/CMPO/DBGP11 7 P15/INTE/IN1+/AN5/DBGP22 14 VDD1 No.A1335-5/21 LC87F2708A System Block Diagram Interrupt control IR Standby control PLA Flash ROM High-speed RC Freq. divider Mediumspeed RC Clock generator PC RES WDT (Low-speed RC) Reset control ACC Reset circuit (LVD/POR) Bus interface Timer 0 Port 1 (INTE to INTF) Timer 1 Port 3 (INTA to INTD) High-speed PWM DATA BUS SIO7 DATA BUS B register C register ALU PSW ADC RAR High-speed pulse width/period counter1 High-speed pulse width/period counter2 RAM Analog comparator Stack pointer On-chip debugger No.A1335-6/21 LC87F2708A Pin Description Pin Name I/O Description Option VSS1 - - power supply pin VDD1 - + power supply pin No • 7-bit I/O port Yes PORT1 I/O No • I/O specifiable in 1-bit units P10 to P16 • Pull-up resistors can be turned on and off in 1-bit units • Multiplexed pins P10: SIO7 data output P11: SIO7 data input/bus I/O/high-speed pulse width/period counter 2 input P12: SIO7 clock I/O P13: Timer 1 PWML output P14: Timer 1 PWMH output P10, P11, P14, P15: INTE input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P12, P13, P16: INTF input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input AD converter input port: AN0 to AN6(P10 to P16) Analog comparator input port 0: IN0+, IN0-(P11, P12) Analog comparator input port 1: IN1+, IN1-(P15, P16) On-chip debugger pin 1: DBGP02 (P10) On-chip debugger pin 3: DBGP20 to DBGP22 (P13 to P15) • Interrupt acknowledge type PORT3 I/O Rising Falling INTE enable enable INTF enable enable Rising & H level L level enable disable disable enable disable disable Falling • 4-bit I/O port Yes • I/O specifiable in 1-bit units P30 to P33 • Pull-up resistors can be turned on and off in 1-bit units • Multiplexed pins P30: INTA input/HOLD release input/timer 0L capture input/high-speed pulse width/ period counter 1 input P31: INTB input/HOLD release input/timer 0H capture input/high-speed pulse width/ period counter 2 input P32: INTC input/HOLD release input/timer 0 event input/timer 0L capture input/ analog comparator output P33: INTD input/HOLD release input/timer 0 event input/timer 0H capture input/ high-speed PWM output On-chip debugger pin 1: DBGPX0 to DBGP01 (P30 to P31) On-chip debugger pin 2: DBGPX0 to DBGP12 (P30, P32 to P33) • Interrupt acknowledge type RES I/O Rising Falling INTA enable enable INTB enable enable INTC enable INTD enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable External reset input/internal reset output Falling No No.A1335-7/21 LC87F2708A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Sselected in Units of Option Type P10 to P16 1 bit 1 P30 to P33 1 bit 2 Output Type Pull-up Resistor CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable Nch-open drain Programmable On-chip Debugger Pin Processing For the processing of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip Debugger Installation" and "LC872000 Series On-chip Debugger Pin Processing." Recommended Unused Pin Connections Recommended Unused Pin Connections Pin Name Board Software P10 to P16 OPEN Set output low P30 to P33 OPEN Set output low User Option Table Option Name Port output type Option Type Flash Version Option Switched in Unit of Description P10 to P16 { 1 bit CMOS P30 to P33 { 1 bit CMOS Nch-open drain Nch-open drain Program start - { - address Brown-out detector reset function Power-on-reset { - Brown-out trip level { - Power-on-reset level { - Oscillation frequency { - Brown-out detector function oscillator circuit Enable: Used Disable: Not Used function High-speed RC 00000h 01E00h 3 levels 3 levels 20 MHz 40 MHz No.A1335-8/21 LC87F2708A Absolute Maximum Ratings at Ta = 25°C, VSS1 =0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Maximum supply VDD max VDD1 Input voltage VI RES Input/output VIO • Port 1 voltage • Port 3 voltage Peak output IOPH(1) Port 1 current per applicable pin High level output current IOPH(2) Port 3 CMOS output selected per applicable pin Mean output IOMH(1) Port 1 current (Note 1-1) CMOS output selected per applicable pin IOMH(2) Port 3 CMOS output selected per applicable pin Total output ΣIOAH(1) current ΣIOAH(2) ΣIOAH(3) Low level output current CMOS output selected • Ports 10, 15, 16 Total of currents at all • Ports 30, 31 applicable pins • Ports 11 to 14 Total of currents at all • Ports 32, 33 applicable pins • Port 1 Total of currents at all • Port 3 applicable pins min typ max -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 -10 -5 -7.5 -20 -20 mA -35 IOPL(1) Port 1 Per applicable pin current IOPL(2) Port 3 Per applicable pin 10 Mean output IOML(1) Port 1 Per applicable pin 10 current IOML(2) Port 3 Per applicable pin ΣIOAL(1) • Port 10 Total of currents at all • Ports 30, 31 applicable pins • Ports 11 to 16 Total of currents at all • Ports 32, 33 applicable pins • Port 1 Total of currents at all • Port 3 applicable pins MFP14S(225mil) • Ta=-40 to +85°C 15 7.5 (Note 1-1) current ΣIOAL(2) ΣIOAL(3) Power dissipation Pd max(1) 25 35 55 113 • Independent package Pd max(2) V -7.5 Peak output Total output unit • Ta=-40 to +85°C mW • Mounted on thermal test 260 board • (Note 1-2) Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 °C Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: Thermal test board used conforms to SEMI (size: 76.1×114.3×1.6tmm, glass epoxy board). No.A1335-9/21 LC87F2708A Allowable Operating Range at Ta = -40 to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Operating VDD VDD1 min typ max unit 0.272μs ≤ tCYC ≤ 100μs supply voltage 2.7 5.5 2.0 5.5 (Note 2-1) Memory VHD VDD1 sustaining RAM and register contents sustained in HOLD mode supply voltage High level VIH(1) Low level VIH(2) RES VIL(1) • Port 1 Output disabled Output disabled • Port 3 input voltage VIL(2) Instruction • Port 1 • Port 3 input voltage RES 2.7 to 5.5 0.3VDD 2.7 to 5.5 0.75VDD VDD +0.7 V VDD 0.1VDD 4.0 to 5.5 VSS 2.7 to 4.0 VSS 0.2VDD 2.7 to 5.5 VSS 0.25VDD 2.7 to 5.5 0.272 100 4.5 to 5.5 38 40 42 +0.4 tCYC cycle time μs (Note 2-2) Oscillation FmHRC(1) • High-speed RC oscillation frequency • 40MHz selected as option range • Ta=-20 to +85°C FmHRC(2) • High-speed RC oscillation 4.5 to 5.5 37.6 40 42.4 FmHRC(3) • 40MHz selected as option 3.5 to 5.5 36.8 40 43.2 2.7 to 5.5 32 40 43.2 FmHRC(4) FmHRC(5) • Ta=-40 to +85°C MHz • High-speed RC oscillation • 20MHz selected as option 3.0 to 5.5 19 20 21 2.7 to 5.5 18.7 20 21.3 • Ta=-20 to +85°C FmHRC(6) • High-speed RC oscillation • 20MHz selected as option • Ta=-40 to +85°C Oscillation FmRC Medium-speed RC oscillation 2.7 to 5.5 0.5 1.0 2.0 FmSLRC Low-speed RC oscillation 2.7 to 5.5 15 30 60 kHz tmsHRC • When high-speed RC oscillation 100 μs stabilization state is switched from stopped to time enabled. 2.7 to 5.5 • See Fig. 2. Note 2-1: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the power-on reset (POR) circuit is 2.87V±0.12V. Note 2-2: Relationship between tCYC and oscillation frequency is as follows: • When system clock source is set to medium-speed RC oscillation 3/FmRC at a division ratio of 1/1, 6/FmRC at a division ratio of 1/2, 12/FmRC a division ratio of 1/4, and so forth • When system clock source is set to high-speed RC oscillation (40MHz selected by optional configuration) 12/FmHRC at a division ratio of 1/1, 24/FmHRC at a division ratio of 1/2, 48/FmHRC a division ratio of 1/4, and so forth • When system clock source is set to high-speed RC oscillation (20MHz selected by optional configuration) 6/FmHRC at a division ratio of 1/1, 12/FmHRC at a division ratio of 1/2, 24/FmHRC a division ratio of 1/4, and so forth No.A1335-10/21 LC87F2708A Electrical Characteristics at Ta = -40 to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High level input IIH(1) current • Port 1 • Output disabled • Port 3 • Pull-up resistor off • VIN=VDD min typ max unit 2.7 to 5.5 1 2.7 to 5.5 1 (including output Tr. off leakage current) Low level input IIH(2) RES VIN=VDD IIL • Port 1 • Output disabled • Port 3 • Pull-up resistor off current • VIN=VSS 2.7 to 5.5 -1 IOH=-1mA 4.5 to 5.5 VDD-1 IOH=-0.35mA 2.7 to 5.5 VDD-0.4 IOH=-5mA 4.5 to 5.5 VDD-1.5 IOH=-0.7mA 2.7 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 IOL=1.4mA 2.7 to 5.5 0.4 Port 3 IOL=5mA 4.5 to 5.5 1.5 IOL=0.7mA 2.7 to 5.5 0.4 Rpu(1) • Port 1 VOH=0.9VDD 4.5 to 5.5 15 35 80 Rpu(2) • Port 3 2.7 to 4.5 18 50 150 Rpu(3) RES 2.7 to 5.5 216 360 504 VHYS • Port 1 μA (including output Tr. off leakage current) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) Low level output voltage VOL(1) CMOS output type port 1 CMOS output type port 3 Port 1 VOL(2) VOL(3) VOL(4) Pull-up resistance Hysteresis voltage • Port 3 V kΩ 2.7 to 5.5 0.1VDD V 2.7 to 5.5 10 pF • RES Pin capacitance CP All pins • VIN=VSS for pins other than that under test • f=1MHz • Ta=25°C No.A1335-11/21 LC87F2708A Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = 0V 1. SIO7 Serial I/O Characteristics (Note 4-1-1) Parameter tSCK(1) Pin/ SCK7(P12) Specification Conditions Remarks VDD[V] • See Fig. 4 Low level tSCKL(1) 2.7 to 5.5 pulse width High level Frequency tSCK(2) SCK7(P12) • CMOS output selected tSCKL(2) 4/3 2.7 to 5.5 1/2 tSCK tSCKH(2) 1/2 Serial input SB7(P11), • Must be specified with respect to 0.03 rising edge of SIOCLK. • See Fig. 4. 2.7 to 5.5 thDI(1) 0.03 Input clock Output delay tdDO(1) SO7(P10), SB7(P11) time • Must be specified with respect to rising edge of SIOCLK. 1tCYC • Must be specified as the time to tdDO(2) mode • See Fig. 4. μs +0.05 the beginning of output state change in open drain output Output clock Serial output tsDI(1) SI7(P11) Data hold time unit 1 pulse width Data setup time max 1 pulse width High level typ tCYC tSCKH(1) • See Fig. 4. Low level min 2 (Note 4-1-2) pulse width Output clock Serial clock Input clock Frequency Symbol 2.7 to 5.5 (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in transmission/reception mode, the time from SI7RUN being set when serial clock is "H" to the first falling edge of the serial clock must be longer than 1tCYC. No.A1335-12/21 LC87F2708A Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] High/low level tPIH(1) INTA(P30), • Interrupt source flag can be set. pulse width tPIL(1) INTB(P31), • Event inputs for timers 0 and 1 are INTD(P33), enabled. INTE min. typ. 2.7 to 5.5 1 2.7 to 5.5 1 max. unit (P10, P11, P14, P15), INTF(P12, P13, P16) tPIH(2) INTC(P32) when noise • Interrupt source flag can be set. tPIL(2) filter time constant is • Event inputs for timer 0 are "none" enabled. tPIH(3) INTC(P32) when noise • Interrupt source flag can be set. tPIL(3) filter time constant is • Event inputs for timer 0 are "1/16" INTC(P32) when noise • Interrupt source flag can be set. tPIL(4) filter time constant is • Event inputs for timer 0 are INTC(P32) when noise • Interrupt source flag can be set. tPIL(5) filter time constant is • Event inputs for timer 0 are tPIH(6) HCT1IN(P30) tPIL(6) 64 2.7 to 5.5 128 2.7 to 5.5 256 2.7 to 5.5 3 2.7 to 5.5 6 2.7 to 5.5 200 enabled. tPIH(5) "1/64" 2.7 to 5.5 enabled. tPIH(4) "1/32" tCYC enabled. Pulses can be recognized as signals by the high-speed pulse width/period H1CK (Note 5-1) counter 1. tPIH(7) HCT2IN(P11, P31) tPIL(7) Pulses can be recognized as signals by the high-speed pulse width/period H2CK (Note 5-2) counter 2. tPIL(8) RES Resetting is enabled. μs Note 5-1: H1CK denotes the period of the base clock (1 to 8 × high-speed RC oscillation clock or system clock) for the high-speed pulse width/period counter 1. Note 5-2: H2CK denotes the period of the base clock (2 to 16 × high-speed RC oscillation clock or system clock) for the high-speed pulse width/period counter 2. Comparator Characteristics at Ta = -40 to +85°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Common mode VCMIN IN0-(P12), range IN1+(P15), VOFF Response time tRT typ IN0+(P11), input voltage Offset voltage min IN1-(P16) 2.7 to 5.5 Within common mode input voltage range max VDD VSS -1.5 unit V 2.7 to 5.5 ±10 ±30 mV 2.7 to 5.5 200 600 ns 1.0 μs • Within common mode input voltage range • Input amplitude=100mV • Overdrive=50mV Operation tCMW stabilization time 2.7 to 5.5 (Note 6-1) Note 6-1: The interval after CMPON is set till the operation gets stabilized. No.A1335-13/21 LC87F2708A AD Converter Characteristics at VSS1 = 0V <12-bits AD Converter Mode/Ta = -40 to +85°C > Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(P10) to Absolute ET AN6(P16) max unit 12 bit ±16 3.0 to 5.5 • See Conversion time calculation tCAD typ 3.0 to 5.5 (Note 7-1) accuracy Conversion time min 4.0 to 5.5 38 104.3 3.0 to 5.5 75.8 104.3 LSB μs method • (Note 7-2) Analog input VAIN 3.0 to 5.5 voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 VSS VDD V 1 μA -1 <8-bits AD Converter Mode/Ta = -40 to +85°C > Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(P10) to Absolute ET AN6(P16) method. • (Note 7-2) Analog input max VAIN voltage range unit 8 bit ±1.5 3.0 to 5.5 • See Conversion time calculation tCAD typ 3.0 to 5.5 (Note 7-1) accuracy Conversion time min 4.0 to 5.5 23.4 64.3 3.0 to 5.5 46.7 64.3 3.0 to 5.5 VSS VDD Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 LSB 1 -1 μs V μA Conversion time calculation formulas: 12-bits AD Converter Mode: tCAD(Conversion time) = ((52/(Division ratio))+2)×(1/3)×tCYC 8-bits AD Converter Mode: tCAD(Conversion time) = ((32/(Division ratio))+2)×(1/3)×tCYC <Recommended Operating Conditions> High-speed RC oscillation (FmHRC) 40MHz/20MHz Supply voltage range (VDD) System clock division ratio (SYSDIV) Cycle time (tCYC) AD division Conversion time (tCAD) ratio (ADDIV) 12-bits AD 8-bits AD 4.0V to 5.5V 1/1 300ns 1/8 41.8μs 25.8μs 3.0V to 5.5V 1/1 300ns 1/16 83.4μs 51.4μs Note 7-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured when no change occurs in the I/O state of the pins that are adjacent to the analog input channel during AD conversion processing. Note 7-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital conversion value against the analog input value is loaded in the result register. * The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1335-14/21 LC87F2708A Power-on Reset (POR) Characteristics at Ta = -40 to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage POR release PORRL voltage 2.87V 2.75 2.87 2.99 3.86V 3.73 3.86 3.99 4.35V 4.21 4.35 4.49 0.7 0.95 (Note 8-2) PORIS max • See Fig. 6. • See Fig. 6 POUKS unknown state Power supply rise typ • Option selected (Note 8-1) Detection voltage min Power startup time from time 100 VDD=0V to 2.8V. unit V ms Note 8-1: The POR release voltage can be selected from three levels when the low-voltage detection feature is deselected. Note 8-2: There is an unpredictable period before the power-on reset transistor starts to turn on. Low Voltage Detection Reset (LVD) Characteristics at Ta = -40 to +85°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage LVD reset Voltage LVDET (Note 9-2) 2.81V 2.71 2.81 2.91 3.79V 3.69 3.79 3.89 4.28V 4.18 4.28 4.38 LVHYS hysteresis LVUKS unknown state Minimum low voltage detection width 2.81V 60 3.79V 65 4.28V 65 unit V mV • See Fig. 7. (Note 9-4) tLVDW max • See Fig. 7. (Note 9-3) Detection voltage typ • Option selected. (Note 9-1) LVD voltage min 0.7 0.95 V • LVDET-0.5V • See Fig. 8. 0.2 ms (response sensitivity) Note 9-1: The LVD reset voltage can be selected from three levels when the low-voltage detection feature is selected. Note 9-2: The hysteresis voltage is not included in the LVD reset voltage value. Note 9-3: There are cases when the LVD reset voltage value is exceeded when a greater change in the output level or large current is applied to the port. Note 9-4: There is an unpredictable period before the low-voltage detection resetting transistor starts to run. No.A1335-15/21 LC87F2708A Consumption Current Characteristics at Ta = -40 to +85°C, VSS1 = 0V Parameter Normal mode Symbol IDDOP(1) VDD1 Specification Conditions VDD[V] min typ max unit • FmHRC=40MHz oscillation mode • System clock set to high-speed RC, 10MHz consumption 4.5 to 5.5 7.8 14 2.7 to 3.6 4.9 9.4 4.5 to 5.5 7.1 12.8 2.7 to 3.6 4.5 8.6 4.5 to 5.5 0.60 1.9 2.7 to 3.6 0.38 1.3 (1/4 of 40MHz) current (Note 10-1) Pin/ Remarks IDDOP(2) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDOP(3) • FmHRC=20MHz oscillation mode • System clock set to high-speed RC, 10MHz (1/2 of 20MHz) IDDOP(4) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDOP(5) • High-speed RC oscillation stopped • System clock set to medium-speed RC IDDOP(6) oscillation mode • System clock frequency division ratio set to 1/2 HALT mode IDDHALT(1) consumption • FmHRC=40MHz oscillation mode current • System clock set to high-speed RC, (Note 10-1) IDDHALT(2) mA HALT mode 4.5 to 5.5 3.2 5.0 2.7 to 3.6 2.0 3.1 4.5 to 5.5 2.5 3.9 2.7 to 3.6 1.6 2.5 4.5 to 5.5 0.32 1.0 2.7 to 3.6 0.16 0.55 10MHz (1/4 of 40MHz) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDHALT(3) HALT mode • FmHRC=20MHz oscillation mode • System clock set to high-speed RC, IDDHALT(4) 10MHz (1/2 of 20MHz) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDHALT(5) HALT mode • High-speed RC oscillation stopped IDDHALT(6) • System clock set to medium-speed RC oscillation mode • System clock frequency division ratio set to 1/2 HOLD mode IDDHOLD(1) HOLD mode 4.5 to 5.5 0.04 3.0 consumption IDDHOLD(2) • Ta=-10 to +50°C 2.7 to 3.6 0.02 1.8 IDDHOLD(3) HOLD mode 4.5 to 5.5 0.04 34 IDDHOLD(4) • Ta=-40 to +85°C 2.7 to 3.6 0.02 22 IDDHOLD(5) HOLD mode 4.5 to 5.5 3.1 6.8 • Ta=-10 to +50°C 2.7 to 3.6 2.4 4.2 HOLD mode 4.5 to 5.5 3.1 39 • Ta=-40 to +85°C 2.7 to 3.6 2.4 25 HOLD mode 4.5 to 5.5 3.4 10 • Ta=-10 to +50°C 2.7 to 3.6 1.7 6.0 HOLD mode 4.5 to 5.5 3.4 42 • Ta=-40 to +85°C 2.7 to 3.6 1.7 27 HOLD mode 4.5 to 5.5 110 160 2.7 to 3.6 65 100 current (Note 10-1) IDDHOLD(6) IDDHOLD(7) IDDHOLD(8) IDDHOLD(9) IDDHOLD(10) IDDHOLD(11) IDDHOLD(12) IDDHOLD(13) IDDHOLD(14) • LVD option selected • LVD option selected • Watchdog timer active • Watchdog timer active μA • Comparator active (IN+=VDD, IN-=VSS) Note 10-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.A1335-16/21 LC87F2708A F-ROM Programming Characteristics at Ta = +10 to +55°C, VSS1 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Onboard IDDFW VDD1 programming min typ max unit • Microcontroller consumption current is excluded. 3.0 to 5.5 5 10 mA 20 30 ms 40 60 µs current Programming tFW(1) • Erase operation time tFW(2) • Programming operation 3.0 to 5.5 Power Pin Treatment Recommendations (VDD1, VSS1) Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (L1=L1', L2=L2'). • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ No.A1335-17/21 LC87F2708A 0.5VDD Figure 1 AC Timing Measurement Point VDD Operating VDD lower 0V Power Reset time RES Medium-speed RC oscillation tmsHRC High-speed RC oscillation Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD/HALT release signal No HOLD release signal HOLD release signal valid HALT release signal valid Medium-speed RC oscillation tmsHRC High-speed RC oscillation State HOLD HALT Instruction execution HOLD Release Signal and Oscillation Stabilization Time Figure 2 Oscillation Stabilization Times No.A1335-18/21 LC87F2708A VDD Note: The external peripheral circuit differs depending on the way in which the power-on reset and low-voltage detection reset functions are used. Refer to the Chapter, entitled "Reset Function", of the user's manual. RRES RES CRES Figure 3 Sample Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 4 Serial I/O Waveforms tPIL tPIH Figure 5 Pulse Input Timing Signal Waveform No.A1335-19/21 LC87F2708A (a) POR release voltage (PORRL) (b) VDD Reset period 100μs or longer Reset period Reset unknown-state (POUKS) RES Figure 6 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) • The POR circuit generates a reset signal only when the power voltage is raised from the VSS level. • No stable reset signal is generated if power is turned on again when the power voltage does not go down to the VSS level as shown in (a). If this case is anticipated, use the LVD function as explained below or configure an external reset circuit. • A reset is effected only when power is turned on again after the power voltage goes down to and remains at the VSS level for 100μs or longer as shown in (b). LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD voltage (LVDET) Reset period Reset period Reset period Reset unknown-state (LVUKS) RES Figure 7 Example of POR + LVD Mode Waveforms (at Reset Pin with RRESS Pull-up Resistor Only) • A reset is effected both when power is turned on and when it goes down. • The hysteresis width (LVHYS) is introduced in the LVD circuit to prevent the iterations of the IC entering and exiting the reset state near the detection threshold level. No.A1335-20/21 LC87F2708A VDD LVD release voltage LVD voltage LVDET-0.5V tLVDW VSS Figure 8 Minimum Low Voltage Detection Width (Example of Short Interruption of Power/Power Fluctuation Waveform) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2009. Specifications and information herein are subject to change without notice. PS No.A1335-21/21