Ordering number : ENA2304 LC87F0G08A CMOS LSI 8-bit 1-chip Microcontroller http://onsemi.com 8K-byte Flash ROM / 256-byte RAM / 24-pin Features a 10 /20 amplifier a 8/10-bit High-speed PWM(150kHz) a Reference Voltage Generator Circuit(2V/4V) for an AD converter a Temperature sensor an internal reset circuit a 7-channel AD converter with 12-/8-bit resolution selector Internal oscillation circuits (30kHz/1MHz/8MHz) SSOP24(225mil) Performance 83.3ns (12.0MHz) VDD=2.7V to 5.5V Ta= 40C to + 85C 125ns (8.0MHz) VDD=2.0V to 5.5V Ta= 40C to + 85C 250ns (4.0MHz) VDD=1.8V to 5.5V Ta= 40C to + 85C Function Descriptions Ports - I/O ports : 18 - Reference voltage outputs : 1 (VREF) - Power supply pins : 3 (VSS1, VSS2, VDD1) Timers (3ch) - Timer 0 : 16-bit timer/counter with a capture register. - Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs - a Base timer serving as a realtime clock SIO (1ch) - SIO1 : 8-bit asynchronous/synchronous serial interface Comparator Watchdog Timer P70/INT0/T0LCP/AN09 RES Frequency tunable 12-bit PWM 2ch VSS1 CF1/XT1 System Clock Divider Function CF2/XT2 CF Oscillation Circuit, X'tal Oscillation Circuit VDD1 P10/SO1 15 sources, 10 vectors interrupts P11/SI1/SB1 P12/SCK1 On-chip Debugger Function P13/INT4/T1IN/AN7 P14/INT4/T1IN/AN6 P15/INT3/T0IN/AN5 1 2 3 4 5 6 7 8 9 10 11 12 LC87F0G08A 24 23 22 21 20 19 18 17 16 15 14 13 OWP0 P06/T1PWMH P05/T1PWML /CKO P04/AN4/VCPWM1 P03/AN3/VCPWM0 P02/AN2/CPIM P01/APIP P00/APIM VREF VSS2 P17/BUZ/INT1/T0HCP/HPWM2 P16/INT2/T0IN/CPOUT/HPWM2 Application Shaver, Battery charge control Pin Assignment (Top view) * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 31 of this data sheet. Semiconductor Components Industries, LLC, 2014 March, 2014 Ver. 1.01 31014HKIM 20130905-S00003 No.A2304-1/31 LC87F0G08A Function Details Flash ROM Capable of on-board programming with a wide range of supply voltages : 2.2 to 5.5V Block-erasable in 128 byte units Writes data in 2-byte units 8192 × 8 bits RAM 256 × 9 bits Bus Cycle Time 83.3ns ( 12MHz, VDD=2.7V to 5.5V, Ta=40C to 85C) 125ns ( 8MHz, VDD=2.0V to 5.5V, Ta=40C to 85C) 250ns ( 4MHz, VDD=1.8V to 5.5V, Ta=40C to 85C) Note : The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) 250ns (12MHz, VDD=2.7V to 5.5V, Ta=40C to 85C) 375ns ( 8MHz, VDD=2.0V to 5.5V, Ta=40C to 85C) 750ns ( 4MHz, VDD=1,8V to 5.5V, Ta=40C to 85C) Potrs Normal withstand voltage I/O ports whose I/O direction can be designated in 1-bit units 18(P0n, P1n, P70, CF1, CF2) Reset pins 1(RES) Power supply pins 3(VSS1, VSS2,VDD1) Reference voltage outputs 1(VREF) Dedicated debugger port 1(OWP0) Timers Timer 0 : 16-bit timer/counter with 2 capture registers. Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3 : 16-bit counter (with two 16-bit capture registers) Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1 : 8-bit PWM with an 8-bit prescaler 2 channels Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a PWM output) Base timer (1) The clock is selectable from the subclock (32.768kHz crystal oscillation), the low speed RC, system clock, and timer 0 prescaler output. (2) with an 8-bit programmable prescaler (3) Interrupts programmable in 5 different time schemes No.A2304-2/31 LC87F0G08A SIO SIO1 : 8-bit asynchronous/synchronous serial interface Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect) AD Converter: AD converter input port with 10 /20 amplifier (1channel) AD converter input port (7channel) 12-/8-bit resolution selectable AD converter Selectable reference voltage source for an AD converter ( Selectable from VDD , Internal Reference Voltage Generator Circuit(VREF) .) Internal Reference Voltage Generator Circuit(VREF) Generates 2.0V/4.0V for AD converter. Comparator Comparator input pin (1 channel) Comparator output pin (1 channel) Comparator output set high when (comparator input level) < 1.22V Comparator output set low when (comparator input level) > 1.22V Clock Output Function Generates clocks with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillation clock that is selected as the system clock. Watchdog Timer Generates an internal reset on an overflow occurring in the timer running on the low-speed RC oscillator clock (approx. 30kHz) or subclock. Operating mode at standby is selectable from 3 modes (continue counting/suspend operation/suspend counting with the count value retained) No.A2304-3/31 LC87F0G08A Interrupts 15 sources, 10 vectors 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address is given priority. No. Vector Address Level 1 00003H X or L Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/BT 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L HPWM2 8 0003BH H or L SIO1 9 00043H H or L ADC 10 0004BH H or L P0/VCPWM INT0 Priority levels X > H > L Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: Up to 128levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions 16 bits 8 bits (5 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) 16 bits 8 bits (8 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) Oscillation Circuits Internal oscillation circuits 1) Low-speed RC oscillation circuit: 2) Medium-speed RC oscillation circuit: 3) Hi-speed RC oscillation circuit1: 4) Hi-speed RC oscillation circuit2: For system clock (approx.30kHz) For system clock (1MHz) For system clock (8MHz) For High speed PWM (40MHz) System Clock Divider Function Can run on low consumption current. Minimum instruction cycle selectable from 375ns, 750ns, 1.5s, 3.0s, 6.0s, 12.0s, 24.0s, 48.0s, and 96.0s (at 8MHz main clock) Internal Reset Circuit Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level is 1.67V. Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level can be selected from 7 levels (1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V and 4.28V), through option configuration. No.A2304-4/31 LC87F0G08A Standby Function ● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) Having the watchdog timer or LVD function generate a reset (3) Having an interrupt generated ● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC and crystal oscillators automatically stop operation. Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. 2) There are four ways of resetting the HOLD mode: (1) Setting the reset pin to the lower level (2) Having the watchdog timer or LVD function generate a reset (3) Having an interrupt source established at one of the INT0, INT1, INT2 and INT4 pins * INT0 and INT1 can be used in the level sense mode only. (4) Having an interrupt source established at port 0. ● X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. (when X’tal oscillation or low-speed RC oscillation is selected). 1) The CF, low-speed, and medium-speed RC oscillators automatically stop operation. Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. Note: If the base timer is run with low-speed RC oscillation selected as the base timer input clock source and the X’tal HOLD mode is entered, the low-speed RC oscillator retains the state that is established when the X’tal HOLD mode is entered. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Having the watchdog timer or LVD function generate a reset (3) Having an interrupt source established at one of the INT0, INT1, INT2, and INT4 pins * INT0 and INT1 can be used in the level sense mode only. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit VCPWM: Frequency tunable 12-bit PWM × 2ch High speed PWM (HPWM2) 8-/10- bits PWM ×1ch 1) The PWM clock is selectable from system clock and Hi-speed RC2 (40MHz) 2) The PWM type is selectable from 8 bits(Normal mode) and 10 bits( additive puls mode). Temperature sensor Senseor voltage can be comapred by the AD converter. On-chip Debugger Function Supports software debugging with the IC mounted on the target board. Provides 1 channel of on-chip debugger pin. OWP0 Data Security Function Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. Package Form SSOP24 (225mil): Lead-free and halogen-free type No.A2304-5/31 LC87F0G08A Development Tools On-chip debugger: TCB87 Type C (1-wire interface cable) + LC87F0G08A Programming Boards Package Programming boards SSOP24(225mil) W87F0GS Flash Programmer Maker Flash Support Group, Inc. (FSG) Single Programmer Flash Support Group, Inc. (FSG) + Our company Model Supported version Device AF9709C Rev 03.28 or later 87F008SU (Note 2) - AF9101/AF9103(Main unit) Onboard Single/Gang Programmer (FSG models) SIB87 Type C(Inter Face Driver) (Our company model) (Note 1) Single/Gang Programmer Our company SKK Type B / SKK Type C 1.08 or later Onboard Single/Gang Programmer Application Version SKK-DBG Type C Chip Data Version LC87F0G08 2.46 or later For information about AF-Series : Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87 Type C) together can give a PC-less, standalone on-board-programming capabilities. Note2: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or Our company for the information. No.A2304-6/31 LC87F0G08A Package Dimensions unit : mm SSOP24 (225mil) CASE 565AR ISSUE A SOLDERING FOOTPRINT* 5.80 1.0 (Unit: mm) 0.32 GENERIC MARKING DIAGRAM* XXXXXXXXXX YMDDD 0.50 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *This information is generic. Please refer to device data sheet for actual part marking. No.A2304-7/31 LC87F0G08A Pin Assignment P70/INT0/T0LCP/AN09 RES VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO1 P11/SI1/SB1 P12/SCK1 P13/INT4/T1IN/AN7 P14/INT4/T1IN/AN6 P15/INT3/T0IN/AN5 1 2 3 4 5 6 7 8 9 10 11 12 LC87F0G08A 24 23 22 21 20 19 18 17 16 15 14 13 OWP0 P06/T1PWMH P05/T1PWML /CKO P04/AN4/VCPWM1 P03/AN3/VCPWM0 P02/AN2/CPIM P01/APIP P00/APIM VREF VSS2 P17/BUZ/INT1/T0HCP/HPWM2 P16/INT2/T0IN/CPOUT/HPWM2 SSOP24(225mil) "Lead-/Halogen-free Type" SSOP24 NAME SSOP24 NAME 1 P70/INT0/T0LCP/AN09 13 P16/INT2/T0IN/CPOUT/HPWM2 2 P17/BUZ/INT1/T0HCP/HPWM2 RES 14 3 VSS1 15 VSS2 4 CF1/XT1 16 VREF 5 P00/APIM CF2/XT2 17 6 VDD1 18 P01/APIP 7 P10/SO1 19 P02/AN2/CPIM 8 P11/SI1/SB1 20 P03/AN3/VCPWM0 9 P12/SCK1 21 P04/AN4/VCPWM1 10 P13/INT4/T1IN/AN7 22 P05/T1PWML/CKO 11 P14/INT4/T1IN/AN6 23 P06/T1PWMH 12 P15/INT3/T0IN/AN5 24 OWP0 No.A2304-8/31 LC87F0G08A System Block Diagram Interrupt control IR CF/XT low speed RC medium speed RC High speed RC Flash ROM Clock Generator Standby control PLA PC RES Reset circuit (LVD/POR) ACC Reset control WDT (low speed RC) B register C register SIO1 Bus interface Timer0 Port0 Timer1 Port1 ALU PSW Base timer HPWM2 High speed RC2 Temperature sensor RAR VCPWM RAM Port7 Stack pointer INT0-4 (INT3 with Noise filter) On-chip debugger ADC 10x/20x amplifier (1 channel) + - Vref Comparator No.A2304-9/31 LC87F0G08A Pin Description Pin Name I/O Description Option VSS1 - - power supply pin No VDD1 - + power supply pin No VSS2 - - power supply pin No VREF I/O Reference voltage output(2.0V/4.0V) or External input No OWP0 I/O On-chip debugger pin No Port 0 I/O 7-bit I/O port Yes I/O specifiable in 1-bit units. P00 to P06 Pull-up resistors can be turned on and off in 1-bit units. Pin functions P00 (AN0), P01 (AN1): AD converter input port with 10x/20x operational amplifier P02: AD converter input port (AN2) / Comparator input (CPIM) P03: AD converter input port (AN3) / VCPWM0 output P04: AD converter input port (AN4) / VCPWM1 output P05: Timer 1 PWML output / System clock output P06: Timer 1 PWMH output P07: On-chip debugger pin (OWP0) Port 1 P10 to P15 I/O 8-bit I/O port Yes I/O specifiable in 1-bit units. Pull-up resistors can be turned on and off in 1-bit units. Pin functions P10: SIO1 data output P11: SIO1 data input/bus input/output P12: SIO1 clock input/output P13: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input/ AD converter input port (AN7) P14: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input/ AD converter input port (AN6) P15: INT3 input(with noise filter)/timer 0 event input/timer 0H capture input/ AD converter input port (AN5) P16: INT2 input/HOLD release input/timer 0 event input/ timer 0L capture input/HPWM2 output P17: beeper output/INT1 input/HOLD release input/timer 0H capture input/HPWM2 output Interrupt acknowledge type Rising & H level L level disable enable enable enable enable disable disable enable enable disable disable enable enable disable disable Rising Falling INT1 enable enable INT2 enable INT3 enable INT4 enable Falling Continued on next page. No.A2304-10/31 LC87F0G08A Continued from preceding page. Pin Name Port 7 I/O I/O Description Option 1-bit I/O port No I/O specifiable P70 Pull-up resistors can be turned on and off. Pin functions P70 : INT0 input/HOLD release input/timer 0L capture input/AD converter input port (AN9) Interrupt acknowledge type INT0 RES I Rising Falling enable enable Rising & Falling disable External reset input/internal reset output pin H level L level enable enable Yes Internal pullup ON/OFF CF1/XT1 I/O Ceramic oscillator/32.768kHz crystal oscillator input pin No Pin functions 1-bit I/O port I/O specifiable (only Nch-open drain) CF2/XT2 I/O Ceramic oscillator/32.768kHz crystal oscillator output pin No Pin functions 1-bit I/O port I/O specifiable OWP0 I/O On-chip debugger pin No No.A2304-11/31 LC87F0G08A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P06 P10 to P17 Option selected in units of Option type 1 1 bit 1 bit Output type Pull-up resistor CMOS Programmable Programmable 2 Nch-open drain 1 CMOS Programmable 2 Nch-open drain Programmable CF1/XT1 - No CF2/XT2 - No P70 - No Nch-open drain No when general I/O port is selected. CMOS / Nch-open drain when general I/O port is selected.(programmable) Nch-open drain No Programmable User Option Table Option Name Option Type Flash Version Option Selected in Units of P00 to P06 enable 1 bit P10 to P17 enable 1 bit Port output form Option Selection CMOS Nch-open drain CMOS Nch-open drain 00000h or 01E00h Program start address When protected area 1) is selected - enable - 00000h When either of protected area 2), 3) or 4) is selected 1) 1800h-1FFFh Protected area (Note1) - enable - 2) 0000h-1DFFh,1F00h-1FFFh 3) 0000h-1CFFh,1F00h-1FFFh 4) 0000h-1AFFh,1F00h-1FFFh Reset pin Low-voltage detection reset function Power-on reset function Internal pullup ON/OFF enable - ON OFF Enable: Use Detect function enable - Detect level enable - 7-level Power-On reset level enable - 1-level Disable: Not Used Note1: onboard programming inhbited address No.A2304-12/31 LC87F0G08A Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software P00 to P07 Open Output low P10 to P17 Open Output low P70 Open Output low CF1/XT1 Open General I/O port output low CF2/XT2 Open General I/O port output low OWP0 Pulled low with a 100k resistor - On-chip Debugger Pin Connection Requirements For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “Rd87 On-chip Debugger Installation Manual” Power Pin Treatment Recommendations (VDD1, VSS1) Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (L1=L1’, L2=L2’). Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1F. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ No.A2304-13/31 LC87F0G08A Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = 0V Parameter Maximum supply Symbol Pin/Remarks VDDMAX VDD1 VIO Port0,1 Conditions voltage Input/output voltage Specification VDD[V] min typ max unit -0.3 to +6.5 -0.3 to VDD+0.3 V Port7 High level output current CF1,CF2, RES Peak output IOPH(1) current Average Port0 Port1 IOMH(1) When CMOS output type is selected CF2 Per 1 applicable pin Port0 When CMOS output output current Port1 (Note 1-1) CF2 Per 1 applicable pin Port0,1, Total current of all CF2 applicable pins Total output ΣIOAH(1) current type is selected -10 -7.5 -30 Port0 Per 1 applicable pin 20 Port1 Per 1 applicable pin 20 IOPL(3) Port7,CF1,CF2 Per 1 applicable pin 10 Average IOML(1) Port0 Per 1 applicable pin 15 output current (Note 1-1) IOML(2) Port1 Per 1 applicable pin 15 IOML(3) Port7,CF1,CF2 Per 1 applicable pin 7.5 Total output current ΣIOAL(1) Port0,1,7, Total current of all CF1,CF2 applicable pins Allowable power Dissipation Pdmax(1) Low level output current IOPL(1) IOPL(2) Peak output current SSOP24(225mil) mA 80 Ta=-40 to + 85C Package with thermal 260 resistance board mW (Note 1-2) Operating ambient Topr Temperature Storage ambient temperature Tstg -40 +85 -55 +125 C Note 1-1: The average output current is an average of current values measured over 100ms intervals. Note 1-2: SEMI standards thermal resistance board (size: 76.1114.31.6tmm, glass epoxy) is used. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. No.A2304-14/31 LC87F0G08A Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max 0.245s tCYC 200s 2.7 5.5 VDD(2) 0.367s tCYC 200s 2.0 5.5 VDD(3) 0.735s tCYC 200s 1.8 5.5 Operating VDD(1) supply voltage (Note 2-1) Memory VHD VDD1 VDD1 sustaining unit RAM and register contents sustained in HOLD mode. 1.6 supply voltage High level VIH(1) input voltage Low level Port 0,1 P70 1.8 to 5.5 0.3VDD +0.7 VIH(4) CF1,CF2, RES 1.8 to 5.5 0.75VDD VIL(1) Port 0,1 4.0 to 5.5 P70 1.8 to 4.0 VSS VSS VIL(4) CF1,CF2, RES 1.8 to 5.5 input voltage V VDD VDD 0.1VDD+0.4 0.2VDD 0.25VDD Instruction tCYC 2.7 to 5.5 VSS 0.245 cycle time (Note 2-2) 2.0 to 5.5 0.367 200 1.8 to 5.5 0.735 200 2.7 to 5.5 0.1 12 2.2 to 5.5 0.1 8 (Note 2-2) External FEXCF CF1 CF2 pin open 200 s System clock frequency system clock frequency division ratio=1/1 External system clock MHz duty=50 5% Oscillation FmCF(1) CF1,CF2 frequency range When 12MHz ceramic oscillation See Fig. 1. FmCF(2) CF1,CF2 (Note 2-3) When 8MHz ceramic oscillation See Fig. 1. FmCF(3) CF1,CF2 When 4MHz ceramic oscillation See Fig. 1. FmFRC(1) 2.7 to 5.5 12 2.2 to 5.5 8 1.8 to 5.5 4 Internal high-speed RC oscillation Ta=-10C to +85C 1.8 to 5.5 7.76 8.0 8.24 1.8 to 5.5 7.60 8.0 8.40 1.8 to 5.5 0.5 1.0 2.0 1.8 to 5.5 27 30 33 MHz (Note 2-4) FmFRC(2) Internal high-speed RC oscillation Ta=-40C to +85C (Note 2-4) FmRC Internal medium-speed RC oscillation FmSRC Internal low-speed RC oscillation (Note 2-5) FsX’tal XT1,XT2 FmPWMRC 32.768kHz crystal oscillation See Fig. 2. Internal high-speed RC oscillation for HPWM2 CF1,CF2 tmsCF Stabilization tmsFRC switched from “oscillation Time (Note 2-4) stopped” to “oscillation tmsPWMR enabled” . C See Fig. 3. tmsRC tmsSRC 38 XT1,XT2 40 kHz 42 MHz See Table 1 1.8 to 5.5 100 1.8 to 5.5 100 s 1.8 to 5.5 0 1.8 to 5.5 (Note2-5) tmsX’tal 2.7 to 5.5 When oscillation circuit is Oscillation 32.768 1.8 to 5.5 kHz 1 ms See Table 2 Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: An oscillation stabilization time of 100s or longer must be provided before switching the system clock source after the state of the high-speed RC oscillation circuit is switched from “oscillation stopped” to “oscillation enabled” . Note 2-5: An oscillation stabilization time of 1ms or longer must be provided before switching the system clock source after the state of the low-speed RC oscillation circuit is switched from “oscillation stopped” to “oscillation enabled” . Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. No.A2304-15/31 LC87F0G08A Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter High level input Symbol IIH(1) current Pin/Remarks Conditions Port 0,1, Output disabled Port 7, Pull-up resistor off RES VIN=VDD (Including output Tr's off Specification VDD[V] min typ max unit 1.8 to 5.5 1 1.8 to 5.5 15 leakage current) IIH(2) CF1 VIN=VDD IIL(1) Port 0,1, Output disabled Port 7, Pull-up resistor off RES VIN=VSS (Including output Tr's off IIL(2) CF1 VIN=VSS 1.8 to 5.5 -15 High level output VOH(1) Port 0,1, IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) CF2 IOH=-0.2mA 1.8 to 5.5 VDD-0.4 Low level input current 1.8 to 5.5 A -1 leakage current) V Low level output VOL(1) Port 0,1, IOL=10mA 4.5 to 5.5 1.5 voltage VOL(2) P70,CF1,CF2 IOL=1.0mA 1.8 to 5.5 0.4 Pull-up resistance Rpu(1) Port 0,1, VOH=0.9VDD 4.5 to 5.5 15 35 80 Rpu(2) P70 1.8 to 4.5 18 50 230 Rpu(3) RES 1.8 to 5.5 300 400 500 VHYS(1) Port 0,1, 2.7 to 5.5 0.1VDD 1.8 to 5.5 0.07VDD 1.8 to 5.5 10 Hysteresis voltage P70 RES Pin capacitance CP All pins k V For pins other than that under test: VIN=VSS f=1MHz pF Ta=25C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.A2304-16/31 LC87F0G08A SIO1 Serial I/O Characteristics (Note 4-1) Input clock Symbol Frequency tSCK(1) Low level tSCKL(1) Pin/ Conditions Remarks SCK1(P12) VDD[V] See Fig. 5. tSCK(2) SCK1(P12) CMOS output type selected tSCKL(2) 2 1/2 tSCK tSCKH(2) 1/2 pulse width Serial input Data setup time tsDI(1) SI1(P11), SB1(P11) Specified with respect to rising edge of SIOCLK. See Fig. 5. Data hold time unit 1 1.8 to 5.5 pulse width High level max 1 See Fig. 5. Low level typ tCYC tSCKH(1) Frequency min 2 1.8 to 5.5 pulse width High level Specification pulse width Output clock Serial clock Parameter thDI(1) 0.05 1.8 to 5.5 0.05 tdDO(1) SO1(P10), Serial output Output delay time SB1(P11) s Specified with respect to falling edge of SIOCLK Specified as the time up to the beginning of output change in (1/3)tCYC 1.8 to 5.5 +0.08 open drain output mode. See Fig. 5. Note 4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter Symbol Pin/Remarks Conditions High/low level tPIH(1) INT0(P70), Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), Event inputs for timer 0 or 1 are INT2(P16), enabled. Specification VDD[V] min 1.8 to 5.5 1 1.8 to 5.5 2 typ max unit INT4(P13, P14) tPIH(2) INT3(P15) when noise Interrupt source flag can be set. tPIL(2) filter time constant is Event inputs for timer 0 are 1/1 enabled. tPIH(3) INT3(P15) when noise Interrupt source flag can be set. tPIL(3) filter time constant is Event inputs for timer 0 are 1/32 INT3(P15) when noise Interrupt source flag can be set. tPIL(4) filter time constant is Event inputs for timer 0 are tPIL(5) RES 1.8 to 5.5 64 1.8 to 5.5 256 1.8 to 5.5 200 enabled. tPIH(4) 1/128 tCYC enabled. Resetting is enabled. s No.A2304-17/31 LC87F0G08A AD Converter Characteristics at VSS1 = VSS2 = 0V <12bits AD Converter Mode/Ta = -40C to +85C > Parameter Symbol Pin/Remarks Resolution N AN2(P02) Absolute ET AN3(P03) Conditions Specification VDD[V] min typ 1.8 to 5.5 (Note 6-1) max unit bit 12 1.8 to 5.5 16 accuracy AN4(P04) Conversion time AN5(P15) See conversion time 2.7 to 5.5 AN6(P14) 32 115 calculation method. AN7(P13) 2.2 to 5.5 134 215 (Note 6-2) 1.8 to 5.5 400 430 1.8 to 5.5 VSS VDD 4.3 to 5.5 VSS VREF VSS VREF TCAD AN9(P70) Analog input VAIN(1) voltage range VAIN(2) When VDD is selected (Note 6-3) LSB s When internal VREF=4V is selected. V VREFVDD When internal VREF=2V is 2.3 to 3.6 selected Analog port IAINH VREFVDD VAIN=VDD input current IAINL VAIN=VSS 1.8 to 5.5 1.8 to 5.5 1 -1 A <8bits AD Converter Mode/Ta = -40C to +85C > Parameter Symbol Pin/Remarks Resolution N AN2(P02) Absolute ET AN3(P03) TCAD AN5(P15) (Note 6-1) See conversion time calculation AN6(P14) method. AN7(P13) (Note 6-2) AN9(P70) Analog input VAIN(1) voltage range VAIN(2) When VDD is selected (Note 6-3) Specification VDD[V] min typ 1.8 to 5.5 AN4(P04) accuracy Conversion time Conditions max unit bit 8 1.8 to 5.5 1.5 2.7 to 5.5 20 90 2.2 to 5.5 80 135 1.8 to 5.5 245 265 1.8 to 5.5 VSS VDD 4.3 to 5.5 VSS VREF VSS VREF LSB s When internal VREF=4V is selected. V VREFVDD When internal VREF=2V is selected. Analog port IAINH VREFVDD VAIN=VDD input current IAINL VAIN=VSS 2.3 to 3.6 1.8 to 5.5 1.8 to 5.5 1 -1 A <Conversion time calculation method> 12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)(1/3)tCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2) (1/3)tCYC No.A2304-18/31 LC87F0G08A <Recommended Operating Conditions> External Operating supply oscillation voltage range (FmCF) (VDD) CF-8MHz CF-4MHz System division ratio Cycle time (SYSDIV) (tCYC) 2.7V to 5.5V 1/1 2.2V to 5.5V 2.7V to 5.5V AD conversion time AD division (TCAD) ratio (ADDIV) 12bit AD 8bit AD 375ns 1/8 52.25s 32.25s 1/1 375ns 1/32 208.25s 128.25s 1/1 750ns 1/8 104.5s 64.5s 2.2V to 5.5V 1/1 750ns 1/16 208.5s 128.5s 1.8V to 5.5V 1/1 750ns 1/32 416.5s 256.5s Note 6-1: The quantization error (1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured when no change occurs in the I/O state of the pins that are adjacent to the analog input channel during AD conversion processing. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: The first AD conversion executed in the 12-bit AD conversion mode after a system reset The first AD conversion executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode Note 6-3: See section 8, “10×/20× amplifier characteristics”, for analog channel 0 (10×/20× amplifier output). Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Reference Voltage Generator Circuit (VREF) Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter VREF=2V voltage Symbol VREF2VO accuracy VREF=4V voltage VREF4VO accuracy VREFoutput current VREFIO Operation tVREFW stabilization time Pin/Remarks Conditions Specification VDD[V] min VREF 1.8 to 2.0 VDD-0.1 VDD (Note 7-2) 2.0 to 5.5 1.90 2.02 2.3 to 5.5 1.98 2.02 1.8 to 4.0 VDD-0.1 VDD 4.0 to 5.5 3.90 4.04 4.3 to 5.5 3.96 4.04 1.8 to 5.5 VSS 0.5 mA 5 ms 1.8 to 5.5 typ max unit V (Note 7-1) Note 7-1: Refers to the interval between the time VR12ON and VR24ON are set to 1 and the time operation gets stabilized. Note 7-2: An external 4.7F capacitor must be connected to the VREF pin to stabilize the VREF voltage. No.A2304-19/31 LC87F0G08A 10x/20x Amplifier Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter 20x Amplifier gain 20x Amplifier Symbol Pin/Remarks Conditions APGAIN20 P00/APIM Ta=-40 to +85C See Fig7 P01/APIP 1)APDIR=0 & GAIN20=1. Specification VDD[V] min typ max unit 20 P01=0V,P000V or VAPIO20 P00=0V,P010V offset 2)APDIR=1 & GAIN20=1. 200 600 P01/APIP=0V -0.17 0 P00/APIM=0V 0 0.17 P01/APIP=0V 0 0.17 P00/APIM=0V -0.17 0 P01=0V,P000V or mV P00=0V,P010V 20x Amplifier VAPIM20-1 P00/APIM input voltage VAPIP20-1 P01/APIP range 10x Amplifier gain 10x Amplifier 1) VAPIM20-2 P00/APIM VAPIP20-2 P01/APIP APGAIN10 P00/APIM Ta=-40 to +85C See Fig7 P01/APIP 3)APDIR=0 & GAIN20=0. 2) P01=0V,P000V or VAPIO10 V V 10 4.3 to 5.0 P00=0V,P010V offset 4)APDIR=1 & GAIN20=0. P01=0V,P000V or 100 300 mV P00=0V,P010V 10x Amplifier VAPIM10-3 P00/APIM input voltage VAPIP10-3 P01/APIP range VAPIM10-4 P00/APIM VAPIP10-4 P01/APIP Amplifier input IAPINL port input current IAPINH Operation tAPW 3) P01/APIP=0V -0.24 0 P00/APIM=0V 0 0.24 P01/APIP=0V 0 0.24 P00/APIM=0V -0.24 0 P00/APIM P00/APIM=VSS-0.2V -1 P01/APIP P01/APIP=VDD 4) stabilization time 1 20 V V A s (Note 8-1) Note 8-1: Refers to the interval between the time APON is set to 1 and the time operation gets stabilized. <Amplifier input vaoltage calculation method:See Fig7> VAPFUL = ( VREFAD - VAPIO ) / APGAIN ( VREFAD can be selected from internal-VREF4V, internal-VREF2V and VDD. ) Note: VAPFUL must not exceed VAPIP or VAPIM. No.A2304-20/31 LC87F0G08A Comparator Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter Comparator Symbol VCMVT Pin/Remarks Conditions Specification VDD[V] min typ max unit P02/CPIM threshold voltage 2.5 to 5.5 1.12 2.5 to 5.5 VSS 1.22 1.32 V VDD V (Note 9-1) Input voltage range VCMIN Offset voltage VOFF Within input voltage range Response time 2.5 to 5.5 ±10 ±30 mV 2.5 to 5.5 200 600 ns 1.0 s Within input voltage tRT range Input amplitude =100mV Overdrive=50mV Operation tCMW 2.5 to 5.5 stabilization time (Note 9-2) Note 9-1: Comparator output=High level when (P02/CPIM voltage) < VCMVT Comparator output=Low level when (P02/CPIM voltage) > (VCMVT +VOFF) Note 9-2: Refers to the interval between the time CPON is set to 1 and the time operation gets stabilized. Temperature Sensor Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V <4-diode mode> Parameter Output voltage Symbol Pin/Remarks Conditions Specification VDD[V] min typ max VOTMP4(1) Ta=-40C 5.0 3.23 3.25 3.27 VOTMP4(2) Ta=+25C 5.0 2.75 2.77 2.80 VOTMP4(3) Ta=+85C 5.0 2.28 2.31 2.34 sensitivity Vsen4 Ta=-40 to +85C 3.5 to 5.5 -7.63 -7.54 -7.45 Absolute accuracy ETTMP4 3.5 to 5.5 ±2.5 ±5 3.5 to 5.5 ±5 ±10 Vref=4[V] Ta=(60±10) C (Note 10-1) (Note 10-3) (Note 10-2) Ta=-40 to +85C unit V mV/C C <2-diode mode> Parameter Output voltage Symbol Pin/Remarks Conditions Specification VDD[V] min typ max VOTMP2(1) Ta=-40C 3.3 1.61 1.63 1.64 VOTMP2(2) Ta=+25C 3.3 1.37 1.39 1.40 VOTMP2(3) Ta=+85C 3.3 1.14 1.16 1.17 sensitivity Vsen2 Ta=-40 to +85C 2.0 to 5.5 -3.81 -3.77 -3.72 Absolute accuracy ETTMP2 2.0 to 5.5 ±2.5 ±5 2.0 to 5.5 ±5 ±10 Vref=2[V] Ta=(60±10) C (Note 10-1) (Note 10-4) (Note 10-2) Ta=-40 to +85C unit V mV/C C Note 10-1: There are cases when the absolute accuracy specification value is exceeded when a large current flows through the ports. Note 10-2: Including error of AD Converter. Note 10-3: When using the Temperature sensor 60C 2-diodes reference register D2TL/ D2TH. Note 10-4: When using the Temperature sensor 60C 4-diodes reference register D4TL/ D4TH. No.A2304-21/31 LC87F0G08A Power-on Reset (POR) Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin / Remarks Conditions Option Selected Voltage POR release PORRL Option selected (Note 11-1) POUKS See Fig. 8. (Note 11-2) voltage Detection voltage unpredictable 1.67V min typ max 1.10 unit 1.79 V 0.7 0.95 area Power supply rise PORIS Power startup time from time 100 VDD=0V to 1.6V ms Note 11-1: The POR release voltage can be selected when the low-voltage detection feature is deselected. Note 11-2: There is an unpredictable area before the transistor starts to turn on. Low Voltage Detection Reset (LVD) Characteristics at Ta = -40C to +85C, VSS1= VSS2= 0V Specification Parameter Symbol Pin / Remarks Conditions Option Selected Voltage LVD reset voltage LVDET (Note 12-2) 1.91V 1.81 1.91 2.01 2.01V 1.91 2.01 2.11 2.31V 2.21 2.31 2.41 2.51V 2.41 2.51 2.61 2.81V 2.71 2.81 2.93 3.79V 3.69 3.79 3.92 4.28V 4.18 4.28 4.41 LVHYS hysteresis LVUKS unpredictable max Option selected (Note 12-3) Detection voltage typ See Fig. 9. (Note 12-1) LVD voltage min 1.91V 55 2.01V 55 2.31V 55 2.51V 55 2.81V 60 3.79V 65 4.28V 65 See Fig. 9. (Note 12-4) 0.7 unit V mV 0.95 V area Minimum low voltage detection width (response TLVDW LVDET-0.5V See Fig. 10. 0.2 ms sensitivity) Note 12-1: The LVD reset voltage can be selected from 7 levels when the low-voltage detection feature is selected. Note 12-2: The hysteresis voltage is not included in the LVD reset voltage specification value. Note 12-3: There are cases when the LVD reset voltage specification value is exceeded when a greater change in the output level or large current is applied to the port. Note 12-4: There is an unpredictable area before the transistor starts to turn on. No.A2304-22/31 LC87F0G08A Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = 0V Parameter Normal mode Symbol IDDOP(1) Pin / Conditions Remarks VDD1 Specification VDD[V] min typ max unit FmCF=8MHz ceramic oscillation mode consumption System clock set to 8MHz mode current Internal low-/medium-speed RC oscillation 2.2 to 5.5 3.8 5.2 2.2 to 3.6 2.2 2.9 1.8 to 5.5 2.1 3.5 1.8 to 3.6 1.1 1.7 1.8 to 5.5 0.23 0.39 1.8 to 3.6 0.13 0.19 1.8 to 5.5 2.7 3.6 1.8 to 3.6 1.7 2.3 1.8 to 5.5 10 42 1.8 to 3.6 6 21 1.8 to 5.5 46 101 1.8 to 3.6 16 40 stopped (Note 13-1) Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 (Note 13-2) IDDOP(2) FmCF=4MHz ceramic oscillation mode System clock set to 4MHz mode Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDOP(3) mA FsX’tal=32.768kHz crystal oscillation mode Internal low-speed RC oscillation stopped System clock set to internal medium-speed RC oscillation mode Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 IDDOP(4) FsX’tal=32.768kHz crystal oscillation mode Internal low-/medium-speed RC oscillation stopped System clock set to internal high-speed RC oscillation mode Frequency division ratio set to 1/1 IDDOP(5) External oscillation FsX’tal/FmCF stopped System clock set to internal low-speed RC oscillation mode Internal medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDOP(6) A FsX’tal=32.768kHz crystal oscillation mode System clock set to 32.768kHz mode Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 Continued on next page. No.A2304-23/31 LC87F0G08A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) Pin / Conditions Remarks VDD1 FmCF=8MHz ceramic oscillation mode current System clock set to 8MHz mode (Note 13-1) Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDHALT(2) min Typ max unit HALT mode consumption (Note 13-2) Specification VDD[V] 2.2 to 5.5 2.0 3.2 2.2 to 3.6 1.0 1.6 1.8 to 5.5 1.2 2.4 1.8 to 3.6 0.5 1.0 HALT mode FmCF=4MHz ceramic oscillation mode System clock set to 4MHz mode Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDHALT(3) mA HALT mode FsX’tal=32.768kHz crystal oscillation mode 1.8 to 5.5 0.12 0.25 1.8 to 3.6 0.06 0.11 1.8 to 5.5 1.1 1.7 1.8 to 3.6 0.7 1.0 1.8 to 5.5 3.8 37 1.8 to 3.6 2.4 17 Internal low-speed RC oscillation stopped System clock set to internal medium-speed RC oscillation mode Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 IDDHALT(4) HALT mode FsX’tal=32.768kHz crystal oscillation mode Internal low-/medium-speed RC oscillation stopped System clock set to internal high-speed RC oscillation mode Frequency division ratio set to 1/1 IDDHALT(5) HALT mode External oscillation FsX’tal/FmCF stopped System clock set to internal low-speed RC oscillation mode Internal medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/1 IDDHALT(6) A HALT mode FsX’tal=32.768kHz crystal oscillation mode 1.8 to 5.5 42 97 1.8 to 3.6 13 38 System clock set to 32.768kHz mode Internal low-/medium-speed RC oscillation stopped Internal high-speed RC oscillation stopped Frequency division ratio set to 1/2 HOLD mode IDDHOLD(1) VDD1 HOLD mode consumption current (Note 13-1) (Note 13-2) Timer HOLD IDDHOLD(2) IDDHOLD(3) current (Note 13-1) (Note 13-2) VDD1 IDDHOLD(4) 0.023 33.2 0.012 14.2 1.8 to 5.5 1.09 26.9 LVD option selected 1.8 to 3.6 0.86 11.8 Timer HOLD mode 1.8 to 5.5 39 94 1.8 to 3.6 12 36 1.8 to 5.5 0.63 34 1.8 to 3.6 0.53 15 FsX’tal=32.768kHz crystal oscillation mode mode consumption HOLD mode 1.8 to 5.5 1.8 to 3.6 Timer HOLD mode FmSRC=30kHz internal low-speed RC oscillation mode A Note 13-1: The consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. Note 13-2: Unless otherwise specified, the consumption current for the LVD circuit is not included. No.A2304-24/31 LC87F0G08A F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = 0V Parameter Onboard Symbol IDDFW(1) Pin/Remarks VDD1 Conditions Specification VDD[V] min typ max unit Excluding power programming dissipation in the current microcontroller block Programming tFW(1) Erasing time time tFW(2) Programming time 2.2 to 5.5 2.2 to 5.5 5 10 mA 20 30 ms 40 60 s No.A2304-25/31 LC87F0G08A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator MURATA Manufacturing Co., Ltd. Nominal Frequency Circuit Constant Type Oscillator Name C1 C2 Rf Operating Voltage Range Rd Oscillation Stabilization Time [V] typ max Remarks [pF] [pF] [] [] [ms] [ms] 12MHz SMD CSTCE12M0G52-R0 (10) (10) Open 680 2.6 to 5.5 0.02 0.3 C1 and C2 8MHz SMD CSTCE8M00G52-R0 (10) (10) Open 1k 2.1 to 5.5 0.02 0.3 integrated 4MHz SMD CSTCR4M00G53-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.03 0.45 type Characteristics of a Sample Subsystem Clock Oscillation Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit that Uses a Crystal Oscillator EPSON TOYOCOM Nominal Frequency Circuit Constant Type Oscillator Name Operating C1 C2 Rf Rd [pF] [pF] [] [] 9 9 Open 330k Voltage Range [V] Oscillation Stabilization Time typ max [ms] [ms] 1.4 4.0 Remarks Applicable 32.768kHz SMD MC-306 1.8 to 5.5 CL value = 7.0pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 3): Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed Till the oscillation gets stabilized after the HOLD mode is released. Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF2/XT2 CF1/XT1 Rf Rd C1 C2 CF/X’tal Figure 1 CF/XT Oscillator Circuit 0.5VDD Figure 2 AC Timing Measurement Point No.A2304-26/31 LC87F0G08A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal medium speed RC oscillation tmsCF/tmsX’tal CF1, CF2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD release signal absent HOLD release signal valid Internal medium speed RC oscillation or internal low speed RC oscillation tmsCF/tmsX’tal CF1, CF2 (Note) State HOLD HALT HOLD Release Signal and Oscillation Stabilization Time Note: When an external oscillation circuit is selected. Figure 3 Oscillation Stabilization Time No.A2304-27/31 LC87F0G08A VDD Note: The external circuit for reset may vary depending on the usage of POR and LVD. See “Reset Function” in the user's manual. RRES RES CRES Figure 4 Sample Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKH tSCKL SIOCL tsDI thDI DATAIN: tdDO DATAOUT: Figure 5 Serial I/O Waveform tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform No.A2304-28/31 LC87F0G08A AMPoutput AMPoutput VREF VREF APGAIN APGAIN VAPIO 0 VAPIO 0 0V -VAPFUL (a) 0V 1) P00/APIM input 2) P01/APIPinput +VAPFUL (b) 1) P01/APIPinput 2) P00/APIMinput Figure 7 10/20 Amplifier Characteristics (a) 1) When P01/APIP is 0V, P00/APIM 0V. 2) When P00/APIM is 0V, P01/APIP 0V. (b) 1) When P00/APIM is 0V, P01/APIP 0V. 2) When P01/APIP is 0V, P00/APIM 0V. No.A2304-29/31 LC87F0G08A (a) POR release voltage (PORRL) (b) VDD Reset period 100s or longer Reset period Reset unknown area (POUKS) RES Figure 8 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) The POR function generates a reset only when the power voltage goes up from the VSS level. No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit as shown below. A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100s or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD Reset unknown area (LVUKS) LVD reset voltage (LVDET) Reset period Reset period Reset period RES Figure 9 Example of POR + LVD Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) Resets are generated both when power is turned on and when the power level lowers. A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. No.A2304-30/31 LC87F0G08A VDD LVD release voltage LVD detect voltage LVDET-0.5V TLVDW VSS Figure 10 Minimum Low Voltage Detection Width (Example of Voltage Sag/Fluctuation Waveform) ORDERING INFORMATION Device LC87F0G08AUJA-AH Package SSOP24(225mil) (Pb-Free / Halogen Free) Shipping (Qty / Packing) LC87F0G08AUJA-FH SSOP24(225mil) (Pb-Free / Halogen Free) 2000 / Tape & Reel LC87F0G08AUJA-ZH SSOP24(225mil) (Pb-Free / Halogen Free) 1400 / Fan-Fold 2000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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