CYPRESS IBIS4-6600

IBIS4-6600
Datasheet
IBIS4-6600
High resolution 6.6 M Pixel
Rolling shutter
CMOS Image sensor
Datasheet
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
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Datasheet
Table of contents
1
INTRODUCTION ..................................................................................................4
1.1
1.2
1.3
2
OVERVIEW .......................................................................................................4
KEY FEATURES .................................................................................................5
PART NUMBER ..................................................................................................5
SPECIFICATIONS ................................................................................................6
2.1 GENERAL SPECIFICATIONS................................................................................6
2.2 ELECTRO-OPTICAL SPECIFICATIONS .................................................................6
2.2.1
Overview ..................................................................................................6
2.2.2
Spectral response curve ...........................................................................7
2.2.3
Photo-voltaic response curve...................................................................8
2.3 FEATURES AND GENERAL SPECIFICATIONS .......................................................8
2.4 ELECTRICAL SPECIFICATIONS ...........................................................................9
2.4.1
Absolute maximum ratings.......................................................................9
2.4.2
Recommended operating conditions ........................................................9
2.4.3
DC Electrical characteristics ................................................................10
3
SENSOR ARCHITECTURE AND OPERATION ..............................................11
3.1 FLOOR PLAN ...................................................................................................11
3.2 PIXEL .............................................................................................................12
3.2.1
Architecture............................................................................................12
3.2.2
FPN and PRNU......................................................................................12
3.2.3
Color filter array....................................................................................13
3.2.4
Dark and dummy pixels .........................................................................14
3.3 PIXEL RATE ....................................................................................................14
3.4 REGION-OF-INTEREST (ROI) READ OUT.........................................................15
3.5 OUTPUT AMPLIFIER ........................................................................................15
3.5.1
Stage 1: Offset, FPN correction and multiplexing.................................16
3.5.2
Stage 2: Programmable gain amplifier .................................................16
3.5.3
Stage 3: Output drivers..........................................................................17
3.5.4
Offset DACs ...........................................................................................18
3.6 SUB-SAMPLING MODES ...................................................................................19
3.7 ELECTRONIC SHUTTER....................................................................................25
3.8 HIGH DYNAMIC RANGE MODES .......................................................................26
3.8.1
Double slope integration........................................................................26
3.8.2
Non-destructive readout (NDR).............................................................27
3.9 SEQUENCER ....................................................................................................28
3.9.1
Internal registers....................................................................................28
3.9.2
Detailed description of registers............................................................30
3.9.3
Serial to Parallel interface.....................................................................37
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4
TIMING DIAGRAMS .........................................................................................39
4.1 SEQUENCER CONTROL SIGNALS ......................................................................39
4.2 BASIC FRAME AND LINE TIMING .....................................................................39
4.3 PIXEL OUTPUT TIMING ....................................................................................40
4.3.1
Two outputs............................................................................................40
4.3.2
Multiplexing to one output .....................................................................41
4.3.3
ADC timing ............................................................................................42
5
PIN LIST ..............................................................................................................43
NOTE ON POWER-ON BEHAVIOR.................................................................................45
6
PAD POSITIONING AND PACKAGING..........................................................47
6.1 BARE DIE ........................................................................................................47
6.2 BONDING PADS ...............................................................................................48
6.2.1
Probe pad positions ...............................................................................48
6.2.2
Bonding pad positions............................................................................49
6.3 PACKAGE DRAWING .......................................................................................51
6.3.1
Technical drawing of the 68-pins LCC package....................................51
6.3.2
Bonding of the IBIS4-6600 sensor in the 68-pins LCC package ...........54
6.4 GLASS LID SPECIFICATIONS ............................................................................55
6.4.1
Color sensor...........................................................................................55
6.4.2
Monochrome sensor...............................................................................56
7
BOUNDARY SCAN TEST STRUCTURES.......................................................57
8
STORAGE AND HANDLING ............................................................................58
8.1
8.2
9
STORAGE CONDITIONS....................................................................................58
HANDLING AND SOLDER PRECAUTIONS ..........................................................58
ORDERING INFORMATION.............................................................................60
APPENDIX A: IBIS4 EVALUATION KIT................................................................62
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1 Introduction
1.1
Overview
The IBIS4-6600 is a solid state CMOS image sensor that integrates the functionality
of complete analog image acquisition, digitizer and digital signal processing system
on a single chip. The image sensor compromises a 6.6 MPixel resolution with
2210x3002 active pixels. The image size is fully programmable to user-defined
windows of interest. The pixels are on a 3.5 µm pitch. The sensor is available in a
Monochrome version or Bayer (RGB) patterned color filter array.
User programmable row and column start/stop positions allow windowing down to
2x1 pixel window for digital zoom. Sub sampling reduces resolution while
maintaining the constant field of view. The analog video output of the pixel array is
processed by an on-chip analog signal pipeline. Double Sampling (DS) eliminates the
fixed pattern noise. The programmable gain and offset amplifier maps the signal
swing to the ADC input range. A 10-bit ADC converts the analog data to a 10-bit
digital word stream. The sensor uses a 3-wire Serial-Parallel (SPI) interface. It
operates with a single 2.5V power supply and requires only one master clock for
operation up to 40 MHz. It is housed in a 68-pin ceramic LCC package.
The IBIS4-6600 is designed taking into consideration interfacing requirements to
standard video encoders. In addition to the 10-bit pixel data stream, the sensor outputs
the valid frame, line and pixel sync signals needed for encoding.
This datasheet allows the user to develop a camera system based on the described
timing and interfacing.
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1.2
Key features
6.6 Mpixel resolution: 2210 x 3002 active pixels – progressive scan.
3.5 µm pitch square pixels (based on the high-fill factor active pixel sensor
technology of FillFactory (US patent No. 6,225,670 and others)).
Monochrome or Bayer (RGB) color filters.
Single 2.5V supply; Single master clock.
High pixel rate of 40 MHz using a 40 MHz system clock.
10-bit digital output.
61 dB dynamic range.
High optical dynamic range with double slope integration and Non Destructive
Read out (NDR) modes.
Electronic rolling shutter.
Pixel addressability to support Region-of-Interest windowing and sub
sampling.
On-chip Double Sampling FPN correction.
Digital programmable using a 3-wire Serial-to-Parallel Interface (SPI).
Programmable gain and offset amplifier.
68-pins ceramic LCC package.
1.3
Part number
Part number
Package
IBIS4-6600-M-1
CYII4SM6600AA-HBC – Preliminary
IBIS4-6600-M-2
CYII4SM6600AA-QBC – Preliminary
IBIS4-6600-C-1
CYII4SC6600AA-HAC – Preliminary
IBIS4-6600-C-2
CYII4SC6600AA-QAC – Preliminary
84 pins
JLCC *
68 pins
LCC
84 pins
JLCC
68 pins
LCC
Monochrome
/ color die
Glass lid
Monochrome
Monochrome**
Monochrome
Monochrome
Color
Color***
Color
Color
* JLCC package for use in evaluation kits only.
** D263 is used as monochrome glass lid (see Figure 34 for spectral transmittance).
*** S8612 is used as color glass lid (see Figure 33 for spectral transmittance).
Other packaging combinations are available upon special request.
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2 Specifications
2.1
General specifications
Table 1: General specifications
Parameter
Pixel
architecture
Pixel size
Resolution
Specification
Pixel rate
40 MHz
Shutter type
Electronic rolling
shutter
Full frame
rate
5 frames/second
2.2
Remarks
3T-pixel
3.5 µm x 3.5 µm
2210 x3002
The resolution and pixel size results in a
7,74 mm x 10,51 mm optical active area.
Using a 40 MHz system clock and 1 or 2
parallel outputs.
Increases with ROI read out and/or sub
sampling.
Electro-optical specifications
2.2.1 Overview
Table 2: Electro-optical specifications
Parameter
FPN (local)
PRNU (local)
Conversion gain
Output signal
amplitude
Saturation charge
Sensitivity
Specification
<0.35 %
<1.5%
37 uV/electron
Remarks
RMS % of saturation signal.
RMS of signal level.
@ output (measured).
0.8V
At nominal conditions.
21.500 e283 V.m2/W.s
1.57 V/lux.s
Peak QE * FF
Peak SR * FF
22.5 %
0.12 A/W
Fill factor
Dark current (@
21 °C)
Temporal noise
50%
6.29 mV/s
170 e-/s
20 RMS e1100:1
940:1
Dynamic range
Average white light.
Visible band only (180 lx = 1 W/m2).
Average QE*FF = 20% (visible range).
Average SR*FF = 0.1 A/W (visible range).
See spectral response curve.
Light sensitive part of pixel.
Typical value of average dark current of the
whole pixel array.
Measured at digital output (in the dark).
Full: 61 dB.
Linear: 59.5 dB.
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Parameter
Spectral
sensitivity range
Specification
Remarks
400 – 1000 nm
Optical cross talk
15%
4%
To the first neighboring pixel.
To the second neighboring pixel.
Power
dissipation
190 mWatt
Typical (with ADC’s).
2.2.2 Spectral response curve
0.14
QE 30%
QE 20%
0.12
Spectral Response [A/W]
0.1
QE 10%
0.08
0.06
0.04
0.02
0
400
500
600
700
800
900
1000
Wavelenght [nm]
Figure 1: Spectral response curve
Figure 1 shows the spectral response characteristic. The curve is measured directly on
the pixels. It includes effects of non-sensitive areas in the pixel, e.g. interconnection
lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE * FF is
22.5% approximately between 500 and 700 nm. In view of a fill factor of 50%, the
QE is thus close to 50% between 500 and 700 nm.
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2.2.3 Photo-voltaic response curve
0.9
0.8
0.7
output swing [V]
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5000
10000
15000
20000
25000
30000
number of electrons
Figure 2: Photo-voltaic response curve
Figure 2 shows the pixel response curve in linear response mode. This curve is the
relation between the electrons detected in the pixel and the output signal. The
resulting voltage-electron curve is independent of any parameters (integration time,
etc). The voltage to electrons conversion gain is 37 µV/electron.
2.3
Features and general specifications
Table 3: Features and general specifications
Feature
Electronic shutter type
Integration time control
Windowing (ROI)
Sub-sampling modes:
Extended dynamic range
Analog output
Digital output
Supply voltage VDD
Logic levels
Specification/Description
Rolling shutter.
60 us – 1/frame period.
Randomly programmable ROI read out.
Several sub sample modes can be programmed (see 3.6)
Dual slope (up to 90 dB optical dynamic range) and
non-destructive read out mode.
The output rate of 40 Mpixels/s can be achieved with 2
analog outputs each working at 20 Mpixel/s.
2 on-chip 10-bit ADC’s @ 20 Msamples/s are
multiplexed to 1 digital 10 bit output @ 40 Msamples/s.
Nominal 2.5V (some supplies require 3.3V for extended
dynamic range).
2.5V.
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Feature
Interface
Package
2.4
Specification/Description
Serial-to Parallel Interface (SPI).
68-pins LCC.
Electrical specifications
2.4.1 Absolute maximum ratings
Table 4: Absolute maximum ratings
Symbol
VDD
VIN
VOUT
IIO
TL
Parameter
Value
Unit
DC supply voltage
DC input voltage
DC output voltage
DC current drain per pin; any single input
or output.
Lead temperature (5 seconds soldering).
-0.5 to 3.3
-0.5 to (VDC +0.5)
-0.5 to (VDC + 0.5)
V
V
V
± 50
mA
350
°C
Absolute Ratings are those values beyond which damage to the device may occur.
VDD = VDDD = VDDA (VDDD is supply to digital circuit, VDDA to analog circuit).
2.4.2 Recommended operating conditions
Table 5: Recommended operating conditions
Symbol
VDD
TA
Parameter
Min
Typ
Max
Unit
DC supply voltage
Commercial operating
temperature.
2.5
0
0
2.5
24
24
3.3
50
38
V
°C (@ 15% RH)
°C (@ 86% RH)
RH = Relative Humidity
All parameters are characterized for DC conditions after thermal equilibrium has been
established.
Unused inputs must always be tied to an appropriate logic level, e.g. either VDD or GND.
This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however it is recommended that normal precautions be taken to avoid
application of any voltages higher than the maximum rated voltages to this high impedance
circuit.
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2.4.3 DC Electrical characteristics
Table 6: DC electrical characteristics
Symbol
VIH
VIL
IIN
VOH
VOL
IDD
Characteristic
Input high voltage
Input low voltage
Input leakage current
Output high voltage
Output low voltage
Maximum operating
current
Condition
Min
Max
VDD-0.5
VIN = VDD or GND
VDD=min; IOH= -100mA
VDD=min; IOH= 100mA
-10
VDD-0.5
System clock <= 40MHz
70
Unit
0.5
V
V
µA
V
V
80
mA
0.6
+10
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3 Sensor architecture and operation
In this part of the document some of the more important specifications will be
discussed more detail.
3.1
Floor plan
(excl. dark +
dummy pixels)
column amplifiers
clk_x
sync_x
Dig. logic
addressable x-shift register + sub-sampling
SPI
address &
data bus
Dig. logic
DAC
DAC in
ADC, 10 bit
eos_yr
clk_y
sync_yr
clk_y
sync_yl
Pixel (0,0)
ADC, 10 bit
2210 x 3002
sequencer
reset and select drivers
pixel array
addressable y-shift register + sub-sampling
select
tri r
reset
tri l
IMAGE CORE
reset and select drivers
addressable y-shift register + sub-sampling
eos_yl
SENSOR
analog output (2)
Figure 3: Block diagram of the IBIS4-6600 CMOS image sensor
Figure 3 shows the architecture of the image sensor that has been designed. It consists
basically of the pixel array, shift registers for the readout in x and y direction, parallel
analog output amplifiers, and column amplifiers that correct for the fixed pattern
noise caused by threshold voltage non-uniformities. Reading out the pixel array starts
by applying a y clock pulse to select a new row, followed by a calibration sequence to
calibrate the column amplifiers (row blanking time). Depending on external bias
resistors and timing, typically this sequence takes about 7 µs per line (baseline). This
sequence is necessary to remove the Fixed Pattern Noise of the pixel and of the
column amplifiers themselves (by means of a Double Sampling technique). Pixels can
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also be read out in a non-destructive manner. Two DACs have been added to make
the offset level of the pixel values adjustable and equal for the two output busses. A
third DAC is used to connect the busses to a stable voltage during the row blanking
period (or to the reset busses continuously in case of non-destructive readout). Two
10-bit ADCs running at 20 Msamples/s will convert the analog pixel values. The
digital outputs will be multiplexed to 1 digital 10-bit output at 40 Msamples/s. Note
that these blocks are electrically completely isolated from the sensor part (except for
the multiplexer for which the settings are uploaded through the shared address and
data bus).
The x and y shift registers do have a programmable starting point. The starting points
possibilities are limited due to limitations imposed by sub-sampling requirements.
The upload of the start address is done through the serial to parallel interface.
Most of the signals for the image core in Figure 3 are generated on chip by the
sequencer. This sequencer also allows running the sensor in basic modes, not fully
autonomously.
3.2
Pixel
3.2.1 Architecture
The pixel architecture is the classical three-transistor pixel as shown in Figure 4. The
pixel has been implemented using the high fill factor technique as patented by
FillFactory (US patent No. 6,225,670 and others).
Vdd
reset
M1
select
M2
M3
output
(column)
Figure 4: Architecture of the 3T-pixel
3.2.2 FPN and PRNU
Fixed Pattern Noise correction is done on chip. Raw images taken by the sensor
typically feature a residual (local) FPN of 0.35 % RMS of the saturation voltage.
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The Photo Response Non Uniformity (PRNU), caused by mismatch of photodiode
node capacitances, is not corrected on chip. Measurements indicate that the typical
PRNU is about 1.5 % RMS of the signal level.
3.2.3 Color filter array
The IBIS4-6600 can also be processed with a Bayer RGB color pattern. Pixel (0,0)
has a green filter and is situated on a green-red row.
Figure 5: Color filter arrangement on the pixels. Green1 and green2 are separately processed color
filters and have a different spectral response. Green1 pixels are located on a blue-green row, green2
pixels are located on a green-red row.
Figure 6 below shows the response of the color filter array as function of the
wavelength. Note that this response curve includes the optical cross talk and the NIR
filter of the color glass lid as well (see chapter 6.4.1 for response of the color glass
lid).
Figure 6: Color filters response curve
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3.2.4 Dark and dummy pixels
Figure 7 shows a plan of the pixel array. The sensor has been designed in “portrait”
orientation. A ring of dummy pixels surrounds the active pixels. Black pixels are
implemented as “optical” black pixels.
Dummy ring of pixels,
surrounding complete pixel
array. not read
Ring of dummy pixels,
covered with black layer,
readable
3002
Ring of 2 dummy pixels,
illuminated, readable
3014
array of active pixels, read
3002x 2210
2222
2210
Figure 7: Floor plan pixel array
3.3
Pixel rate
The pixel rate for this sensor is high enough to support a frame rate of >75 Hz for a
window size of 640 x 480 pixels (VGA format) + 23 pixels over scan in both
directions. Taking into account a row blanking time of 7.2 µs (as baseline, see also
3.9.2.a.7.), this requires a minimum pixel rate of nearly 40 MHz. The final bandwidth
of the column amplifiers, output stage etc. is determined by external bias resistors.
Taken into account a pixel rate of 40 MHz a full frame rate of a little more than 5
frames/s will be obtained.
The frame period of the IBIS4-6600 sensor can be calculated as follows:
=> Frame period = (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with: Nr. Lines: Number of Lines read out each frame (Y).
Nr. Pixels: Number of pixels read out each line (X).
RBT: Row Blanking Time = 7.2 µs (typical).
Pixel period: 1/40 MHz = 25 ns.
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Example: read out time of the full resolution at nominal speed (40 MHz pixel rate):
=> Frame period = (3002 * (7.2 µs + 25 ns * 2210)) = 187.5 ms => 5.33 fps.
3.4
Region-Of-Interest (ROI) read out
Windowing can easily be achieved by uploading the starting point of the x- and yshift registers in the sensor registers (see 3.10). This downloaded starting point
initiates the shift register in the x- and y-direction triggered by the Y_START (initiates
the Y-shift register) and the Y_CLK (initiates the X-shift register) pulse. The
minimum step size for the x-address is 24 (only even start addresses can be chosen)
and 1 for the Y-address (every line can be addressed). The frame rate increases almost
linearly when fewer pixels are read out. Table 7 gives an overview of the achievable
frame rates with ROI read out.
Table 7: Frame rate vs. resolution
Image Resolution
(Y*X)
3002 x 2210
1501 x 1104
640 x 480
3.5
Frame rate
[frames/s]
5
14
89
Frame readout
time [ms]
187.5
67
11
Comment
Full resolution.
ROI read out.
ROI read out.
Output amplifier
The output amplifier subtracts the reset and signal voltages from each other to cancel
FPN as much as possible (Figure 8). The DAC that is used for offset adjustment
consists of 2 DACs. One is used for the main offset (DAC_raw) and the other allows
for fine tuning to compensate the offset difference between the signal paths arriving at
the two amplifiers A1 and A2 (DAC_fine). With the analog multiplexer the signals S1
and S2 from the two busses can be combined to one pixel output at full pixel rate (40
MHz). The two analog signals S1 and S2 can, however, also be available on two
separate output pins to allow a higher pixel rate.
The third DAC (DAC_dark) puts its value on the busses during the calibration of the
output amplifier. In case of non-destructive readout (no double sampling), bus1_R
and bus2_R are continuously connected to the output of the DAC_fine to provide a
reference for the signals on bus1_S and bus2_S.
The complete output amplifier can be put in standby by setting the corresponding bit
in the AMPLIFIER register.
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programmable
gain amplifiers
bus1_S
+
bus1_R
−
bus2_S
+
bus2_R
−
A1
A2
output
drivers
Pixel output 1
S1
1
analog
multiplexer
Pixel output 2
S2
1
Stage 1
Stage 2
Stage 3
DAC_raw /
DAC_fine
DAC_dark
Figure 8: Output amplifier architecture
3.5.1 Stage 1: Offset, FPN correction and multiplexing
In the first stage, the signals from the busses are subtracted and the offset from the
DACs is added. After a system reset, the analog multiplexer is configured for two
outputs (see bit settings of the AMPLIFIER register). In case ONE_OUT is set to 1, the
two signals S1 and S2 are multiplexed to one output (output 1). The amplifiers of
stage 2 and stage 3 of the second output path are then put in standby. The speed and
power consumption of the first stage is controllable through the resistor connected to
CMD_OUT_1.
3.5.2 Stage 2: Programmable gain amplifier
The second stage provides the gain which will be adjustable between 1.36 and 17.38
in steps of roughly 20.25 (~1.2). An overview of the gain settings is given in Table 8
and Figure 9. The speed and power consumption of the second stage is controllable
through the resistor connected to CMD_OUT_2.
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Table 8: Overview gain settings
bits
0000
0001
0010
0011
0100
0101
0110
0111
DC gain
1.36
1.64
1.95
2.35
2.82
3.32
3.93
4.63
bits
1000
1001
1010
1011
1100
1101
1110
1111
DC gain
5.40
6.35
7.44
8.79
10.31
12.36
14.67
17.38
Figure 9: Overview of the gain for each gain setting
3.5.3 Stage 3: Output drivers
The speed and power consumption of the third stage is controllable through the
resistor connected to CMD_OUT_3. The output drivers are designed to drive a 20 pF
output load at 40 Msamples/s with a bias resistor of 100 kΩ.
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3.5.4 Offset DACs
Figure 10 shows how the DAC registers influence the black reference voltages of the
two different channels. The offset is mainly given through DAC_raw. DAC_fine can
be used to shift the reference voltage of bus 2 up or down to compensate for different
offsets in the two channels.
10K
DAC_RAW_REG<0:7>
blackref
bus1
DAC_raw
out
200K
rcal
RCAL
+
pad
RCAL_DAC_OUT
VDDA
VCAL
50K
DAC_FINE_REG<0:7>
DAC_fine
10K
blackref
bus2
200K
out
50K
rcal
GNDA
floating
Figure 10: Offset for the two channels through DAC_raw and DAC_fine
Assume that Voutfull is the voltage that depends on the bit values that are applied to the
DAC and ranges from
Voutfull : 0 (bit values 00000000) → VDDA (1 −
1
) (bit values 11111111)
28
Externally, the output range of DAC_raw can be changed by connecting a resistor Rcal
to RCAL_DAC_OUT and applying a voltage Vcal. The output voltage Vout of DAC_raw
follows relation (R = 10 kΩ)
Vout
Special case: Rcal = ∞
=
R + Rcal
R
Voutfull +
Vcal
2 R + Rcal
2 R + Rcal
then Vout = Voutfull (e.g. for DAC_fine)
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Rcal = 0, Vcal = GND
then Vout = Voutfull/2
A similar relation holds for the output range of DAC_DARK (RCAL_DAC_DARK can be
used to tune the output range of this DAC).
3.6
Sub-sampling modes
To increase the frame rate for lower resolution and/or regions of interest, a number of
sub sampling modes have been implemented. The following modes are foreseen
(Table 9). The bits can be programmed in the IMAGE_CORE register (see 3.9).
Table 9: Overview sub sample modes
Mode
Bits
Read
Step
A
000
2
2
Default mode
B
001
2
4
(Skip 2)
C
010
2
6
(Skip 4)
D
011
2
8
(Skip 6)
E
1xx
2
12
(Skip 10)
To preserve the color information, 2 adjacent pixels are read in any mode, while the
number of pixels that is not read, varies from mode to mode. This will be designed as
a repeated block of 24 pixels wide, which is the lowest common multiple of the
modes described above. Including the dummy pixels and the two additional
rows/columns, the number of starting coordinates for the x and y shift register is thus
99 in the X and 138 in the Y direction. The total number of pixels, excluding dummy
pixels, is a multiple of 24, and two additional pixels to have the same window edges
independently of the sub-sampling mode. In the X direction, two columns are always
addressed at the same moment since the signals from the odd and even columns must
be put simultaneously on the corresponding bus. In the Y direction, the rows are
addressed one by one. This results in slightly different implementations of the subsampling modes for the two directions (Figure 11 and Figure 12).
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Logic selecting 2 collumns
Logic selecting 2 collumns
Logic selecting 2 collumns
Logic selecting 2 collumns
Logic selecting 2 collumns
Logic selecting 2 collumns
Logic selecting 2 collumns
Shift register
Shift register
Shift register
Shift register
Shift register
Shift register
Logic selecting 2 collumns
Shift register
Shift register
Logic selecting 2 collumns
Shift register
Logic selecting 2 collumns
Logic selecting 2 collumns
Shift register
Shift register
Logic selecting 2 collumns
scan direction
Shift register
IBIS4-6600
Datasheet
24 column amplifiers
bus1_S
bus1_R
bus2_S
bus2_R
A
B
C
D
E
Figure 11: X sub-sampling
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Logic selecting 1 row
shift registers on pixel pitch
scan direction
E
D
C
B
A
Figure 12: Y sub-sampling
Table 10 lists the frame rates of the sensor in various sub-sampling modes (see also
chapter 3.4).
Table 10: Frame rate in the various sub sampling modes
Mode
A
B
C
D
E
VGA (p)
VGA (p) + 23
VGA (l)
Ratio
1:1
1:4
1:9
1:16
1:36
Resolution (Y*X)
3002 x 2210
1502 x 1106
1002 x 738
752 x 554
502 x 370
640 x 480
663 x 503
480 x 640
Frame time [ms]
187.4
52.3
25.7
15.8
8.2
12.3
13.1
11.1
Frame rate [fr/s]
5.3
19.1
38.9
63.2
121.2
81.5
76.4
89.9
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Mode
VGA(l) + 23
Ratio
Resolution (Y*X)
503 x 663
Frame time [ms]
11.9
Frame rate [fr/s]
83.7
Figure 13 shows the pixels read out in each color sub-sampling mode.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
mode A
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23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
mode B
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
mode C
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23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
mode D
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
mode E
Figure 13: Pixels read out in the various sub-sampling modes
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3.7
Electronic shutter
A curtain like (rolling) electronic shutter has been implemented on chip. As can be
seen in Figure 14, there are two Y shift registers. One of them points to the row that is
currently being read out. The other shift register points to the row that is currently
being reset. Both pointers are shifted by the same Y-clock and move over the focal
plane. The integration time is set by the delay between both pointers.
Integration
time
Readout
pointer
Reset
pointer
Figure 14: Operation of the electronic shutter
In case of a mechanical shutter, the two shift registers can be combined to apply the
pulses from both sides of the pixel array simultaneously. This is to halve the influence
of the parasitic RC times of the reset and select lines in the pixel array (which can
result in a reduction of the row blanking time). This is the case when FAST_RESET in
the SEQUENCER register is set to 1 or in the non-destructive readout modes 1 and 2.
Reset sequence
Line number
Time axis
Frame time
Integration time
Figure 15: Rolling shutter operation
In Figure 15, we schematically indicate the relative shift of the integration times of
different lines during the rolling shutter operation. Each line is read and reset in a
sequential way. The integration time is the same for all lines, but shifted in time. The
integration time can be varied through the INT_TIME register (in number of lines).
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3.8
High dynamic range modes
3.8.1 Double slope integration
The IBIS4-6600 has a feature to increase the optical dynamic range of the sensor;
called double slope integration. The pixel response can be extended over a larger
range of light intensities by using a “dual slope integration” (patents pending). This is
obtained by the addition of charge packets from a long and a short integration time in
the pixel during the same exposure time.
1.6
1.4
1.2
Output signal [V]
1.8
1
0.8
0.6
Dual slope operation
Long integration time
Short integration time
0.4
0.2
Relative exposure (arbitrary scale)
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Figure 16: Double slope response curve
Figure 16 shows the response curve of a pixel in dual slope integration mode. The
curve also shows the response of the same pixel in linear integration mode, with a
long and short integration time, at the same light levels.
Dual slope integration is obtained by:
Feeding a lower supply voltage to VDD_RESET_DS (e.g. apply 2.0V to
2.5V). Note that for normal (single slope operation VDD_RESET_DS should
have the same value as VDD_RESET. The difference between
VDD_RESET_DS and VDD_RESET determines the range of the high
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sensitivity, thus the output signal level at which the transition between high
and low sensitivity occurs.
Put the amplifier gain to the lowest value where the analog output swing
covers the ADC’s digital input swing. Increasing the amplification too much
will likely boost the high sensitivity part over the whole ADC range.
The electronic shutter determines the ratio of integration times of the two
slopes. The high sensitivity ramp corresponds to “no electronic shutter”, thus
maximal integration time (frame read out time). The low sensitivity ramp
corresponds to the electronic shutter value that would have been obtained in
normal operation.
Examples of the double slope (high dynamic range) mode can be found at
http://www.fillfactory.be/htm/technology/htm/dual-slope.htm.
3.8.2 Non-destructive readout (NDR)
The default mode of operation of the sensor is with FPN correction (double
sampling). However, the sensor can also be read out in a non-destructive way. After a
pixel is initially reset, it can be read multiple times, without resetting. The initial reset
level and all intermediate signals can be recorded. High light levels will saturate the
pixels quickly, but a useful signal is obtained from the early samples. For low light
levels, one has to use the later or latest samples.
time
Figure 17. Principle of non-destructive readout.
Essentially an active pixel array is read multiple times, and reset only once. The
external system intelligence takes care of the interpretation of the data. Table 11
summarizes the advantages and disadvantages of non-destructive readout.
Table 11: Advantages and disadvantages of non-destructive readout.
Advantages
Low noise – as it is true CDS. In the
order of 10 e- or below.
High sensitivity – as the conversion
capacitance is kept rather low.
Disadvantages
System memory required to record the
reset level and the intermediate samples.
Requires multiples readings of each pixel,
thus higher data throughput.
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Advantages
Disadvantages
High dynamic range – as the results Requires system level digital calculations.
includes signal for short and long
integrations times.
3.9
Sequencer
Figure 3 showed a number of control signals that are needed to operate the sensor in a
particular sub-sampling mode, with a certain integration time, output amplifier gain,
etc. Most of these signals are generated on chip by the sequencer that uses only a few
control signals. These control signals should be generated by the external system:
SYS_CLOCK, which defines the pixel rate (nominal 40 MHz),
Y_START pulse, which indicates the start of a new frame,
Y_CLOCK, which selects a new row and will start the row blanking sequence,
including the synchronization and loading of the X-register.
The relative position of the pulses will be determined by a number of data bits that are
uploaded in internal registers through a Serial to Parallel interface (SPI).
3.9.1 Internal registers
Table 12 shows a list of the internal registers with a short description. In the next
section, the registers are explained in more detail.
Table 12: List of internal registers
Register
Bit
0 (0000)
11:0
0
1:2
Name
SEQUENCER register
NDR
NDR_mode
3
RESET_BLACK
4
FAST_RESET
5
FRAME_CAL_MODE
6
LINE_CAL_MODE
7
CONT_CHARGE
8
9
GRAN_X_SEQ_LSB
GRAN_X_SEQ_MSB
Description
Selection of mode, granularity of the X
sequencer clock, calibration, …
Default value <11:0>:”000100000000”
Mode of readout:
NDR = 0: normal readout (double sampling)
NDR = 1: non-destructive readout
4 different modes of non-destructive readout (no
influence if NDR = 0)
0 = normal operation
1 = reset of pixels before readout
0 = electronic shutter operation
1 = addressing from both sides
0 = fast
1 = slow
0 = fast
1 = slow
0 = normal mode
1 = ‘continuous precharge’
Granularity of the X sequencer clock
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Register
Bit
Name
10
BLACK
11
RESET_ALL
1 (0001)
10:0
NROF_PIXELS
2 (0010)
11:0
NROF_LINES
3 (0011)
11:0
INT_TIME
4 (0100)
7:0
DELAY
5 (0101)
0:3
4:7
6:0
DELAY_PIX_VALID
DELAY_EOL/EOF
X_REG
6 (0110)
7:0
Y_REG
7 (0111)
7:0
1:0
IMAGE CORE register
TEST_mode
4:2
7:5
9:0
3:0
4
X_SUBSAMPLE
Y_SUBSAMPLE
AMPLIFIER register
GAIN<3:0>
UNITY
8 (1000)
5
ONE_OUT
6
STANDBY
9 (1001)
7:9
7:0
DELAY_CLK_AMP
DAC_RAW_REG
10 (1010)
7:0
DAC_FINE_REG
11 (1011)
7:0
DAC_DARK_REG
12 (1100)
10:0
0
ADC register
STANDBY_1
1
2
STANDBY_2
ONE
3
SWITCH
Description
0 = normal mode
1 = disconnects column amplifiers from busses,
output of amplifier equals dark reference level
0 = normal mode
1 = continuous reset of all pixels
Number of pixels to count (X direction).
Max. 2222/2 (2210 real + 12 dummy pixels).
Default value <10:0>:”01000000000”
Number of lines to count (Y direction).
Max. 3014 (3002 real + 12 dummy pixels).
Default value <11:0>:”101111000110”
Integration time.
Default value <11:0>:”000000000001”
Delay of sequencer pulses
Default value <7:0>:”00000011”
Delay of PIX_VALID pulse
Delay of EOL/EOF pulses
X start position (0 to 98).
Default value <6:0>:”0000000”
Y start position (0 to 137).
Default value <7:0>:”00000000”
Default value <7:0>:”00000000”
LSB: odd, MSB: even
0 = normal operation
sub-sampling mode in X-direction
sub-sampling mode in X-direction
Default value <9:0>:”0000010000”
Output amplifier gain setting
0 = gain setting by GAIN<3:0>
1 = unity gain setting
0 = two analog outputs
1 = multiplexing to one output (out_1)
0 = normal operation
1 = amplifier in standby mode.
Delay of pixel clock to output amplifier.
Amplifier DAC raw offset.
Default value <7:0>:”10000000”
Amplifier DAC fine offset.
Default value <7:0>:”10000000”
DAC dark reference on output bus.
Default value <7:0>:”10000000”
Default value <10:0>:”00000000000”
0 = normal operation
1 = ADC in standby
0 = multiplexing of two ADC outputs
1 = disable multiplexing
if ONE = 0: delay of output with one
(EXT_CLK = 0) or half (EXT_CLK = 1) clock
cycle
if ONE = 1: switch between two ADCs
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Register
13 (1101)
14 (1110)
15 (1111)
Bit
Name
4
EXT_CLK
5
TRISTATE
6:8
9
DELAY_CLK_ADC
GAMMA
10
BITINVERT
Description
0 = internal clock (same as clock to X shift
register and output amplifier)
1 = external clock
0 = normal operation
1 = outputs in tristate mode
Delay of clock to ADCs and digital multiplexer
0 = linear conversion
1 = ‘gamma’ law conversion
0 = no inversion of bits
1 = inversion of bits
Reserved.
Reserved.
Reserved.
3.9.2 Detailed description of registers
3.9.2.a
3.9.2.a.1
SEQUENCER register
NDR (bit 0)
In normal operation (NDR = 0), the sensor operates in double sampling mode. At the
start of each row readout, the signals from the pixels are sampled, the row is reset and
the signals from the pixels are sampled again. The values are subtracted in the output
amplifier.
When NDR is set to 1, the sensor operates in non-destructive readout (NDR) mode
(see 3.8.2).
3.9.2.a.2
NDR_mode (bit 1 and 2)
These bits only influence the operation of the sensor in case NDR (bit 0) is set to 1.
There are basically two modes for non-destructive readout (mode 1 and 2). Each
mode needs two different frame readouts (setting 1 and 2 for mode 1, setting 3 and 4
for mode 2). First a reset/readout sequence (called reset_seq hereafter) and then one
or several pure readout sequences (called read_seq hereafter). Table 13 shows an
overview of the different NDR modes.
Table 13: Overview of NDR modes.
Setting Bits NDR mode sequence
1
00
1
reset
2
01
1
read
3
10
2
reset
4
11
2
read
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MODE 1
In this mode, the sensor is readout in the same way as for non-destructive readout.
However, electronic shutter control is not possible in this case, i.e. the minimal
(integration) time between two readings is equal to the number of lines that has to be
read out (frame read time). The row lines are clocked simultaneously (left and right
clock pulses are equal).
MODE 2
In mode 2, it is possible to have a shorter integration time than the frame read time.
Rows are alternating read out with the left and right pointer. These two pointers can
point to two different rows (see INT_TIME register). The (integration) time between
two readings of the same row is equal to the number of lines that is set in the
INT_TIME register times 2 plus 1 and is minimal 1 line read time. In setting 3, the row
that is read out by the left pointer is reset and read out (first Y_CLOCK), the row that is
read out by the right pointer is read out without resetting (second Y_CLOCK). In
setting 4, both rows are read out without resetting (on the first Y_CLOCK the row is
read out by the left pointer; on the second Y_CLOCK the row is read out by the right
pointer).
For both modes, the signals are read out through the same path as with destructive
readout (double sampling) but the busses that are carrying the reset signals in
destructive readout, are in non-destructive readout set to the voltage given by
DAC_DARK.
3.9.2.a.3
Reset_black (bit 3)
If RESET_BLACK is set to 1, each line is reset before it is read out (except for the row
that is read out by the right pointer in NDR mode 2). This might be useful to obtain
black pixels.
3.9.2.a.4
Fast_reset (bit 4)
The fast reset option (FAST_RESET = 1) might be useful in case a camera shutter is
used. The fast reset is done on a row-by-row basis, not by a global reset. A global
reset means charging all the pixels at the same time, which may result in a huge peak
current. Therefore, the rows can be scanned rapidly while the left and right shift
registers are both controlled identically, so that the reset lines over the pixel array are
driven from both sides. This reduces the reset (row blanking) time (when FAST_RESET
= 1 the smallest X-granularity can be used). After the row blanking time the row is
reset and Y_CLOCK can be asserted to reset the next row.
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After a certain integration time, the read out can be done in a similar way. The Y shift
registers are again synchronized to the first row. Both shift registers are driven
identically, and all rows & columns are scanned for (destructive) readout.
FAST_RESET = 1 puts the sequencer in such mode that the left and right shift registers
are both controlled identically.
3.9.2.a.5
Output amplifier calibration (bit 5 and 6)
Bits FRAME_CAL_MODE and LINE_CAL_MODE define the calibration mode of the
output amplifier.
During every row-blanking period, a calibration is done of the output amplifier.
There are 2 calibration modes. The FAST mode (= 0) can force a calibration in one
cycle but is not so accurate and suffers from kTC noise, while the SLOW mode (= 1)
can only make incremental adjustments and is noise free. Approximately 200 or more
“slow” calibrations will have the same effect as 1 “fast” calibration.
Different calibration modes can be set at the beginning of the frame
(FRAME_CAL_MODE bit) and for every subsequent row that is read (LINE_CAL_MODE
bit).
3.9.2.a.6
Continuous charge (bit 7)
For some applications it might be necessary to use continuous charging of the pixel
columns instead of a precharge on every row sample operation.
Setting bit CONT_CHARGE to 1 will activate this function. The resistor connected to
pin CMD_COL is used to control the current level on every pixel column.
3.9.2.a.7
Internal clock granularities
The system clock is divided several times on chip.
The X-shift-register that controls the column/pixel read out, is clocked by half the
system clock rate. Odd and even pixel columns are switched to 2 separate buses. In
the output amplifier the pixel signals on the 2 busses can be combined to one pixel
stream at 40 MHz.
The clock that drives the X-sequencer can be a multiple of 2, 4, 8 or 16 times the
system clock. Table 14 shows the settings for the granularity of the X-sequencer clock
and the corresponding row blanking time (for NDR = 0). A row blanking time of 7.18
µs is the baseline for almost all applications.
Table 14: Granularity of X-sequencer clock and corresponding row blanking time (for NDR = 0).
Gran_x_seq_msb/lsb
00
X-sequencer
Row blanking
Row blanking time
2 x sys_clock
142 x TSYS_CLOCK
3.55
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01
10
11
3.9.2.a.8
4 x sys_clock
8 x sys_clock
16 x sys_clock
282 x TSYS_CLOCK
562 x TSYS_CLOCK
1122 x
7.05
14.05
28.05
Black (bit 10)
In case BLACK is set to 1, the internal black signal will be held high continuously. As
a consequence, the column amplifiers are disconnected from the busses, the busses are
set to the voltage given by DAC_DARK and the output of the amplifier equals the
voltages from the offset DACs.
3.9.2.a.9
Reset_all (bit 11)
In case RESET_ALL is set to 1, all the pixels are simultaneously put in a ‘reset’ state. In
this state, the pixels behave logarithmically with light intensity. If this state is
combined with one of the NDR modes, the sensor can be used in a non-integrating,
logarithmic mode with high dynamic range.
3.9.2.b
NROF_PIXELS register
After the internal X_SYNC is generated (start of the pixel readout of a particular row),
the PIXEL_VALID signal goes high. The PIXEL_VALID signal goes low when the pixel
counter reaches the value loaded in the NROF_PIXEL register and an EOL pulse is
generated. Due to the fact that 2 pixels are addressed at each internal clock cycle the
amount of pixels read out in one row = 2*(NROF_PIXEL + 1).
3.9.2.c
NROF_LINES register
After the internal YL_SYNC is generated (start of the frame readout with Y_START),
the line counter increases with each Y_CLOCK pulse until it reaches the value loaded
in the NROF_LINES register and an EOF pulse is generated. In NDR mode 2, the line
counter increments only every two Y_CLOCK pulses and the EOF pulse shows up only
after the readout of the row indicated by the right shift register.
3.9.2.d
INT_TIME register
When the Y_START pulse is applied (start of the frame readout), the sequencer will
generate the YL_SYNC pulse for the left Y-shift register. This loads the left Y-shift
register with the pointer loaded in Y_REG register. At each Y_CLOCK pulse, the
pointer shifts to the next row and the integration time counter increases (increment
only every two Y_CLOCK pulses in NDR mode 2) until it reaches the value loaded in
the INT_TIME register. At that moment, the YR_SYNC pulse for the right Y-shift
register is generated which loads the right Y-shift register with the pointer loaded in
Y_REG
register
(Figure
18).
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Sync of left
shift-register
Last line, followed by sync
of left shift-register
Sync of right
shift-register
Sync
Line n
Treg_int
Tint
Figure 18: Syncing of the Y-shift registers.
Treg_int Difference between left and right pointer = integration counter until value “n”
of INT_TIME register is reached = INT_TIME register.
In case of NDR = 0, the actual integration time Tint is given by
Tint
Integration time [# lines] = NROF_LINES register - INT_TIME register + 1
In case of NDR = 1, NDR mode 1, the time Tint between two readings of the same row
is given by
Tint
Integration time [# lines] = NROF_LINES register + 1
In case of NDR = 1, NDR mode 2, the times Tint1 and Tint2 between two readings of
the same row (alternatingly) are given by
Tint1
Integration time [# lines] = 2 * INT_TIME register + 1
Tint2
Integration time [# lines]
= 2 * (NROF_LINES register + 1) – (2 * INT_TIME register + 1)
3.9.2.e
DELAY register
The DELAY register can be used to delay the PIXEL_VALID pulse (bits 0:3) and the
EOL/EOF pulses (bits 4:7) to synchronize them to the real pixel values at the analog
output or the ADC output (which give additional delays depending on their settings).
The bit settings and corresponding delay is indicated in Table 15.
Table 15: Delay added by changing the settings of the DELAY register
bits
0000
0001
0010
0011
0100
0101
Delay [# SYS_CLOCK periods]
0
0
0
1
2
3
bits
1000
1001
1010
1011
1100
1101
Delay [# SYS_CLOCK periods]
6
7
8
9
10
11
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bits
0110
0111
3.9.2.f
Delay [# SYS_CLOCK periods]
4
5
bits
1110
1111
Delay [# SYS_CLOCK periods]
12
13
X_REG register
The X_REG register determines the start position of the window in the X-direction. In
this direction, there are 2208 + 2 + 12 readable pixels. In the active pixel array subsampling blocks are 24 pixels wide and the columns are read two by two and
therefore, the number of start positions equals 2208/24 +2/2 +12/2 = 92 + 1 + 6 = 99.
3.9.2.g
Y_REG register
The Y_REG register determines the start position of the window in the Y-direction. In
this direction, there are 3000 + 2 + 12 readable pixels. In the active pixel array subsampling blocks are 24 pixels wide and the rows are read one by one and therefore,
the number of start positions equals 3000/24 + 2/2 +12 = 125 + 1 + 12 = 138.
3.9.2.h
IMAGE_CORE register
Bits 0:1 of the IMAGE_CORE register defines the several test modes of the image core.
Setting 00 is the default and normal operation mode. In case the bit is set to 1, the odd
(bit 0) or even (bit 1) columns are tight to VDD. These test modes can be used to tune
the sampling point of the ADC’s to an optimal position.
Bits 2:7 of the IMAGE_CORE register define the sub-sampling mode in the X-direction
(bits 2:4) and in the Y-direction (bits 5:7). The sub-sampling modes and
corresponding bit setting are given in 3.6.
3.9.2.i
3.9.2.i.1
AMPLIFIER register
Gain (bits 0:3)
The gain bits determine the gain setting of the output amplifier. They are only
effective if UNITY = 0. The gains and corresponding bit setting are given in Table 8 in
3.5.2.
3.9.2.i.2
Unity (bit 4)
In case UNITY = 1, the gain setting of GAIN is bypassed and the gain amplifier is put
in unity feedback.
3.9.2.i.3
One_out
If ONE_OUT = 0, the two output amplifiers are active. If ONE_OUT = 1, the signals
from the two busses are multiplexed to output OUT1. The gain amplifier and output
driver of the second path are put in standby.
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3.9.2.i.4
Standby
If STANDBY = 1, the complete output amplifier is put in standby (this reduces the
power consumption significantly)
3.9.2.i.5
Delay_clk_amp
The clock that acts on the output amplifier can be delayed to compensate for any
delay that is introduced in the path from shift register, column selection logic, column
amplifier and busses to the output amplifier. Setting ‘000’ is used as a baseline.
Table 16: Delay added by changing the settings of the DELAY_CLK_AMP bits
bits Delay [ns]
000
1.7
001
2.9
010
4.3
011
6.1
3.9.2.j
bits
Delay [ns]
100 Inversion + 8.3
101 Inversion + 9.7
110 Inversion + 11.1
111 Inversion + 12.3
DAC_RAW_REG and DAC_FINE_REG register
These registers determine the black reference level at the output of the output
amplifier. Bit setting 11111111 for DAC_RAW_REG register gives the highest offset
voltage; bit setting 00000000 for DAC_RAW_REG register gives the lowest offset
voltage. Ideally, if the two output paths have no offset mismatch, the DAC_FINE_REG
register must be set to 10000000. Deviation from this value can be used to
compensate the internal mismatch (see 3.5.4).
3.9.2.k
DAC_RAW_DARK register
This register determines the voltage level that is put on the internal busses during
calibration of the output stage. This voltage level is also continuously put on the reset
busses in case of non-destructive readout (as a reset level for the double sampling
FPN correction).
3.9.2.l
3.9.2.l.1
ADC register
Standby_1 and standby_2
In case only one or none of the ADCs is used, the other or both ADCs can be put in
standby by setting the bit to 1 (this reduces the power consumption significantly).
3.9.2.l.2
One
In case OUT1 and OUT2 are both used and connected to ADC_IN1 and ADC_IN2
respectively, ONE must be 0 to use both ADCs and to multiplex their output to
ADC_D<9:0>. If ONE = 1, the multiplexing is disabled.
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3.9.2.l.3
Switch
In case the two ADCs are used (ONE = 0) and internal pixel clock (EXT_CLK = 0), the
ADC output is delayed with one system clock cycle if SWITCH = 1. In case the two
ADCs are used (ONE = 0) and an external ADC clock (EXT_CLK = 1) is applied, the
ADC output is delayed with half ADC clock cycle if SWITCH = 1.
In case only one ADC is used, the digital multiplexing is disabled by ONE = 1, but
SWITCH selects which ADC output is on ADC_D<9:0> (SWITCH = 0: ADC_1,
SWITCH = 1: ADC_2).
3.9.2.l.4
Ext_clk
In case EXT_CLK = 0, the internal pixel clock (that drives the X-shift registers and
output amplifier, i.e. half the system clock) is used as input for the ADC clock. In case
EXT_CLK = 1, an external clock must be applied to pin ADC_CLK_EXT (pin 46).
3.9.2.l.5
Tristate
In case TRISTATE = 1, the ADC_D<9:0> outputs are in tri-state mode.
3.9.2.l.6
Delay_clk_adc
The clock that finally acts on the ADCs can be delayed to compensate for any delay
that is introduced in the path from the analog outputs to the input stage of the ADCs.
The same settings apply as for the delay that can be given to the clock acting on the
output amplifier (see Table 16). The best setting will also depend on the delay of the
output amplifier clock and the load of the output amplifier. It must be used to
optimize the sampling moment of the ADCs with respect to the analog pixel input
signals. Setting ‘000’ is used as a baseline.
3.9.2.l.7
Gamma
If GAMMA is set to 0, the ADC input to output conversion is linear, otherwise the
conversion follows a ‘gamma’ law (more contrast in dark parts of the window, lower
contrast in the bright parts).
3.9.2.l.8
Bitinvert
If BITINVERT = 0, 0000000000 is the conversion of the lowest possible input voltage,
otherwise the bits are inverted.
3.9.3 Serial to Parallel interface
To upload the sequencer registers a dedicated serial to parallel interface (SPI) is
implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. The
address must be uploaded first (MSB first), then the data (also MSB first).
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The elementary unit cell is shown in Figure 18. 16 of these cells connected in series,
having a common SPI_CLK form the entire uploadable parameter block, where Dout of
one cell is connected to SPI_DATA of the next cell (max. speed 20 MHz). The
uploaded settings on the address/data bus are loaded into the correct register of the
sensor on the rising edge of signal REG_CLOCK and become effective immediately.
16 outputs to address/data bus
D
REG_CLOCK
SPI_DATA
Q
SPI_CLK
C
To address/data bus
SPI_DATA
SPI_CLK
D
Q
C
Unity Cell
Entire uploadable address block
REG_CLOCK
Dout
SPI_CLK
SPI_DATA
A3
A2
A1
D0
REG_CLOCK
Internal register
upload
Figure 19: Schematic and timing of the SPI interface
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4 Timing diagrams
4.1
Sequencer control signals
There are 3 control signals that operate the image sensor:
•
•
•
SYS_CLOCK
Y_CLOCK
Y_START
These control signals should be generated by the external system with following time
constraints to SYS_CLOCK (rising edge = active edge):
TSETUP >7.5 ns.
THOLD > 7.5 ns.
It is important that these signals are free of any glitches.
Figure 20: Relative timing of the 3 sequencer control signals
Figure 21 shows the recommended schematic for generating the control signals and to
avoid any timing problems.
Y_CLOCK
FF
Y_START
SYS_CLOCK_N
SYS_CLOCK
Figure 21: Recommended schematic for generating control signals
4.2
Basic frame and line timing
The basic frame and line timing of the IBIS4-6600 sensor is shown in Figure 21.
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Figure 22: Basic frame and line timing.
The pulse width of Y_CLOCK should be minimum 1 clock cycle and 3 clock cycles for
Y_START. As long as Y_CLOCK is applied, the sequencer stays in a suspended state.
T1
Row blanking time: During this period, the X-sequencer generates the control
signals to sample the pixel signal and pixel reset levels, and start the readout
of one line. It depends on the granularity of the X-sequencer clock (see Table
14).
T2
Pixels counted by pixel counter until the value of NROF_PIXELS register is
reached. PIXEL_VALID goes high when the internal X_SYNC signal is
generated, in other words when the readout of the pixels is started.
PIXEL_VALID goes low when the pixel counter reaches the value loaded in the
NROF_PIXELS register. EOL goes high SYS_CLOCK cycle after the falling edge
of PIXEL_VALID.
T3
EOF goes high when the line counter reaches the value loaded in the
NROF_LINES register and the line is read (PIXEL_VALID goes low).
Both EOF and EOL can be tied to Y_START (EOF) and Y_CLOCK (EOL) if both signals
are delayed with at least 2 SYS_CLOCK periods to let the sensor run in a fully
automatic way.
4.3
Pixel output timing
4.3.1 Two outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after 4 SYS_CLOCK cycles
when the internal X_SYNC (= start of PIXEL_VALID output) has appeared (see Figure
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22). The PIXEL_VALID and EOL / EOF pulses can be delayed by the user through the
DELAY register.
T1
Row blanking time (see Table 14)
T2
4 SYS_CLOCK cycles.
N-1
Figure 23: Pixel output timing (two outputs).
4.3.2 Multiplexing to one output
The pixel signal at the OUT1 output becomes valid after 5 SYS_CLOCK cycles when
the internal X_SYNC (= start of PIXEL_VALID output) has appeared (see Figure 23).
The PIXEL_VALID and EOL / EOF pulses can be delayed by the user through the DELAY
register.
T1
Row blanking time
T2
5 SYS_CLOCK cycles.
Figure 24: Pixel output timing (one output)
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4.3.3 ADC timing
4.3.3.a
Two analog outputs
Figure 25: ADC timing using two analog outputs
Figure 25 shows the timing of the ADC using two analog outputs. Internally, the
ADCs sample on the falling edge of the ADC_CLOCK (in case of internal clock, the
clock is half the SYS_CLOCK).
T1
Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total
pipeline delay of 4 pixels.
4.3.3.b
One analog output
Figure 26: ADC timing with using analog output
Figure 26 shows the timing of the ADC using one analog output. Internally, the ADC
samples on the falling edge of the ADC_CLOCK.
T1
The ADC has a pipeline delay of 2 ADC_CLOCK cycles.
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5 Pin list
Table 17 is a list of all the pins and their function. In total, there are 68 pins. All pins
with the same name can be connected together.
Table 17: Pin list
Pin Pin name
Pin
type
Expected
Pin description
Voltage [V]
1
CMD_COL_CTU
Input
0
2
CMD_COL
Input
1.08
3
CMD_COLAMP
Input
0.66
4
CMD_COLAMP_CTU
Input
0.37
5
RCAL_DAC_DARK
Input
1.27 @ code
128
DAC_DARK
reg
6
RCAL_DAC_OUT
Input
0
7
8
9
10
VDDA
GNDA
VDDD
GNDD
Power
Power
Power
Power
2.5
0
2.5
0
11
CMD_OUT_1
Input
0.78
12
CMD_OUT_2
Input
0.97
13
CMD_OUT_3
Input
0.67
14
SPI_CLK
Input
-
15
SPI_DATA
Input
-
16
VDDAMP
Power
2.5
Biasing of columns (ctu). Decouple
with 100 nF to GNDA.
Biasing of columns. Connect to VDDA
with R = 10 kΩ and decouple to GNDA
with C = 100 nF.
Biasing of column amplifiers. Connect
to VDDA with R = 100 kΩ and
decouple to GNDA with C = 100 nF.
Biasing of column amplifiers. Connect
to VDDA with R = 10 MΩ and
decouple to GNDA with C = 100 nF.
Biasing of DAC for dark reference.
Can be used to set output range of
DAC.
Default: decouple to GNDA with C =
100 nF.
Biasing of DAC for output dark level.
Can be used to set output range of
DAC. Default: connect to GNDA.
VDD of analog part [2.5 V].
GND (&substrate) of analog part.
VDD of digital part [2.5 V].
GND (&substrate) of digital part.
Biasing of first stage output amplifiers.
Connect to VDDAMP with R = 50 kΩ
and decouple to GNDAMP with C =
100 nF.
Biasing of second stage output
amplifiers. Connect to VDDAMP with
R = 25 kΩ and decouple to GNDAMP
with C = 100 nF.
Biasing of third stage output amplifiers.
Connect to VDDAMP with R = 100 kΩ
and decouple to GNDAMP with C =
100 nF.
Clock of digital parameter upload.
Shifts on rising edge.
Serial address and data input. 16 bit
word. Address first. MSB first.
VDD of analog output [2.5 V] (Can be
connected to VDDA).
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Pin Pin name
Pin
type
Expected
Pin description
Voltage [V]
17
CMD_FS_ADC
Input
0.73
18
CMD_SS_ADC
Input
0.73
19
CMD_AMP_ADC
input
0.59
20
GNDAMP
Ground
21
OUT1
Output
0
Black level: 1
@ code 190
DAC_RAW reg.
22
ADC_IN1
Input
See OUT1.
23
VDDAMP
Power
2.5
24
OUT2
Output
25
26
27
28
29
ADC_IN2
VDDD
GNDD
GNDA
VDDA
Input
Power
Power
Power
Power
Black level: 1
@ code 190
DAC_RAW reg.
See OUT2.
2.5
0
0
2.5
30
REG_CLOCK
Input
-
31
32
33
34
35
36
37
38
SYS_CLOCK
SYS_RESET
Y_CLK
Y_START
GNDD_ADC
VDDD_ADC
GNDA_ADC
VDDA_ADC
Input
Input
Input
Input
Power
Power
Power
Power
0
2.5
0
2.5
39
VHIGH_ADC
Input
2.37
40
VLOW_ADC
Input
0.59
41
42
43
44
GNDA_ADC
VDDA_ADC
GNDD_ADC
VDDD_ADC
Power
Power
Power
Power
0
2.5
0
2.5
Biasing of first stage ADC. Connect to
VDDA_ADC with R = 50 kΩ and
decouple to GNDA_ADC with C = 100
nF.
Biasing of second stage ADC. Connect
to VDDA_ADC with R = 50 kΩ and
decouple to GNDA_ADC.
Biasing of input stage ADC. Connect to
VDDA_ADC with R = 180 kΩ and
decouple to GNDA_ADC with C = 100
nF.
GND (&substrate) of analog output.
Analog output 1.
Analog input ADC 1.
VDD of analog output [2.5 V] (Can be
connected to VDDA).
Analog output 2.
Analog input ADC 2.
VDD of digital part [2.5 V].
GND (&substrate) of digital part.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
Register clock. Data on internal bus is
copied to corresponding registers on
rising edge.
System clock defining the pixel rate.
Global system reset.
Line clock.
Start frame readout.
GND (&substrate) of digital part ADC.
VDD of digital part [2.5 V] ADC.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
ADC high reference voltage (e.g.
connect to VDDA_ADC with R = 144
Ω and decouple to GNDA_ADC with C
= 100 nF.
ADC low reference voltage (e.g.
connect to GNDA_ADC with R = 59 Ω
and decouple to GNDA_ADC with C =
100 nF.
GND (&substrate) of analog part.
VDD of analog part [2.5 V].
GND (&substrate) of digital part ADC.
VDD of digital part [2.5 V] ADC.
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Pin Pin name
Pin
type
Expected
Pin description
Voltage [V]
45
VDD_RESET_DS
Power
46
ADC_CLK_EXT
Input
2.5 (for no
dual slope)
-
47
EOL
Output
-
48
EOF
Output
-
49
PIX_VALID
Output
-
50
TEMP
Output
-
51
52
ADC_D<9>
VDD_PIX
Output
Power
2.5
53
GND_AB
Power
0
54
55
56
57
58
59
ADC_D<8>
ADC_D<7>
ADC_D<6>
ADC_D<5>
ADC_D<4>
ADC_D<3>
Output
Output
Output
Output
Output
Output
-
60
VDD_RESET
Power
2.5
61
62
63
ADC_D<2>
ADC_D<1>
ADC_D<0>
Output
Output
Output
-
64
BS_RESET
Input
-
65
BS_CLOCK
Input
-
66
BS_DIN
Input
-
67
BS_BUS
Output
-
68
CMD_DEC
Input
0.74
Variable reset voltage (dual slope).
External ADC clock.
Diagnostic end of line signal (produced
by sequencer), can be used as Y_CLK.
Diagnostic end of frame signal
(produced by sequencer), can be used
as Y_START.
Diagnostic signal. High during pixel
readout.
Temperature measurement. Output
voltage varies linearly with
temperature.
ADC data output (MSB).
VDD of pixel core [2.5 V].
Anti-blooming ground. Set to 1 V for
improved anti-blooming behavior.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
Reset voltage [2.5 V]. Highest voltage
to the chip. 3.3 V for extended dynamic
range or ‘hard reset’.
ADC data output.
ADC data output.
ADC data output (LSB).
Boundary scan (allows debugging of
internal nodes): reset.
Boundary scan (allows debugging of
internal nodes): clock.
Boundary scan (allows debugging of
internal nodes): in.
Boundary scan (allows debugging of
internal nodes): bus.
Biasing of X and Y decoder. Connect
to VDDD with R = 50 kΩ and decouple
to GNDD with C = 100 nF.
Note on power-on behavior
At power-on, the chip is in an undefined state. It is advised that the power-on is
accompanied by the assertion of the SYS_CLOCK and a SYS_RESET pulse that puts all
internal registers in their default state (all bits are set to 0). The X-shift registers are in
a defined state after the first X_SYNC which occurs a few microseconds after the first
Y_START and Y_CLOCK pulse. Prior to this X_SYNC, the chip may draw more current
from the analog power supply VDDA. It is therefore favorable to have separate analog
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and digital supplies. The current spike (if there will be any) may also be avoided by a
slower ramp-up of the analog power supply or by disconnecting the resistor on pin 3
(CMD_COLAMP) at start-up.
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6 Pad positioning and packaging
6.1
Bare die
The IBIS4-6600 image sensor has 68 pins, 17 pins on each side. The die size from
pad-edge to pad-edge (without scribe-line) is
9120.10 µm (X) by 11960.10 µm (Y)
Scribe lines will take about 100 to 150 µm extra on each side.
Pin 1 is located in the middle of the left side, indicated by a “1” on the layout.
A logo and some identification tags can be found on the lower right of the die (see
Figure 25).
Pad 60
Bonding
Pad 44
Probe
Pad 61
Pad 43
7777.00 µm
(2222 * 3.5)
10549.00 µm
(3014 * 3.5)
11960.10µm
4404.47 µm
Pixel array center
Pad 1
Origin
(0,0)
Test diodes
Bonding
6427.00 µm
Probe
Probe
Bonding
Identification
Pixel 0,0
Pad 27
Pad 9
Pad 10
Probe
Bonding
9120.10µm
Pad 26
Figure 27: Layout of the IBIS4-6600 sensor
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6.2
Bonding pads
The pad size is 100 µm by 100 µm.
Every pin has double bonding pads, one for bonding, the other for wafer probing:
-
Horizontal pads on the top and bottom:
o Horizontal pitch is 537.5 µm.
o Left pad for wafer probing on the bottom, right pad on the top.
o Right pad for bonding on the bottom, left pad on the top.
-
Vertical pads on the left and the right:
o Vertical pitch is 715 µm.
o Upper pad is for wafer probing on the right, lower pad on the left.
o Lower pad is for bonding on the right, upper pad on the left.
The origin of all coordinates in the tables is located in the centre of the pad at pin
location 1. The distance between the centre of the probe pad and the centre of the
bonding pad of the same pin equals 120 µm.
6.2.1 Probe pad positions
Table 18 shows the position of the pads for wafer probing.
Table 18: Probe pad positions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X (µm)
0
0
0
0
0
0
0
0
0
145.05
682.55
1220.05
1757.55
2295.05
2832.55
3370.05
3907.55
4445.05
4982.55
5520.05
Probe pad
Y (µm)
Pin
0
-715
-1430
-2145
-2860
-3575
-4290
-5005
-5720
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
X (µm)
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
8865.05
8327.55
7790.05
7252.55
6715.05
6177.55
5640.05
5102.55
4565.05
4027.55
3490.05
Y (µm)
-120
595
1310
2025
2740
3455
4170
4885
5600
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
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Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
X (µm)
Probe pad
Y (µm)
Pin
6057.55
6595.05
7132.55
7670.05
8207.55
8745.05
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5985.05
-5840
-5125
-4410
-3695
-2980
-2265
-1550
-835
55
56
57
58
59
60
61
62
63
64
65
66
67
68
X (µm)
2952.55
2415.05
1877.55
1340.05
802.55
265.05
0
0
0
0
0
0
0
0
Y (µm)
5865.05
5865.05
5865.05
5865.05
5865.05
5865.05
5720
5005
4290
3575
2860
2145
1430
715
6.2.2 Bonding pad positions
Table 199 shows the position of the pads for bonding.
Table 19: Bonding pad positions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
X (µm)
0
0
0
0
0
0
0
0
0
265.05
802.55
1340.05
1877.55
2415.05
2952.55
3490.05
4027.55
4565.05
5102.55
5640.05
6177.55
6715.05
7252.55
7790.05
8327.55
Bonding pad
Y (µm)
Pin
0
-715
-1430
-2145
-2860
-3575
-4290
-5005
-5720
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
-5865.05
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
X (µm)
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
8745.05
8207.55
7670.05
7132.55
6595.05
6057.55
5520.05
4982.55
4445.05
3907.55
3370.05
2832.55
2295.05
1757.55
1220.05
682.55
Y (µm)
120
835
1550
2265
2980
3695
4410
5125
5840
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
5985.05
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Pin
26
27
28
29
30
31
32
33
34
X (µm)
8865.05
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
9010.1
Bonding pad
Y (µm)
Pin
-5865.05
-5600
-4885
-4170
-3455
-2740
-2025
-1310
-595
60
61
62
63
64
65
66
67
68
X (µm)
145.05
0
0
0
0
0
0
0
0
Y (µm)
5985.05
5720
5005
4290
3575
2860
2145
1430
715
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6.3
Package drawing
6.3.1 Technical drawing of the 68-pins LCC package
Figure 28: Top view (all dimensions in inch).
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Figure 29: Side view (all dimensions in inch).
Table 20: Side view dimensions.
Dimension
A
B
C
D
E
F
G
Description
Glass (thickness)
Die – Si (thickness)
Die attach-bondline (thickness)
Glass attach-bondline
(thickness)
Imager to lid-outer surface
Imager to lid-inner surface
Imager to seating plane of pkg
Min
0.037
0.002
0.002
(inch)
Typ
0.039
0.029
0.004
0.004
Max
0.041
Min
0.950
0.006
0.006
0.030
0.030
0.081
0.039
0.061
(mm)
Typ
1.000
0.740
0.060
0.070
Max
1.050
0.090
0.110
2.048
0.978
1.562
D- Glass lid sealing thickness
A
E
F
G
C- Die attach thickness
B - Die
Figure 30: Side view dimensions.
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Figure 31: Back view (all dimensions in inch).
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6.3.2 Bonding of the IBIS4-6600 sensor in the 68-pins LCC package
Figure 32. Bonding scheme.
The middle of the die corresponds with the middle of the package cavity (± 50 µm).
Pixel 0,0 is located at x = -4023 um , y = -4806 um (mechanical centre of the
die/package is x = 0, y = 0).
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6.4
Glass lid specifications
6.4.1 Color sensor
A STD-1 glass lid will be used as NIR cut-off filter on top of the IBIS4-6600-C color
image sensor. Figure 26 shows the transmission characteristics of the STD-1 glass lid.
Figure 33: Transmission characteristics of the S8612 glass used as NIR cut-off filter.
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6.4.2 Monochrome sensor
A D263 glass will be used as protection glass lid on top of the IBIS4-6600
monochrome sensors. The refraction index of the D263 glass lid is 1.52. Figure 33
shows the transmission characteristics of the D263 glass.
100
90
Transmission [%]
80
70
60
50
40
30
20
10
0
400
500
600
700
800
900
Wavelength [nm]
Figure 34: Transmission characteristics of the D263 glass lid.
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7 Boundary scan test structures
Table 20 summarizes the pins that can be used to scan through internal nodes. In case
testing is not needed, these pins can be left floating.
Table 21: Boundary scan pins
Boundary scan pins
64
65
66
67
BS_RESET
BS_CLOCK
BS_DIN
BS_BUS
input
input
input
output
Boundary scan: reset
Boundary scan: clock
Boundary scan: in
Boundary scan: bus
The following signals can be connected to the bus (make sure to have only one 1 in
the scan registers at any time) (see Table 220).
Table 22: Internal signals that can be connected to the boundary scan bus.
Internal signals
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
eos_yl_shift
clk_x_seq
sync_x_seq
clk_y_seq
sync_yl_seq
reset_seq
tri_l_seq
select_seq
sub_x<1>
sub_x<2>
sub_x<3>
sub_x<4>
sub_x<5>
sub_y<1>
sub_y<2>
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
sub_y<3>
sub_y<4>
sub_y<5>
address<3>
address<2>
address<1>
address<0>
data<11>
data<10>
data<9>
data<8>
data<7>
data<6>
data<5>
data<4>
31
32
33
34
35
36
37
38
39
40
41
42
43
44
data<3>
data<2>
data<1>
data<0>
eos_yr_shift
eos_x_shift
sync_yr_shift
tri_r_seq
cal_seq
slowfast_seq
black_seq
precharge_seq
sample_S_seq
sample_R_seq
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8 Storage and handling
8.1
Storage conditions
Description
Minimum
Temperature
-10
Temperature
-10
Note: RH = Relative Humidity
8.2
Maximum
66
38
Units
°C
°C
Conditions
@ 15% RH
@ 86% RH
Handling and solder precautions
Special care should be given when soldering image sensors with color filter arrays
(RGB color filters), onto a circuit board, since color filters are sensitive to high
temperatures. Prolonged heating at elevated temperatures may result in deterioration
of the performance of the sensor. The following recommendations are made to ensure
that sensor performance is not compromised during end-users’ assembly processes.
Board Assembly:
Device placement onto boards should be done in accordance with strict ESD controls
for Class 0, JESD22 Human Body Model, and Class A, JESD22 Machine Model
devices. Assembly operators should always wear all designated and approved
grounding equipment; grounded wrist straps at ESD protected workstations are
recommended including the use of ionized blowers. All tools should be ESD
protected.
Manual Soldering:
When a soldering iron is used the following conditions should be observed:
Use a soldering iron with temperature control at the tip.
The soldering iron tip temperature should not exceed 350°C.
The soldering period for each pin should be less than 5 seconds.
Reflow Soldering:
Figure 34 shows the maximum recommended thermal profile for a reflow soldering
system. If the temperature/time profile exceeds these recommendations damage to the
image sensor may occur.
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Figure 35: Reflow soldering temperature profile
Precautions and cleaning:
Avoid spilling solder flux on the cover glass; bare glass and particularly glass with
antireflection filters may be adversely affected by the flux. Avoid mechanical or
particulate damage to the cover glass.
It is recommended that isopropyl alcohol (IPA) is used as a solvent for cleaning the
image sensor glass lid. When using other solvents, it should be confirmed beforehand
whether the solvent will dissolve the package and/or the glass lid or not.
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9 Ordering Information
Table 23: FillFactory and Cypress part numbers
FillFactory Part Number
Cypress Semiconductor Part Number
IBIS4-6600-M-1
CYII4SM6600AA-HBC – Preliminary
IBIS4-6600-M-2
CYII4SM6600AA-QBC – Preliminary
IBIS4-6600-C-1
CYII4SC6600AA-HAC – Preliminary
IBIS4-6600-C-2
CYII4SC6600AA-QAC – Preliminary
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Disclaimer
The IBIS4-6600 sensor is only to be used for non-low vision aid applications. A strict
exclusivity agreement prevents us to sell the IBIS4-6600 sensor to customers who
intend to use it for the above specified applications.
FillFactory image sensors are only warranted to meet the specifications as described
in the production data sheet. FillFactory reserves the right to change any information
contained herein without notice.
Please contact [email protected] for more information.
Revision changes
No.
1.0
1.1
Date
18-Dec-03
25-Mar-04
1.2
16-Sep-04
1.3
04-Jan-05
Description of revision
Origination.
1.3 Part numbers updated.
2.2.1 Fill factor and dark current value updated.
2.2.2 The QE is thus … sentence updated.
2.4.3 DC electrical conditions updated.
6.3.1 Package drawings updated.
8.2 Reflow soldering recommendations added.
Figure 20, 22, 23, 23 and 24 redrawn.
3.2.3 Color filter response updated.
3.4 Minimum step size X-direction is 24.
3.9.1 Internal sequencer. Default values added.
4.2 Both EOL and EOF can be… sentence updated.
4.3.1 Figure 23 updated.
4.3.3 ADC timing updated.
5 Pin list. Description of pin 1 updated.
6.4 Refraction index of cover glass lids added.
6.4.1 Response curve of color cover glass lid updated.
8.2 Reflow soldering: note deleted.
Added Cypress equivalent part number, ordering
information.
Restricted use information added in disclaimer.
Added Cypress Document # 38-05708 Rev ** in the
document footer.
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APPENDIX A: IBIS4 Evaluation Kit
For evaluating purposes an IBIS4 evaluation kit is available.
The IBIS4 evaluation kit consists of a multifunctional digital board (memory,
sequencer and IEEE 1394 Fire Wire interface) and an analog image sensor board.
Visual Basic software (under Win 2000 or XP) allows the grabbing and display of
images and movies from the sensor. All acquired images and movies can be stored in
different file formats (8 or 16-bit). All setting can be adjusted on the fly to evaluate
the sensors specs. Default register values can be loaded to start the software in a
desired state.
Figure 36: Content of the IBIS4 evaluation kit
Please contact Fillfactory ([email protected]) if you want any more information
on the evaluation kit.
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Document History Page
Document Title:
IBIS4-6600 High Resolution 6.6MPixel Rolling Shutter CMOS Image
Sensor
Document Number: 38-05708
Rev.
**
ECN
No.
310213
Issue Date
See ECN
Orig. of
Change
SIL
Description
of Change
Initial
Cypress
release
(EOD)
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