NCP1871 D

NCP1871
Narrow Voltage DC Battery
Charger
The NCP1871 is a NVDC switching battery charger designed for
2−3−4 battery cell applications such as ultra books or tablets. It is
optimized for use with the mobile computing chipsets, and is also
compatible with most mobile solutions.
The NCP1871 is designed around a full NMOS DC to DC controller
that brings down the high voltage charger adapter voltage to a
regulated system supply that is in the same range as the battery pack
voltage. This limits the variation on the system supply voltage, and
improves the efficiency of the core converters. The device includes a
voltage droop monitor, charger adapter validation and blocking as well
as an intelligent battery connection control. The adapter current,
charge current and system current are closely monitored and an image
is provided to the host. The NCP1871 is fully programmable through
an I2C friendly SMBus Interface.
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1
QFN20
MN SUFFIX
CASE 485CP
MARKING DIAGRAM
XXXXX
XXXXX
ALYWG
G
Features
•
•
•
•
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
ACSN
HSDRV
SW
CBOOT
VCORE
•
•
•
SMBus Host−controlled NVDC−1 2S−4S Battery Charge Controller
Instant−on Works with No Battery or Deeply Discharged Battery
Automatic Supplement Mode with BATFET Control
Battery Removal Sensor
Programmable Switching Frequency
SMBUS Clock up to 400 kHz (I2C compatible)
Programmable Charge Current, Charge Voltage, Input Current Limit
with Interrupt Management
♦ ±0.5% Charge Voltage Regulation up to 18.08 V
♦ ±3% Input/Charge Current Regulation up to 8.064 A
Support Battery LEARN Function
Support Shipping Mode and Hard System Reset
Ultra−Low Quiescent Current of 10 mA at OFF Mode and High PFM
Light Load Efficiency 80% at 20 mA Load to Meet Energy Star and
ErP Lot6
Full NMOS Solution
Current and Power Monitoring
3.5 mm x 3.5 mm QFN−20 Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ACSP
RBDRV
VIN
VSEL
VINOK
1
20 19 18 17 16
15
2
14
GND
3
13
4
12
5
6
7
8
9
11
10
LSDRV
BCSP
BCSN
BATDRV
VBAT
PRHOTB
PMO
SDA
SCL
TS
•
•
•
•
•
•
•
(Top View)
Typical Applications
• Ultrabook
• Notebook
• Tablet PC
ORDERING INFORMATION
Device
NCP1871MNTXG
Package
Shipping†
QFN20
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 0
1
Publication Order Number:
NCP1871/D
NCP1871
AC
ADAPTOR
RIN
QAC
QRB
QLS
RAC
QHS
DF
CBOOT
LX
COUT1
COUT2
SYSTEM
LOAD
CAC
CIN
RCELL
VIN
VDD
RBDRV
ACSP
ACSN HSDRV
SW CBOOT LSDRV
BCSP
VSEL
RBC
10k
BCSN
BATDRV
NCP1871
SCL
QBAT
VBAT
RTS
PRHOTB
PMO
TS
RPMO
VCORE
GND
CCORE
Figure 1. Typical Application Circuit
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2
RUP
VINOK
SDA
HOST
CBAT
BATTERY
PACK
+5V
ACSN
HSDRV
SW
CBOOT
VCORE
NCP1871
1
20 19 18 17 16
15
2
14
GND
3
13
12
4
5
6
7
8
9
11
10
LSDRV
BCSP
BCSN
BATDRV
VBAT
PRHOTB
PMO
SDA
SCL
TS
ACSP
RBDRV
VIN
VSEL
VINOK
Figure 2. Pin Out Description (Top View)
Table 1. PIN FUNCTIONAL DESCRIPTION
Pin
Name
Type
Description
1
ACSP
ANALOG INPUT
2
RBDRV
ANALOG OUTPUT
3
VIN
ANALOG INPUT
Charger Adapter Input. Bypass with a Damping network
4
VSEL
ANALOG INPUT
Adapter detection input. Program adapter valid input threshold by connecting a
resistor divider from adapter input to VSEL pin to GND pin. Connect a serial resistance of 220 kW to select 3−4 Cells default setting.
5
VINOK
OPEN DRAIN OUTPUT
Charge Adapter Valid Output. Signals the VIN is within the target range.
Open drain output requiring an external pull up. Also use for short pulse signal interrupt generation
6
PRHOTB
OPEN DRAIN OUTPUT
Processor Hot Signal Output. Pulled low to reduce processor speed based on BCSP.
7
PMO
ANALOG OUTPUT
8
SDA
DIGITAL IN/OUT
Control Bus Data Line.
9
SCL
DIGITAL INPUT
Control Bus Clock Line.
Charger Adapter Current Sense Positive terminal. Use a 10 mW sense resistor
RAC. Bypass ACSP with a 10 mF capacitor
Reverse Blocking FET Driver. Drives the gate of the RBFET NMOS
Can also drive gate optional ACFET NMOS.
Current based indication of system power. Amplified version of the adapter power,
the battery power or sum of both.
10
TS
ANALOG INPUT
Battery Presence Detection. Connect this pin to the battery thermistor sensor.
11
VBAT
ANALOG IN/OUT
Battery Connection. Bypass with at least 10 mF capacitor.
12
BATDRV
ANALOG OUTPUT
13
BCSN
ANALOG INPUT
Battery Current Sense Negative Terminal. Use a 10 mW sense resistor RBC.
14
BCSP
ANALOG INPUT
Battery Current Sense Positive Terminal. Use a 10 mW sense resistor RBC.
15
LSDRV
ANALOG OUTPUT
Low Side Switch Driver. Drives the gate of the DC to DC low side NMOS.
16
VCORE
ANALOG OUTPUT
Core Voltage. Do not connect load on this pin. Bypass with a 2.2 mF capacitor
17
CBOOT
ANALOG IN/OUT
18
SW
ANALOG OUTPUT
Switching Node. Connection to the 2.2 mH inductor.
19
HSDRV
ANALOG OUTPUT
High Side Switch Driver. Drives the gate of the DC to DC high side NMOS. Supplied
from the bootstrap capacitor.
20
ACSN
ANALOG INPUT
−
EXPOSE
PAD
GROUND
Battery FET Driver.
Bootstrap Capacitor Connection.
Charger Adapter Current Sense Negative terminal.
Use a 10 mW sense resistor RAC.
Internally connected to ground
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3
NCP1871
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN , RBDRV (Note 1)
VMR_AC
−0.3 to +30
V
ACSP, ACSN, HSDRV, SW, CBOOT, BCSP, BCSN, BATDRV, VBAT (Note 1)
VMR_ACS
−0.3 to +30
V
TS (Note 1)
VMR_DRP
−0.3 to +7.0
V
VMR_CBOOT
−0.3 to +7.0
V
VMR_LV
−0.3 to +7.0
V
VDG
IDG
−0.3 to +7.0 V
20
V
mA
Human Body Model (HBM) ESD Rating are (Note 2)
ESD HBM
1500
V
Charged Device Model (CDM) ESD Rating are (Note 2)
ESD CDM
750
CBOOT with respect to SW (JEDEC standard JESD22−A108)
LSDRV, VCORE, PRHOTB, PMO, VINOK, VSEL (Note 1)
Digital Input: SCL, SDA (Note 1)
Input Voltage
Input Current
Latch up Current (Note 3):
All Digital pins( VDG)
VINOK, VSEL
All others pins.
V
ILU
mA
±10
±30
±100
Storage Temperature Range
Maximum Junction Temperature (Note 4)
Moisture Sensitivity (Note 5)
TSTG
−65 to + 150
°C
TJ
−40 to + TSD
°C
MSL
Level 1
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. With Respect to GND. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:. Human Body Model (HBM) ±1.5 kV per JEDEC standard:
JESD22−A114. Charged Device Model (CDM) ±750 V per JEDEC standard: JESD22−C101.
3. Latch up Current Maximum Rating: ±100 mA or per ±10 mA JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
Table 3. OPERATING CONDITION
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN
Operational Power Supply
4.5
VINOV
V
VDG
Digital input voltage level
0
5.5
V
TA
ISINK
Ambient Temperature Range
−40
25
VINOK sink current
+85
°C
10
mA
mF
CIN
Decoupling input capacitor
RIN
Damping resistor
2
W
CAC
Decoupling Switcher capacitor
10
mF
CBOOT
Bootstrap capacitor
100
nF
CCORE
Decoupling core supply capacitor
2.2
mF
Decoupling system capacitor
47
mF
Switcher Inductor
2.2
mH
Current sense resistor
10
mW
N−channel
MOSFET
VGS = 5 V
10
mW
10
nC
(Notes 4 and 6)
50
°C/W
COUT1, COUT2
LX
RAC, RBC
RDSONQRB, RDSONQHS,
RDSON QLS, RDSONQB
RDSON resistance
CGQRB,CGQHS, CGQLS, CGQB
Total Gate Charge
RqJA
TJ
4.7
Thermal Resistance Junction to Air
Junction Temperature Range
−40
25
+125
°C
6. The RqJA is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCP1871
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −20°C to +85°C and TJ up to + 125°C for VIN
between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 12 V (Unless otherwise noted).
Parameter
Symbol
Conditions
Min
Typ
Max
3.5
3.8
Unit
INPUT VOLTAGE
VINDET
Presence input detection threshold
VIN rising
3.2
Hysteresis
VINSYS
Charger mode detection threshold
voltage
VINLO
175
VIN – VBCSP, VIN rising
95
150
200
mV
VIN – VBCSP, VIN falling
10
50
90
mV
1.188
1.2
1.212
V
VSEL rising
Hysteresis
25
50
75
mV
VSEL rising
0.4
0.45
0.5
V
VIN rising, Ratio of VSYSMIN
103.4
106
108.6
%
Hysteresis
101.4
104
106.6
%
22
22.5
23
VCELL
Cells detection threshold
VINMINOK
Operating charger valid
threshold
Valid input high threshold
VIN rising (Note 7)
Hysteresis
VINOV
TVINOV
Max Hot Plug Rise time
V
mV
50
mV
V
Hysteresis
125
mV
ACFET present, from 0 to 30 V,
no overvoltage on ACSP
10
V/ms
RBFET only, from 0 to 30 V,
no overvoltage on BCSP
10
INPUT CURRENT LIMITING
IINLIM
Input current limit
Input Current Limit Range,
Average value.
Short Circuit Detect
TINSHORT
Short Circuit Detect Delay
mA
3328
mA
Input Current Granularity
128
mA
128 mA to 2048 mA
−64
+64
mA
2048 mA to 4096 mA
−3
+3
%
Current Ramping
IINSHORT
8064
Input Current Limit Default. (Note 8)
Input Current
Accuracy
TIIN
128
128/16
Input Current Limit ILIM
10
11
mA/ms
12
A
ms
10
BATTERY AND SYSTEM VOLTAGE
VCHG
Output voltage range
Programmable
3328
Default value, (Note 9)
Voltage regulation accuracy
Constant voltage mode, ICHG>=500 mA
Programmable granularity
VBUCKOV
System OVP
VBCSP
Rising
mV
VSYSMIN +
VSYSOFF
−0.5
0.5
%
16
mV
64/16
mV/ms
VCHG ≤ 9V
10.8
V
9 V ≤ VCHG ≤ 13.5 V
14.4
V
VCHG > 13.5 V
Voltage Ramping
VSYSOV
18080
21.6
V
SYSOV Release Threshold
Hysteresis, Ratio of VCHG Rising Edge
102
%
Buck Out of Regulation
VBCSP Rising, Ratio of VCHG Rising
Edge
104
%
BUCKOV Release Threshold
Hysteresis
102
%
7. 19 V and 14.5 V versions are available upon request
8. 2560 mA versions is available upon request
9. 5.6 V, 12.352 V and 16.592 V versions are available upon request
10. 512 mA, 1024 mA and 2048 mA versions are available upon request
11. 256 mA, 128 mA and 0 mA versions are available upon request
12. 5.6 V, 5.7 V, 5.8 V versions are available upon request
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5
NCP1871
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −20°C to +85°C and TJ up to + 125°C for VIN
between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 12 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
17792
mV
BATTERY AND SYSTEM VOLTAGE
VSYSMIN
Minimum System Voltage Range
Minimum System Voltage Default
3328
RCELL = 0 W (2−3 cells)
7936
mV
RCELL = 220 kW (3−4 cells)
12032
mV
50
mV
128
mV
SYSOFF_SEL = 0, Default
384
mV
SYSOFF_SEL = 1
256
mV
Hysteresis
Minimum System Voltage
Granularity
VSYSOFF
System Voltage Regulation Offset
CHARGE CURRENT
ICHG
Charge current range
Programmable
128
Default value, (Note 10)
Charge current accuracy
128 mA to 2048 mA
−64
2048 mA to 8064 mA
−3
I2C Programmable granularity
TICHG
Current Ramping
IEOC
End of Charge Current Range
8064
128
mA
+64
3
128
End of Charge Current Default
−64
mA
mA
128
End of Charge Current Accuracy
%
mA/ms
1024
256
End of Charge Current Granularity
mA
mA
128/16
128
mA
mA
+64
mA
REVERSE BLOCKING FET
TRBDR
RBDRV Rise Time
3 nC Load
2
ms
TRBDF
RBDRV Fall Time
10 nC Load
1
ms
RRBDL
RBDRV Output High
Referred to ground
Referred to VIN, VIN ≥ 9 V
RRBDH
VRBDL
RBDRV Output Low
VRBDH
4.45
5
30
V
5.5
V
VIN < VACSP, Referred to VIN
0
V
VIN > VACSP, Referred to ACSP
0
V
VINOK PIN
VOL
IINOKLK
FLAG output low voltage
IVINOK = 3 mA
0.4
V
Off−state leakage
VVINOK = 5 V
1
mA
mV
BATTERY MOSFET FET and PRECHARGE MODE
VPRERED
Precharge Current Reduction
Range
SYSOFF_SEL = 0,
BCSP−VSYSMIN, IBAT(DC) = 0 A.
49
399
VPRESTOP
Precharge Current Reduction
Range
BCSP−VSYSMIN, IBAT(AC) = 0 A.
0
128
VDRCON
Battery FET Reconnect Detection
Threshold
End of Charge, VBAT−BCSP
VDOPEN
Battery FET Re−open Detection
Threshold
Supplement, VBAT−BCSP
7. 19 V and 14.5 V versions are available upon request
8. 2560 mA versions is available upon request
9. 5.6 V, 12.352 V and 16.592 V versions are available upon request
10. 512 mA, 1024 mA and 2048 mA versions are available upon request
11. 256 mA, 128 mA and 0 mA versions are available upon request
12. 5.6 V, 5.7 V, 5.8 V versions are available upon request
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6
256
−1
mV
+5
mV
NCP1871
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −20°C to +85°C and TJ up to + 125°C for VIN
between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 12 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BATTERY MOSFET FET and PRECHARGE MODE
VPRE
Precharge voltage threshold
VBAT rising, Ratio of VSYSMIN
Accuracy
100
−2
Hysteresis
IPREMAX
%
512
mA
98
Precharge Current Range
Precharge Current Default
%
+2
128
Default value (Note 11)
Precharge Current Accuracy
%
512
−64
VBFH
BATDRV Output High
VBAT ≥ 3.3 V, Referred to VBAT
4.5
VBFL
BATDRV Output Low
Referred to GND
−0.3
TFBF
BATDRV Fall Time
From VBFH to VBFL, 10 nC Load
TFBR
BATDRV Rise Time
mA
+64
mA
5
8
V
0
0.3
V
200
ms
From VBFL to VBFH 3 nC Load, From
End of Charge to Supplement mode
2
ms
From VBFL to VBFH, 3 nC Load.
5
ms
I2C/SMBus
FSCL
Bus operating frequency
10
400
kHz
TI2CTO
Bus Timeout
25
35
ms
VI2CINT
Peak voltage at SCL line
2.7
5.5
V
VI2CIL
SCL, SDA low input voltage
−0.5
0.5
V
VI2CIH
SCL, SDA high input voltage
1.7
5.5
V
VI2COL
SDA low output voltage
0
0.4
V
600
1200
kHz
Sink 3 mA
BUCK CONVERTER
FSWCHG
Switching Frequency Range
Switching Frequency Default
800
Switching Frequency Granularity
200
Switching Frequency Accuracy
FSWSMB
Spread Spectrum Modulation
Bandwidth
FSWSMR
Spread Spectrum Modulation Rate
IOUTMAX
Output Current Capability
IPKMAX
kHz
−10
Ratio of FSW
kHz
+10
6
%
23
kHz
8
Maximum peak inductor current
%
A
9
A
GENERAL PARAMETERS
IOFF
IQLB
ISTBY
OFF Mode quiescent current
(Measured on BAT)
Drop Detection Quiescent Current
(Measured on BAT)
PMO block quiescent current
(Measured on BAT)
PMO_EN = 0, VDROOP_EN = 0,
VIN = 0 V, 2~3 Cells
10
PMO_EN = 0, VDROOP_EN = 0,
VIN = 0 V, 4 Cells
12
OFF mode. PMO_EN = 0,
VDROOP_EN = 1 VIN = 0 V, VBAT>
VLOBAT, VDRP_SEL ! = 00, 2~3 Cells
80
OFF mode. PMO_EN = 0,
VDROOP_EN = 1 VIN =0V, VBAT>
VLOBAT,VDRP_SEL ! = 00, 4 Cells
140
OFF mode. PMO_EN = 1, VDROOP_EN
= 0 VIN = 0 V, VBAT> 4 V
1500
7. 19 V and 14.5 V versions are available upon request
8. 2560 mA versions is available upon request
9. 5.6 V, 12.352 V and 16.592 V versions are available upon request
10. 512 mA, 1024 mA and 2048 mA versions are available upon request
11. 256 mA, 128 mA and 0 mA versions are available upon request
12. 5.6 V, 5.7 V, 5.8 V versions are available upon request
www.onsemi.com
7
mA
mA
mA
NCP1871
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −20°C to +85°C and TJ up to + 125°C for VIN
between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 12 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
GENERAL PARAMETERS
EECO
NCP1871 Efficiency
With Recommended operating condition,
VIN = 12 V , VBAT = 8.4 V, PMO_EN =
0, VDROOP_EN = 0 ECO_MODE = 1,
20 mA load
80
%
VCORE
Core supply voltage
VIN > 5.5 V
5
V
VUVLO
System UVLO
VIN or VBAT rising, SMBus register
available
TSD
4
V
135
°C
GBC_SEL = 0, Default
0.2
mA/mV
GBC_SEL = 1
0.4
mA/mV
2
mA/V
0.2
mA/mV
2
mA/V
GAIN_SEL = 0, Default
250
kA/A2
GAIN_SEL = 1
500
kA/A2
Power Monitor Output Current
Full Scale
100
mA
Power Monitor Accuracy
per channel
1.00x Full Scale
−5
5
%
0.10x Full Scale
−8.5
8.5
%
0.03x Full Scale
−20
Thermal Shutdown
CURRENT AND POWER MONITORING
GBC
Battery Current Sense Gain
ABC
Battery Voltage Sense Scaling
GAC
Adapter Current Sense Gain
AAC
Adapter Voltage Sense Scaling
KAC, KBC
IPMO
IPAC,IPBC
FPMO
VDRPREF
Mixer Gain
Power Monitor Bandwidth
VDRP Fast Comparator Reference
Voltage
DRP_SEL = 00, Relative to VSYSMIN
97
%
DRP_SEL = 01
5.6
V
DRP_SEL = 10, Default
5.8
V
DRP_SEL = 11
6
−2.1
VLOBAT_REG = 00, Ratio of VDRPREF
OFF
%
VLOBAT_REG = 01
105
107.5
VLOBAT_REG = 11
ILBSK
PRHOTB Sink Capability
Pulse Stretch Duration
VBAT_RMV
Battery Removal Detection
Threshold
128
Output 0.4 V
ms
40
mA
10
ms
BATRMV_SEL = 0, Default
2.7
2.85
3
BATRMV_SEL = 1
1.5
1.6
1.7
Battery Removal Detection time
IBAT_RMV
110
VDRP Slow Comparator Debounce
TLBPS
%
ms
VLOBAT_REG = 10, Default
TLBDEB
V
+2.1
2
VDRP Fast Comparator Debounce
VDRP Slow Comparator
Detection Level
%
kHz
VDRP Fast Comparator Accuracy
VLOBAT
20
8
ms
4
TS Input Leakage
100
7. 19 V and 14.5 V versions are available upon request
8. 2560 mA versions is available upon request
9. 5.6 V, 12.352 V and 16.592 V versions are available upon request
10. 512 mA, 1024 mA and 2048 mA versions are available upon request
11. 256 mA, 128 mA and 0 mA versions are available upon request
12. 5.6 V, 5.7 V, 5.8 V versions are available upon request
www.onsemi.com
8
V
nA
NCP1871
Charging Process
INCHG_OK = (INOK and not VINOK_SEL) or (INMINOK and VINOK_SEL)
SYS RST STATES
(HW_RST & RST_TMR) or (BAT_DIS & INDET)
UVLO
HW_RST
OFF
CONFIG
−Core OFF (10μA)
−DCDC OFF
−SMBus available
−BATFET ON
−RBFET OFF
INDET or
HW_RST
−Core = OFF (BAT_DIS)
−Core = ON (HW_RST)
−DCDC OFF
−SMBus available
−BATFET OFF
−RBFET OFF
−Core ON
−DCDC OFF
−SMBus available
−BATFET ON
−RBFET OFF
(not INDET ) &
(not BAT _DIS)
STBY STATES
INSYS and
not SYSOV and
not SYSOV_INT and
not IINSHORT_INT and
not INOVP
(HW_RST and RST_TMR)
or
(BAT_DIS & RST_TMR &
not INDET)
not INSYS or
SYSOV or
IINSHORT or
INOVP
CHARGE STATES
HOLD
TSD or
CHR_DIS or
WD_TMR or
not INCHG_OK
−Core ON
−DCDC OFF
−SMBus available
−BATFET ON
−RBFET ON
TSD or
CHR_DIS or
WD_TMR or
not INCHG_OK
10ms timer and
INCHG_OK and
not ldo_mode &
not PRE &
not (SYSOV
TSD or
CHR_DIS or
WD_tmr) and
not LEARN
10 ms timer and
INCHG_OK and
(ldo_mode or
PRE) and
not (SYSOV
TSD or
CHR_DIS or
WD_tmr)
PRE CHARGE
FULL CHARGE
PRE
−Core ON
−DCDC ON
−SMBus available
−BATFET: PRECHARGE
−RBFET ON
not PRE and not ldo_mode
−Core ON
−DCDC ON
−SMBus available
−BATFET ON
−RBFET ON
EOC or
(IEOC and IEOC_EN)
SUPPLEMENT
−Core ON
−DCDC ON
−SMBus available
−BATFET ON
−RBFET ON
not EOC
and not IEOC_EN
or LEARN
END OF CHARGE
DRCON
DOPEN and not
LEARN
ACTIVE CHARGE STATES
Figure 3. Charging State Machine
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9
−Core ON
−DCDC ON
−SMBus available
−BATFET OFF
−RBFET ON
NCP1871
Block Diagram
RBDRV
VIN
ACSP
ACSN
HSDRV
VCORE
INPUT VOLTAGE
VIN
INDET
−
Amp
+
INSYS
−
+
+
REVERSE BLOCKING FET
INSHORT
VBUCKREG
VCHG ,
VSYSMIN +
VSYSOFF
−
+
BUCKOK
− VCHG x VBUCKOV
CELL
−
HSS
+
INOK
−
VINLO
QC_DRV
VIIN
V BUCKREG
QCELL
VIBAT
V REF
−
+
+
+
SYSOV
−
VSYSOV
BATTERY AND SYSTEM VOLTAGE
LSS
CHARGE CURRENT
−
V IBAT
BUCK CONVERTER
BAT_RMV
+
VBAT
VIN
+
DOPEN
− VDOPEN
VBAT
Ideal diode
VCORE
VDRPREF
VIPREMAX
EN
VIBAT
Charge
Pump
Amp
IREF
POR
+
CLOCK
VLOBAT
Current,
Voltage,
and Clock
Reference
−
−
V PRERED
VREF
BATDRV
TSD
ACSN
BCSN
− VIEOC
VBCSP
VCORE
Amp
+
IEOC
VBAT _RMV
TS
+
PWM generator
VSEL
−
VCELL
22k
VBAT
Amp +
INPUT CURRENT LIMIT
+
BCSP
VIINSHOR
T
−
VIIN
INMINOK
VSYSMIN x −
VINMINOK
VINSYS
BUCK CONVERTER
INOVP
Drv
LSS
+
−
+
VINOV −
V BCSP
HSS
Drv
Charge
Pump
+
VINDET
Drv
+
LSDRV
SW
CBOOT
Drv
ACSP
ON/OFF
VBAT
GAC
A AC
EN
SMD Digital
& registers
KAC
PRE
Enable on POR
PMO
DRCON
IPBC
GBC
BCSP
+
BCSP
−
+ VDRCON
SDA
CHARGER CONTROL
EN
A BC
SMB Physical Interface
I@C / SMBUS
PRHOTB
+ V SYSMIN
−
IPAC
KBC
VBAT
BATTERY MOSFET AND
PRECHARGE MODE
SCL
BCSN
ACOK_DRV
Pulse Generator
POWER MONITORING
VINOK & INT
GND
Figure 4. Detailed Block Diagram
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VINOK
NCP1871
SMBUS Registers Map
SMBUS slave address (binary): b0001001x.
ChargeOption Register − Memory Location : 12h
Bit
Type
Reset
Name
RST Value
Function
0
RW
POR, TR_OFF
CHR_DIS
0
Charge is suspend when set 1
1
RW
POR, TR_OFF
EOC
0
Set 1 will jump to End of Charge state from FULL
charge: signal dictated by the Fuel Gauge
2
RW
POR, TR_OFF
IEOC_EN
0
Set 1 enable the charger end of charge detection
3
RW
POR, TR_OFF
LEARN
0
Set 1 enable the LEARN mode
4
RW
POR, TR_OFF
PMOBAT_EN
0
Set 1 enable the Battery Power monitoring circuitry
5
RW
POR, TR_OFF
PMOAC_EN
0
Set 1 enable the Input Power monitoring circuitry
6
RW
POR, TR_OFF
GAIN_SEL
0
Multiplier Gain selection
0: Full scale 100 W
1: Full scale 50 W
7
RW
POR, TR_OFF
PMO_IMO_SEL
0
0 : PMO selected
1: IMO selected
8
RW
POR, TR_OFF
GBC_SEL
0
0: Battery Current Sense Gain is 10
1: Battery Current Sense Gain is 20
9
RW
POR, TR_OFF
WDTMR_SET[0]
1
10
RW
POR, TR_OFF
WDTMR_SET[1]
0
Watchdog timer [1:0]:
00: Disable
01: 32s
10: 64s
11: 128s
11
RW
POR, TR_OFF
FREQ_SEL[0]
01
12
RW
POR, TR_OFF
FREQ_SEL[1]
DCDC frequency selection[1:0]:
00: 600 kHz
01: 800 kHz
10: 1000 kHz
11: 1200 kHz
13
RW
POR, TR_OFF
VLOBAT_REG[0]
0
14
RW
POR, TR_OFF
VLOBAT_REG[1]
1
Ratio of VDRPREF[1:0]:
00: Off
01: 105%
10: 107.5%
11: 110%
15
RW
POR, TR_OFF
VDROOP_EN
0
0: Critical Voltage Monitoring disable
1: Critical Voltage Monitoring enable
ChargeCurrent Register − Memory Location : 14h
Bit
Type
Reset
Name
RST Value
0
RW
POR, TR_OFF
IPRE_0
11
1
RW
POR, TR_OFF
IPRE_1
2
R
Not Used
3
R
Not Used
4
R
Not Used
5
R
Not Used
6
R
7
RW
POR, TR_OFF
ICHG_0
8
RW
POR, TR_OFF
ICHG_1
9
RW
POR, TR_OFF
ICHG_2
10
RW
POR, TR_OFF
ICHG_3
Function
00: 0 mA
01: 128 mA
10: 256 mA
11: 512 mA
Not Used
000001
000001 : 128 mA (Lower Clamp)
111111: 8064 mA (Higher Clamp)
Step : 128 mA
11
RW
POR, TR_OFF
ICHG_4
12
RW
POR, TR_OFF
ICHG_5
13
R
Not Used
14
R
Not Used
15
R
Not Used
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NCP1871
ChargeVoltage Register − Memory Location : 15h
Bit
Type
Reset
Name
RST Value
0
R
Not Used
1
R
Not Used
2
R
Not Used
3
R
Not Used
4
RW
POR, TR_OFF
VCHG_0
5
RW
POR, TR_OFF
VCHG_1
6
RW
POR, TR_OFF
VCHG_2
7
RW
POR, TR_OFF
VCHG_3
8
RW
POR, TR_OFF
VCHG_4
9
RW
POR, TR_OFF
VCHG_5
10
RW
POR, TR_OFF
VCHG_6
11
RW
POR, TR_OFF
VCHG_7
12
RW
POR, TR_OFF
VCHG_8
13
RW
POR, TR_OFF
VCHG_9
14
RW
POR, TR_OFF
VCHG_10
15
R
Bit
Type
Reset
Name
RST Value
Function
0
RW
POR, TR_OFF
HW_RST
0
Set 1 will disconnect the battery after RST_TMR
1
RW
POR, TR_OFF
BAT_DIS
0
Set 1 disconnect the battery when
IN unplug until the next IN plug
2
RW
POR, TR_OFF
FAULT_MSK
0
Set 1 Mask fault interuption
3
RW
POR, TR_OFF
STATUS_MSK
0
Set 1 Mask Status interruption
4
R
STATE[0]
5
R
STATE[1]
6
R
STATE[2]
7
RW
POR, TR_OFF
RST_TMR_SET[0]
0
8
RW
POR, TR_OFF
RST_TMR_SET[1]
1
9
RW
POR, TR_OFF
FREQ_S_EN
0
Frequency Spread Spectrum enable
0: Disable
1: Enable
10
RW
POR, TR_OFF
CPEXIT_EN
0
0: CP exit disable
1: CP exit Enable
11
RW
POR, TR_OFF
IEOC[0]
1
12
RW
POR, TR_OFF
IEOC[1]
0
13
RW
POR, TR_OFF
IEOC[2]
0
000: 128 mA
001: 256 mA
010: 384 mA
011: 512 mA
100: 640 mA
101: 768 mA
110: 896 mA
111: 1024 mA
14
RW
POR, TR_OFF
LDO_MODE
0
Set 1 select LDO mode
15
RW
POR, TR_OFF
ECO_MODE
1
0: No Eco Mode
1: Eco Mode
VSYSMIN +
VSYSOFF
Function
00000000000 : 3.328 V
00011010000 : 3.328 V (Lower Clamp)
10001101010 : 18.080 V (Higher Clamp)
11111111111 : 18.080 V
Step : 16 mV
Not Used
ChargeOption2 Register − Memory Location : 3Ch
Charge state [2:0]:
000: OFF
001: CONFIG
010: HOLD
011: PRECHARGE
100: FULLCHARGE
101: SUPPLEMENT
110: END OF CHARGE
111: HW_RST
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12
Reset Timer
00: 0 ms
01: 512 ms
10: 1024 ms
11: 2048 ms
NCP1871
Interrupt Register − Memory Location : 3Dh
Bit
Type
Reset
Name
RST Value
Function
0
RC
POR, OFF
EOC_INT
0
Flag End of Charge State is reached
1
RC
POR, OFF
PRE_INT
0
Flag Precharge state is reached
2
RC
POR, OFF
LEARNB_INT
0
Flag entering/exiting Learn mode
3
RC
POR, OFF
WDOG_INT
0
Flag a WatchDog Timer expired
4
RC
POR, OFF
IPEAK_INT
0
Flag IPEAK MAX is reached
5
RC
POR, OFF
INOVP_INT
0
Flag VIN> VINOV
6
RC
POR, OFF
BUCK_OVP_INT
0
Flag BUCK OV
7
R
POR, OFF
IINSHORT_INT
0
Flag IIN> IINSHORT
8
RC
POR
HW_RST_INT
0
Flag HW_RST state and HW_RST=1
9
RC
POR
BAT_DIS_INT
0
Flag HW_RST state and BAT_DIS=1
10
W1C
POR, OFF
SYSOV_INT
0
Flag System Overvoltage
11
RC
POR, OFF
BAT_RMV_INT
0
Flag battery is removed
12
R
Not Used
13
R
Not Used
14
R
Not Used
15
R
Not Used
Bit
Type
Reset
Name
RST Value
0
RW
POR, TR_OFF
VDYNPRE_EN
1
0: Dynamic precharge disable
1: Dynamic precharge enable
1
RW
POR, TR_OFF
VINOK_SEL
0
Control VINOK signal
0: INOK is set by VSEL
1 INOK is set by VSYSMIN
2
R
Not Used
3
R
Not Used
4
R
Not Used
5
R
Not Used
6
R
Not Used
7
RW
POR, TR_OFF
VSYSMIN_0
8
RW
POR, TR_OFF
VSYSMIN_1
9
RW
POR, TR_OFF
VSYSMIN_2
10
RW
POR, TR_OFF
VSYSMIN_3
11
RW
POR, TR_OFF
VSYSMIN_4
12
RW
POR, TR_OFF
VSYSMIN_5
13
RW
POR, TR_OFF
VSYSMIN_6
14
RW
POR, TR_OFF
VSYSMIN_7
15
RW
POR, TR_OFF
N_CELL_EN
MinSysVoltage Register − Memory Location : 3Eh
See electrical
characteristics
1
Function
00000000 : 3.328 V
00011010 : 3.328 V (Lower Clamp)
10001011 : 17.792 V (Higher Clamp)
11111111 : 17.792 V
Step : 128 mV
0: VSYSMIN default value detection disable
1: VSYSMIN default value detection enable
Reset Legend:
•
•
•
•
•
OFF: Set bit to RST VALUE when the charging state machine is in OFF state.
TR_OFF: Set bit to RST VALUE when the charging state machine transits to OFF state.
POR: Set bit to RST VALUE on power on reset.
W1C : Need to write 1 to reset this bit to 0
RC : Read this bit to reset to 0
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NCP1871
InputCurrent Register − Memory Location : 3Fh
Bit
Type
Reset
Name
RST Value
0
R
Not Used
1
R
Not Used
2
R
Not Used
3
R
Not Used
4
R
Not Used
5
R
Not Used
6
R
Not Used
7
RW
POR, TR_OFF
IINLIM_0
8
RW
POR, TR_OFF
IINLIM_1
9
RW
POR, TR_OFF
IINLIM_2
10
RW
POR, TR_OFF
IINLIM_3
11
RW
POR, TR_OFF
IINLIM_4
12
RW
POR, TR_OFF
IINLIM_5
13
R
Not Used
14
R
Not Used
15
R
Not Used
Bit
Type
Reset
Name
RST Value
0
RW
POR, TR_OFF
SYSOFF_SEL
0
VSYS offset selection:
0 : 384 mV
1 : 256 mV
1
RW
POR, TR_OFF
DRP_SEL[0]
10
2
RW
POR, TR_OFF
DRP_SEL[1]
VDROOP threshold selection:
00 : 97% Relative to VSYSMIN
01 : 5.6 V
10 : 5.8 V
11 : 6 V
3
RW
POR, TR_OFF
BATRMV_SEL
0
Battery removal threshold selection:
0 : 2.85 V
1 : 1.6 V
4
R
Not Used
5
R
Not Used
6
R
Not Used
7
R
Not Used
8
R
Not Used
011010
Function
000000: 128 mA
000001 : 128 mA (Lower Clamp)
111111 : 8064 mA
Step : 128 mA
ChargeOption3 Register − Memory Location : 40h
Function
9
R
Not Used
10
R
Not Used
11
R
Not Used
12
R
Not Used
13
R
Not Used
14
R
Not Used
15
R
Not Used
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14
NCP1871
ManufacturerID Register − Memory Location : FEh
Bit
Type
Reset
Name
RST Value
0
R
1
R
MAN_ID[15:0]
0
0
2
R
0
3
R
0
4
R
0
5
R
0
6
R
0
7
R
0
8
R
0
9
R
0
10
R
0
11
R
0
12
R
0
13
R
1
14
R
1
15
R
1
Bit
Type
0
R
1
R
0
2
R
0
3
R
0
4
R
0
5
R
0
6
R
0
7
R
0
8
R
0
9
R
0
10
R
0
11
R
0
12
R
0
13
R
1
14
R
1
15
R
1
Function
DeviceID Register − Memory Location : FFh
Reset
Name
RST Value
DEV_ID[15:0]
0
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15
Function
NCP1871
FUNCTIONAL DESCRIPTION
Overview
system supply voltage, hence the name Narrow Voltage DC
(NVDC), and improves efficiency of the core converters.
The device includes a voltage droop monitor, charger
adapter validation and blocking as well as an intelligent
battery connection control. The adapter current, charge
current and system current are closely monitored and an
image is provided to the host. The NCP1871 is fully
programmable through an I2C compatible SMBus interface.
In below figure, the block diagram of the NCP1871 in its
typical application is shown.
The NCP1871 is part of On Semiconductor’s growing
switching battery charger family for wireless and mobile
computing. The NCP1871 is a NVDC switching battery
charger with characteristics that makes it perfectly suited for
2−stacked battery cell applications such as ultrabooks or
tablets.
The NCP1871 is designed around a full NMOS DC to DC
controller that brings down the high voltage charger adapter
voltage to a regulated system supply that is in the same range
as the battery pack voltage. This limits the variation on the
ACFET
RBFET
HSS
RAC
AC/DC
2.2uH
VIN
RSEL
Damping network
Adapter Detection
10uF
RBDRV
Input FET
Control
ACSP
ACSN
Adapter
Detection &
Cell Select
SCL
PBC
PRHOTB
PMO
LSDRV
Battery Current
& Power Sense
Charger
Control
RBC
BCSN
Precharge
Control
Power and
Droop Monitor
BATDRV
Battery FET
Control
VIN
VBAT
GND
BATFET
VBAT
VCORE
2.2uF
LSS
BCSP
SMBus
PAC
Application
Output
Stage
Drivers
DC−DC
Controller
SDA
Host
47uF
100nF
SW
CBOOT
Adapter Current
& Power Sense
VSEL
VINOK
HSDRV
NCP1871 NVDC
Battery Charger
Core Supply
TS
10uF
Figure 5. Functional Block Diagram
input current as well as the battery charge current. The latter
is measured by means of a low impedance sense resistor.
The battery pack is connected to the system through a low
impedance NMOS. This battery FET is opened in case the
battery is depleted while the DC to DC directly supplies the
application using the system voltage as its feedback.
When charging, the battery FET is closed and the charge
current is monitored. The battery voltage is used as the
feedback voltage for the DC to DC.
When the battery is fully charged to End of Charge state,
the battery FET is opened to preserve its charge but will
assist the system in case it draws more peak power than the
charge adapter can deliver.
The DC to DC converter runs in fixed frequency PWM
mode with pulse skipping capabilities. To reduce EMI
issues, the switching frequency is selectable and a frequency
The charger adapter is connected to the application
through a reverse blocking FET that avoids the leakage from
the battery to input. The FET is made conducting when a
valid charger is detected. At the same time a signal is
generated to inform the host. Overvoltage detection will
reject high voltage charge sources while protecting the
application by blocking the high side FET of the DC to DC
converter.
The adapter current is measured by means of a low
impedance sense resistor. This information is used by the
DC to DC converter to limit the average input current.
Optionally, a second FET can be placed back−to−back in
series with the reverse blocking FET to provide additional
isolation towards the application.
The DC to DC converter supplies both the application and
charges the battery pack. It regulates its output voltage, the
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16
NCP1871
CORE
spreading feature can be enabled which can reduce peak
amplitude of the EMI energy by 10 dB. Soft start of both
output voltage and output current moderate the inrush
current.
The DC to DC converter uses external NMOS switches to
handle the high currents involved. the NCP1871 has the
capability to deliver up to 8 A. Though optimized for
2−stacked cell battery packs the NCP1871 also supports 3
and 4−stacked cell batteries.
Additional features include a voltage drop monitor that
can supervise critical system voltage, a learn mode that
allows to cycle a battery pack to re−initiate the battery pack’s
fuel gauge, and a system power monitor providing a true
analog image of the system power to the host.
The NCP1871 is controllable through a SMBus interface
that is also compatible with a 400 kHz I2C control. A
sideband interrupt signal informs the system of any event
occurring. The bus allows reading out the device status as
well as programming the different voltage and current levels
and operating modes. The NCP1871 comes in a small
3.5 x 3.5 mm QFN−20 package at 0.5 mm pitch.
The IC core is supplied from a locally generated VCORE.
The VCORE is a regulated supply that automatically takes
the highest of the AC adapter input VIN and the battery
connection VBAT as its input. The core includes a bandgap
and generates all necessary references for the circuit.
VCORE requires a bypass capacitor.
The core operates in two distinct modes: Off and Active.
In Off mode only imprecise detectors are active monitoring
the VIN pin and SMBus activity while keeping the battery
pack connected to the system. All other circuitries are
disabled. When a VIN or SMBus activity is detected, the
core transitions to the active mode where the entire core is
active including the precise bandgap and clocking. In active
mode the different functions of the IC can be enabled such
as the DCDC converter or power monitors.
The core does not operate for voltages below the under
voltage lockout threshold (VUVLO) and all internal circuitry,
both analog and digital, is held in reset.
VIN
VSYS
VBAT
ISYS
IBAT
IIN
Figure 6. Typical Charge Profile
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17
OFF
END OF CHARGE
SUPPLEMENT
END OF CHARGE
FULL CHARGE
PRE CHARGE
HOLD
CONFIG
OFF
Charge Profile
NCP1871
Pre Charge
the battery will supplement the remainder of the current to
avoid further drop. Once the system current is reduced
below the adapter current, the system voltage will again rise
above the battery voltage and the FET is opened. The battery
will not get recharged in the process as long as the charger
is not re−enabled through SMBus.
In case of a depleted battery, attaching a valid charger will
enable the DC to DC and the output voltage will be raised to
VCHG. The feedback of the DC to DC converter is taken
from BCSP. The battery FET will be used in a linear mode
to precharge the battery pack at a current IPRE. Once the
battery voltage reaches the minimum system operating
voltage VSYSMIN, the battery FET is slowly turned on and
the feedback is now taken from VBAT. Note that VSYSMIN
is to be programmed to a value lower than VCHG.
When precharging the battery, the voltage at BCSP is
permanently monitored. When the output drops towards the
VSYSMIN level, the precharge current is reduced to zero in
an analog fashion starting with BCSP being VPRERED
above the VSYSMIN level. The precharge current will drop
to zero immediately if BCSP drops across VPRESTOP
above the VSYSMIN level. The above described precharge
behavior is the default. By opting for a LDO_MODE option,
the precharge phase will be skipped. This should only be
done if the battery pack can handle a safe precharge on its
own.
DCDC Converter
The DC to DC converter uses external NMOS pass
devices for both the low side and the high side switches. To
drive the gate of the high side switch at HSDRV, a bootstrap
capacitor is used that is connected between SW and CBOOT.
This capacitor is precharged from the VCORE reference.
The gate of the low side switch is directly driven at LSDRV.
Not the drain of the high side switch, but the hot side of the
sense resistor should be considered as the input of the
converter and therefore a capacitor has to be placed at ACSP.
To avoid too high ripple in the application, the capacitor is
to be grounded to the source of the low side switch before
connecting to the system ground.
The output voltage of the DC to DC converter is regulated
to the level VCHG as set in the ChargeVoltage register.
Depending on the state of the battery FET the voltage at pin
BCSP (FET open) or the voltage at pin VBAT (FET closed)
is taken as the feedback voltage. The latter is done to avoid
any early charge current reduction due to the IR drop
between BCSP and VBAT.
Apart from the output voltage regulation, the DC to DC
converter control loop will also limit the amount of input
power from the AC adapter and the amount of current
provided to the battery. In other words, the DC to DC
converter will only be at the set output voltage if the current
limits are not hit. The input current limit is set in the
InputCurrent register, the charge current in the
ChargeCurrent register. Note that when the input current
limit is reached, the output voltage will drop automatically
thus reducing the amount of current provided to the battery.
In other words, priority is given to the system current over
the battery charge current.
When enabled, the reference for the DC to DC output
voltage is smoothly ramped. Once the output voltage ramp
has finished, the charge current is ramped up. When
reprogramming an established output voltage to a higher or
lower value, the voltage ramp is also applied. The
combination of these mechanisms limits the peak inrush
current at startup and during the transitions after SMBus
programming.
Once enabled, the converter operates in a fixed frequency
PWM mode and will pulse skip automatically when needed.
The switching frequency is selectable over a small range, it
is however not advised to apply ‘on the fly’ changes but to
use a device instance with a different default value.
During specific mode, the power consumption of the
whole system is intended to be very low. An Eco mode can
be enabled through I2C, (bit ECO_MODE, register
ChargeOption2) which increases the efficiency at very light
load (10−20 mA).
Full Charge
In case of an already connected battery, attaching a valid
charger will enable the DC to DC with VBAT as the
feedback voltage. If at the end of the voltage ramp the VBAT
is greater than VSYSMIN, the battery FET remains closed
and full charging is engaged. For VBAT below the
VSYSMIN however, the battery FET is automatically made
non−conducting, the pin BCSP taken as the feedback, and
the battery pack pre−charged as described above. By this
overlapped approach the system will remain correctly
supplied when opening the battery FET.
End of Charge
Once the battery is fully charged the battery FET is made
non−conducting. This avoids wear and tear of the battery
cells and enhances the battery pack’s lifetime. The fully
charged state is determined by the battery pack’s fuel gauge.
Through SMBus the battery charger is then disabled. This
does not mean that the DC to DC converter is disabled, just
that the battery is no longer charged. Normally, it was still
being charged with a small current before disabling charging
for a full battery, so after the battery FET is opened, the
system voltage is slightly above the battery voltage.
The end of charge detection by the charger is not the
preferred method; termination by the fuel gauge is preferred
at large due to the correlation between end of charge and
100% battery capacity. However, the end of charge detection
may be helpful as an additional means of protection. The end
of charge detection should therefore be set low. Upon an end
of charge detection an interrupt is generated.
Supplement Mode
With the FET non−conducting, the system current may
exceed the power rating of the wall charger. As a result the
system voltage will drop. When a significant BCSP drop of
VDRCON is detected, the battery FET will be turned on and
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18
NCP1871
the LC resonance created on the switch node. In absence of
prolonged switching activity, the bootstrap capacitor will
discharge. In order to maintain the capacitor charge, the low
side FET will be turned on periodically so that the bootstrap
capacitor can be recharged again to VCORE level.
To protect the DC to DC converter output transistors as
well as the inductor, a peak current limiter will limit the
cycle to cycle peak current. It uses the voltage drop over the
input current sense resistor to monitor the peak current. A
flag bit is set to inform the host about the event but the DC
to DC converter is not automatically disabled.
This particular skip mode is active when the input current
is lower than 100 mA. If so, the TONMIN is extended to
reduce switching activity and frequency as a consequence.
The buck also regulates in asynchronous mode. As soon as
ECO_MODE is set to ‘0’ whatever the input current is, the
eco mode is disabled.
The DC to DC converter switches at fairly significant
current levels which could cause conducted and radiated
EMI issues. A frequency spreading option can be enabled to
reduce the side−effects of this. By varying the switching
frequency at a constant low rate (i.e. a modulation with a
triangular waveform), the peak amplitude of the EMI energy
in the output spectrum can be reduced by about 10 dB. Note
that the amount of power itself is not reduced, just its
allocation over the frequency band.
When pulse skipping, the current in the inductor will fall
to zero for each cycle (discontinuous operation). At that
point both the low side and high side switches are
non−conducting, and the SW node will be ringing caused by
Current and Power Monitoring
The current and power monitoring block consists of an
analog output signal reflecting the amount of power taken by
the system and an open drain output signaling the host that
excessive power is drawn by the system.
The below diagram depicts the power monitoring
functionality.
IPAC = KAC ( AAC*VAC * GAC*VIAC )
ACSP
IPBC = KBC ( ABC*VBC * GBC*VIBC )
AAC
VAC
KAC
VIAC
VBC
GBC
VIBC
BCSN
KBC
IPAC
IPBC
G AC
ACSN
ABC
IPMO = IPAC + IPBC
BCSP
RPMO
Figure 7. Power Monitoring Diagram
to the PMO output. The current measurement signal is also
used by the DC to DC converter to limit the input currents
and by the adapter over current protection circuitry.
The current flowing out of and into the battery is sensed
through the sense resistor RBC connected between the pins
BCSP and BCSN. The measurement is low pass filtered to
remove any current spikes due to the transient load response
of the system. The resulting signal is multiplied with the
battery voltage at BCSN and amplified to the PMO output.
The current measurement signal is also used by the DC to
DC converter to control the charge current. The battery
power sense circuitry can be enabled in both charging and
non charging modes.
In order to inform the Host about the amount of power
used by the system, an image of the power taken from the
charger input and the battery pack is provided at the power
monitor output PMO. PMO does take into account the power
that is sourced to the battery during the charge cycle. Based
on this information, the host can determine if it is reaching
the maximum power level it is allowed to take from either
source.
The adapter current is sensed through the sense resistor
RAC connected between the pins ACSP and ACSN. The
measurement is low pass filtered to remove the current
ripple due to the DC to DC activity. The resulting signal is
multiplied with the adapter voltage at ACSP and amplified
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19
NCP1871
VOLTAGE DROOP MONITOR
The below diagram depicts the voltage monitoring functionality.
BCSP
BAT _RMV
VDRPREF
VLOBAT
INSYS
PRHOTB
PRHOTB_DRV
IINLIM_DISABLE
&
CPEXIT_EN
1 shot Pulse
Stretcher (TPS ms )
Figure 8. Critical Voltage Monitor Diagram
Input Current Limitation
The critical system voltage node, is connected to BCSP
and is monitored for a sudden drop due to high loading
conditions. A comparator with a programmable threshold is
used for this. This comparator is enable when bit
VDROOP_EN is set to 1 (register ChargeOption). For
additional adjustment, the detection level can be adjusted
with VDRP_SEL bit of ChargeOption3 register. This
comparator can be disabled under low battery conditions to
avoid false triggering (bits VLOBAT_REG, register
ChargeOption). The overall system can be enabled in both
charging and non charging modes. Note that under low
battery conditions the processor peak current will be
automatically reduced by the system so that critical voltage
droops are avoided.
The output of the drop monitor is fed into a pulse stretcher
that will ensure the PRHOTB pin will be pulled low for a
guaranteed minimum period TPS which will reduce the
processor speed (PROCHOT# pin) and thus the power
consumed. BAT_RMV and INSYS signal leads to a
PRHOTB generation as well.
Apart from the output voltage regulation, the DC to DC
converter control loop will also limit the amount of input
power from the AC adapter and the amount of current
provided to the battery. In other words, the DC to DC
converter will only be at the set output voltage if the current
limits are not hit. The input current limit is set in the
InputCurrent register. Note that when the input current limit
is reached, the output voltage will drop thus automatically
reducing the amount of current provided to the battery.
Battery FET
The battery pack is connected to the system voltage rail
through the NMOS battery FET (BATFET), driven from
BATDRV. In order to support all operating modes of the
application, the battery FET can be operated in three states;
fully conducting, non−conducting and linear mode.
When the application is in off mode and no charger is
attached, the system voltage is maintained by the battery.
The BATFET is fully conducting by BATDRV being driven
high through a charge pump to VBAT plus VPUMP. The
charge pump features a very low bias current when
maintaining BATDRV high. This current is accounted for in
the core quiescent current. When the application is operating
without any charger attached, the battery FET is by default
fully conducting when the VBAT is greater than the
undervoltage threshold UVLO while non−conducting for
lower voltages (fully depleted battery).
Watchdog Timer Description
The battery charging cycle is under control of the host. It
may happen that the host is too busy to survey the charger or
that the system is stuck. As a safety measure therefore a
watchdog timer is started after each I2C write in charge
current or/and voltage setting registers during active charge
states. When the watchdog timer is enabled, the charge will
be suspended if IC does not receive any write charge voltage
or write charge current command within the watchdog time
period. This timer can be set or disabled through SMBus
registers.
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20
NCP1871
Adapter Detection and Removal
VINOK Output
The AC adapter is connected to the input VIN which is
permanently monitored by a set of comparators. A first
imprecise low current comparator will detect the presence of
an input voltage greater than VINDET. This comparator is
always enabled even when the core of the circuit is in off
mode. Once detected, the more precise input voltage
detectors are enabled.
The precise voltage detectors will validate if the applied
charger is in the proper input range bounded by VINLO (on
VSEL pin) and VINOV(on VIN pin) or VINMINOK
depending on VINOK_SEL (see SMBUS Registers Map).
To guarantee a robust detection, debounce timers are added
to the VINLO detection. The VINOV acts as an overvoltage
protection that rejects too high voltage chargers in order to
avoid damage to the application.
When the input voltage is valid (VSEL > VINLO and VIN
< VINOV) or (VINMINOK < VIN < VINOV) depending on
VINOK_SEL bit (register MinSysVoltage), the open drain
VINOK pin is released and pulled high by the external pull
up resistor thus signaling the host that a valid supply is
attached. When becoming invalid the opposite applies.
The SMBus doesn’t has a slave interrupt feature. To
inform the host about an event a sideband signal is to be used.
On the NCP1871 the VINOK pin flags to the host when a
valid charger is attached. Given the non critical timing of the
VINOK signal for this use case, an interrupt is signaled as
a short ‘not VINOK’ pulse. The short period of the pulse
allows distinguishing an interrupt from a charger removal.
An interrupt can only be generated when a valid charger is
attached. The interrupt feature can be enabled and disabled
through the control bus (Bit FAULT_MSK and
STATUS_MSK, Register ChargeOption2). Register
Interrupt inform the system about the nature of interruption.
I2C Signal
Nature
Flagged on
VINOK
Associated
Mask Bit
EOC_INT
RC Dual Edge
Yes
STATUS_MSK
0: Not in End of Charge state
1: End of charge state
PRE_INT
RC Dual Edge
Yes
STATUS_MSK
0: Not in Precharge State
1: Precharge state
LEARNB_INT
RC Dual Edge
Yes
STATUS_MSK
1: Enter/Exit Learn Mode
WDOG_INT
RC Single Edge
Yes
STATUS_MSK
1: Wd timer expired
Description
IPEAK_INT
RC Single Edge
Yes
FAULT_MSK
1: IPKMAX reached.
INOVP_INT
RC Dual Edge
Yes
FAULT_MSK
0: INOVP = 0
1: INOVP = 1
BUCK_OVP_INT
RC Dual Edge
Yes
FAULT_MSK
0: BUCKOV = 0
1: BUCKOV = 1
SYSOV_INT
Write 1 to Clear
Yes
FAULT_MSK
1: SYSOV
HW_RST_INT
RC Single Edge
No
NA
1: HW_RST state and HW_RST=1
1: HW_RST state and BAT_DIS=1
BAT_DIS_INT
RC Single Edge
No
NA
INSHORT_INT
No Clear
Yes
FAULT_MSK
BAT_RMV_INT
RC Single Edge
Yes
STATUS_MSK
1: INSHORT = 1
0: Battery is present
1: Battery is removed
Battery Removal
Event occurs
A battery removal pin TS can be used to monitor battery
presence. This allows the charger to anticipate a potential
voltage drop of the system rail in case of battery removal. If
a battery is suddenly removed, a PRHOTB is immediately
generated, informing the system that the battery is no longer
available for supplement. If this event appears during learn
mode, the buck is immediately forced to VCHG. The
PRHOTB length is 10 ms allowing enough time for the
system to take into account this event, and adapt its power
management accordingly.
200us
VINOK
Valid Adapter Attached
Figure 9. Interrupt Signaling
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21
NCP1871
VSYSMIN Default Value Detection
limited to the capacitor at ACSP. It is therefore thought that
a back to back configuration of a reverse blocking FET
RBFET with an input FET ACFET is not necessarily
required, By using a back to back FET configuration
however, the charger can be isolated from the application
thus providing additional protection against system short
circuits and overvoltages. A back to back FET combination
also allows connecting some additional charging related
circuitry just right after the input FETs while taking
advantage of the overvoltage protection.
When a system short circuit occurs that exceeds the input
and peak to peak current limits, the RBDRV pin will be made
low and the charger will have to be removed to unlatch this
condition. When exceeding the system overvoltage
threshold VSYSOV, SYSOV_INT bit will be triggered as
system over voltage, need to Write 1 to Clear this bit and
release this protection.
For effective isolation the ACFET will have to be added
to create a back to back configuration with the RBFET. Both
mechanisms add additional safety in case the DC to DC
converter does not manage to limit the voltage or current due
to for instance a shorted high side switch or other
malfunctioning.
User can select the VSYSMIN default value thanks to an
external resistor RCELL. The resistance should be put in
series with VSEL pin as follows:
2 /3 Cells
configuration
V IN
3 /4 Cells
configuration
V IN
R2
R2
V SEL
V SEL
RCELL
R1
R1
Figure 10. Resistor Network for CELL Detection
RCELL must be 220 kW if 3/4 cells config selected. R1 is
also fixed to 22 kW, and R2 is used to select VINOK
threshold. The following table illustrates VINOK versus R2.
Learn Mode
The NCP1871 provides a special battery learning cycle
that helps to calibrate the battery fuel gauge. This cycle is
performed while an adapter is attached. Upon the SMBus
LEARN command the DC to DC converter is immediately
forced to VSYSMIN+VSYSOFF, so the application would
be supplied from the battery therefore discharging the latter.
When LEARN is finished (normally by fuel gauge) or
battery is removed, the charge can resume normally.
Constant Power Exit
In case a PRHOTB generation is not sufficient to stop the
voltage drop during a very strong load transient, some AC
adapters are designed to provide more power than their
nominal value. In that case, the charger must disable the
input current limit to allow full power to flow through it.
This mode is enabled thanks to CPEXIT_EN bit in register
ChargeOption2. If this bit is set to 1, the input current limit
will immediately be disabled during PRHOTB generation.
As soon as PRHOTB disappears, the input current limit is
enabled again.
Figure 11. VINOK versus R2 Table
This function can be defeated through I2C (bit
N_CELL_EN, register MinSysVoltage).
Upfront Protection
To avoid the battery voltage supplying the AC adapter
input pin, a reverse blocking element is required. One could
use a Schottky diode but given the high current levels in play,
the dissipation would be excessively high and overall
efficiency degraded. This is resolved by using a reverse
blocking FET (RBFET) function that simulates an ideal
diode. The RBFET is an NMOS type and its gate driven from
RBDRV. An internal charge pump will provide a RBDRV
drive voltage of VIN plus VCORE.
When attaching a charger, the DC to DC converter is not
yet operational and the system is isolated from the charger
by the DC to DC converter high side switch. Therefore, upon
attachment the capacitive loading seen from the battery
charger through the body diode of the RBFET remains
AC Adapter Overvoltage Protection
In case of an overvoltage, the DC to DC converter is
immediately disabled and the RBDRV pin made low, so
a−synchronously with the core logic. The converter and
RBDRV are enabled again when the overvoltage condition
disappears. The converter is definitely disabled by the core
logic and the charger rejected when the overvoltage
condition persists. When connecting an AC adapter,
transient voltages greater than the maximum ratings of the
IC can occur. Appropriate filtering will have to be placed
upfront to stay below these levels.
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22
NCP1871
Hard System Reset
For SMBus the SDA and SCL logic low and high levels
are defined as absolute voltages, where they are relative to
the supply for I2C. Although specification wise this may
lead to conflicting situations, in practice this does not cause
an issue when operating from 3 V and 5 V supply rails. The
interface of the NCP1871 uses absolute levels and is
supplied by the bus lines itself.
For SMBus the clock frequency is within 10 kHz and
100 kHz where I2C allows for 0 Hz while in the widespread
fast mode it can run up to 400 kHz.
The minimum clock frequency for SMBus allows for
implementing a bus timeout mechanism. When the master
keeps the bus clock low the slave will release the data lines
and the transaction is aborted (equivalent to an I2C STOP
command).
Limiting the clock frequency of the interface to the
SMBus standard could lead to conflicts on an I2C bus. The
NCP1871 therefore supports up to 400 kHz. This has no side
effects on the SMBus operation itself. Note that the bus
clocking is independent from the core logic clocking.
For SMBus a slave should always ACK its device address
but is allowed to NACK after any of the data bytes. On I2C
one is allowed to NACK the address. The NCP1871 will
actually never respond with a NACK and therefore always
provide an ACK.
A smart battery charger on a SMBus has an imposed bus
address of 0001001b. Optionally, the NCP1871 includes a
different I2C address (available upon request).
The smart battery charger protocol imposes a word (low
byte, high byte) write/read protocol with one address per 2
bytes. In I2C, the single byte write/read is more common
where each byte of data has its own individual address.
However, most I2C masters can perform an auto increment
to perform a 2 bytes consecutive write/read starting with the
low byte, also see the appendix. The diagram below
summarizes this.
A hard system reset is initiated after the user has pressed
the power button for a long period, usually 8 seconds. The
keyboard controller can then through SMBus program the
system reset bit after which the BATDRV pin is temporarily
made low to GND and the system reset bit cleared. To totally
isolate the battery pack from application, back to back
configuration of BATFET will be needed. Upon HW_RST
bit is set to 1, a RST_TMR timer is launched and BATFETs
are made non conducting when this timer is expired. This
RST_TMR timer ensures the system can turn off correctly
after HW_RST bit is set 1. The Timer also determines the
BATFET OFF duration.
Battery Disconnect
In web tablets and ultrabooks, the battery pack is
embedded and is shipped while being partially charged. To
avoid the battery getting slowly discharged by the
application while being on the shelf, the battery pack is
totally isolated from the application by adding a second
MOS in a back to back configuration. By setting the battery
disconnect bit through SMBus, after a delay of RST_TMR,
the BATDRV pin will be made low to GND when the adapter
is removed and will be kept low as long as the battery power
remains available. To exit this state a valid charger will have
to be inserted which will reconnect the battery pack and reset
the disconnect bit.
Serial Interface (SMBUS)
The device is widely programmable through the SMBus
interface. The SMBus is based on the I2C interface with
some exceptions. These exceptions are documented in the
SMBus specification 2.0 that is available at smbus.org. The
I2C specification is available from the NXP website or
through i2c−bus.org.
The SMBus implementation on the NVDC charger is I2C
friendly allowing it to be used on non SMBus applications.
The most noticeable differences between the two standards
to the NVDC charger are listed below.
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23
NCP1871
Application Information
Typical Application
Negative Protection
circuitry
QNP
R1
Damping
Network
QAC
AC
ADAPTOR
R2
QRB
RIN
QHS
C2
C1
CIN
LX
QLS
RAC
CBOOT
COUT1
COUT2
SYSTEM
LOAD
DF
CAC
RI1
RBDRV
VIN
VDD
R3
D1
RCELL
ACSP
ACSN
HSDRV
SW CBOOT LSDRV
BCSP
VSEL
RBC
RI2
BCSN
BATDRV
VINOK
SDA
HOST
NCP1871
QBAT
SCL
VBAT
RTS
PRHOTB
TS
PMO
VCORE
RPMO
GND
CCORE
RUP
10k
BATTERY
PACK
CBAT
+5V
Figure 12. Additional Circuitry for Negative Protection
Table 5. BILL OF MATERIAL
Reference
Description
Manufacturer / Part Number
Value
4.7 mF / 50 V
CIN
Decoupling input capacitor
RIN
Damping Resistor
2 W / 0.5 W
CAC
Decoupling Switcher capacitor
10 mF / 50 V
CBOOT
Bootstrap capacitor
100 nF / 25 V
CCORE
Decoupling core supply capacitor
2.2 mF / 6.3 V
COUT1, COUT2
Decoupling system capacitor
47 mF / 25 V
CBAT
Decoupling battery capacitor
DF
Clamping Schottky Diode
LX
Switcher Inductor
RAC, RBC
QAC, QRB, QHS, QLS, QBAT
10 mF / 50 V
MBRM120E / ONSEMI
IHLP−2525CZ−01 / VISHAY
Current sense resistor
20 V / 1 A
2.2 mH / 8 A
10 mW / 1 W
Power MOSFET N−channel
NTTFS4C10N / ONSEMI
RTS
Battery Hotplug Current Limit Resistor
RUP
Battery Removal Pull Up resistor
10 mW / 30 V
1 kW / 0.1 W
100 kW / 0.1 W
R1
QRB Reverse protection biasing resistor
3.01 MW / 0.25 W
R2
QRB Reverse protection biasing resistor
1 MW / 0.25 W
R3
RBDRV Reverse protection resistor
4 kW / 0.5 W
Power Monitor Resistor
33 kW / 0.1 W
C1
Reverse protection capacitor
2.2 nF / 50 V
C2
Reverse protection capacitor
0.1 mF / 50 V
RPMO
QNP
D1
Reverse protection NMOS
Schottky Barrier Rectifier
RI1, RI2
Minimum input voltage valid resistor
RCELL
Number of cell selection resistor
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24
2N7002L / ONSEMI
7.5 W / 60 V
MBRA340T3G / ONSEMI
3 A / 40 V
See VSYSMIN Default
Value Detection
NCP1871
Input Damping Network
charger circuitry by blocking the negative voltage and R3
limits the current flowing into the ESD protection circuitry
thus avoiding damage. C1 and C2 ensure the VGS of QRB
and QAC remains 0 V during negative hot plug.
A Damping network is recommended in order to avoid
voltage ringing on the input. On the following example (see
Figure 13) with a 1 mH / 0.1 W cable, the maximum input
voltage is higher than 30 V and can damage the application.
In Figure 14, a damping network 1 mF / 2 W is added so the
input voltage is smoothed to 22−24 V maximum.
Components Selection
Inductor Selection
Inductor electrical selection depends on maximum
current, frequency and duty cycle. The saturation and DC
current are defined by:
I SAT + I CHG ) 0.5
I RIPPLE
The inductor ripple current depends on input voltage
(VIN), duty cycle (D = VOUT /VIN), switching frequency
(FSWCHG) and inductance (LX):
I RIPPLE +
ǒV IN
D
ǒFSWCHG
(1 * D)Ǔ
L XǓ
The maximum inductor ripple current happens for
D = 0.5
IRIPPLE = VIN / (4 x FSWCHG x LX) So maximum current
is given by ISAT = ICHG + 0.5 x VIN / (4 x FSWCHG x LX)
Please note that the NCP1871 switching frequency is
selectable.
Figure 13. Hot Plug Behavior without Damping
Network
Power MOSFETs Selection
NCP1871 is designed to drive N−Chanel MOSFET with
5 V gate drive voltage and an operating voltage up to 24 V.
Due to voltage transient, a 30 V N−MOSFET is preferred.
QAC, QRB, QHS, QLS and QBAT are all N−Chanel MOSFET
and can be identical. It is also recommended to select a very
low RDSON MOSFET (10 mW typically for VGS = 4.5 V)
with a total gate charge around 10 nC typically. NTTFS4C10N
from ON SEMICONDUCTOR is the perfect fit with
NCP1871.
For QBAT, one more thing needs mention: since BATDRV
would be pulled low to GND during shipping mode or hard
system reset action, which means VGS at this time would be
(–VBAT), the NFET needs to be selected with enough VGS
rating especially for 3 or 4 cells application.
Figure 14. Hot Plug Behavior with Damping Network
Input Negative Protection
A negative voltage protection on input is defined by the
negative protection circuitry (see Figure 12). In normal
operation, QNP is off (VGS < 0 V). D1 is conducting and R1,
C1 and C2 have no continuous effect. When adapter voltage
is reversed, QNP VGS is positive causing QNP to turn on. As
a consequence, the source and gate node of QRB is shorted
so QRB is off and the battery side circuitry is protected by the
body diode of QRB. At the same time, D1 is protecting input
PCB Layout Recommendation
Proper layout of the components is recommended in order
to minimize high frequency current path loop and to prevent
high frequency resonant problems and electrical magnetic
field radiation.
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25
NCP1871
GND PLANE
CIN
COUT
CAC
QLS
LX
RIN
AC
ADAPTOR
QAC
VIN
QRB
RBDRV
RAC
ACSP
ACSN HSDRV
RBC
CBOOT
QHS
SYSTEM
LOAD
QBAT
BATTERY
PACK
CBOOT SW LSDRV
BCSP
SENSE
DC POWER
BCSN
BATDRV
NCP1871
VBAT
AC POWER
TS
VCORE
SUPPLY
& DRIVER
CCORE
GND
Figure 15. Typical Layout Recommendation
• CCORE Capacitor must be placed as close as possible to
It is crucial to take the following rules into account.
• The switching loop (AC power track) composed by
CAC, RAC, QHS, QLS, LX, COUT must be as short as
possible and placed on the same layer of PCB. This
track must be isolated from GND plane, only COUT
cold node is connected to the GND plane. This track
must be large enough to reduce impedance of track
(8 A typ).
• The impedance of DC power track composed by QAC,
QRB, RBC and QBAT must be as low as possible and
placed on the same PCB layer as the AC power track.
This track also must be large enough (8 A typ).
•
•
the IC and routed on the same PCB layer as the IC. The
connection to GND (expose pad) should be short and
connected to COUT cold node with a unique track.
Use Kelvin connection for RAC and RBC sensing and
do not route these sense leads through a high di/dt or
dv/dt path.
Supply and driver track must be large enough (1 A
max). LSDRV and HSDRV are switching nodes; track
must be shortened to reduce parasitic inductance.
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26
NCP1871
PACKAGE DIMENSIONS
QFN20 3.5x3.5, 0.5P
CASE 485CP
ISSUE O
PIN ONE
REFERENCE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
B
A
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L
L
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
0.10 C
0.10 C
ÉÉÉ
ÇÇÇ
EXPOSED Cu
TOP VIEW
A
0.05 C
A3
MOLD CMPD
A3
ÇÇÇ
ÉÉÉ
A1
DETAIL B
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.20
0.30
3.50 BSC
2.10
2.30
3.50 BSC
2.10
2.30
0.50 BSC
0.30 REF
0.25
0.45
0.00
0.15
ALTERNATE
CONSTRUCTIONS
0.05 C
DETAIL B
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
RECOMMENDED
MOUNTING FOOTPRINT
0.10 C A B
DETAIL A
D2
3.80
2.36
K
6
20X
0.57
0.10 C A B
20X
11
L
1
E2
2.36
3.80
1
16
e
BOTTOM VIEW
20X
b
0.10 C A B
0.05 C
PACKAGE
OUTLINE
20X
0.50
PITCH
NOTE 3
0.35
DIMENSIONS: MILLIMETERS
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