NCL30185 Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Line Step Dimming and Thermal Foldback The NCL30185 is a controller targeting isolated and non−isolated “smart−dimmable” constant−current LED drivers. Designed to support flyback, buck−boost, and SEPIC topologies, its proprietary current−control algorithm provides near−unity power factor and tightly regulates a constant LED current from the primary side, thus eliminating the need for a secondary−side feedback circuitry or an optocoupler. Housed in the SOIC8, the NCL30185 is specifically intended for very compact space−efficient designs. The device is highly integrated with a minimum number of external components. A robust suite of safety protections is built in to simplify the design. To ensure reliable operation at elevated temperatures, a user configurable current foldback circuit is also provided. In addition, it supports step dimming which allows light output reduction by toggling the main AC switch on and off. Pin−to−pin compatible to the NCL30085, the NCL30185 provides the same benefits with in addition, an increased resolution of the digital current−control algorithm for a 75% reduction in the LED current quantization ripple. www.onsemi.com 8 1 SOIC−8 NB CASE 751 MARKING DIAGRAM 8 L30185x ALYW G 1 L30185x = Specific Device Code x = A, B A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package PIN CONNECTIONS 1 ZCD Features • • • • • • • • • • • VCC Quasi−resonant Peak Current−mode Control Operation DRV VS Valley Lockout Optimizes Efficiency over the Line/Load Range GND COMP Constant Current Control with Primary Side Feedback CS SD Tight LED Constant Current Regulation of ±2% Typical (Top View) Power Factor Correction 3 Step Dimming (70/25/5%) ORDERING INFORMATION Line Feedforward for Enhanced Regulation Accuracy See detailed ordering and shipping information in the package dimensions section on page 27 of this data sheet. Low Start−up Current (10 mA typ.) Wide Vcc Range 300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp Robust Protection Features ♦ OVP on VCC ♦ Thermal Shutdown ♦ Vcc Undervoltage Lockout ♦ Programmable Over Voltage / LED Open Circuit Protection ♦ Brown−out Protection ♦ Cycle−by−cycle Peak Current Limit • Pb−Free, Halide−Free MSL1 Product ♦ Winding Short Circuit Protection Typical Applications ♦ Secondary Diode Short Protection • Integral LED Bulbs and Tubes ♦ Output Short Circuit Protection ♦ Current Sense Short Protection • LED Light Engines ♦ User Programmable NTC Based Thermal Foldback • LED Drivers/Power Supplies © Semiconductor Components Industries, LLC, 2016 February, 2016 − Rev. 0 1 Publication Order Number: NCL30185/D NCL30185 . Aux . . NCL30185 1 8 2 7 3 6 4 5 Figure 1. Typical Application Schematic in a Flyback Converter Aux . . NCL30185 1 8 2 7 3 6 4 5 Figure 2. Typical Application Schematic in a Buck−Boost Converter www.onsemi.com 2 NCL30185 Table 1. PIN FUNCTION DESCRIPTION Pin No Pin Name Function Pin Description 1 ZCD Zero Crossing Detection 2 VS Input Voltage Sensing 3 COMP Filtering Capacitor This pin receives a filtering capacitor for power factor correction. Typical values ranges from 1 − 4.70 mF 4 SD Thermal Foldback and Shutdown Connecting an NTC to this pin allows the user to program thermal current foldback threshold and slope. A Zener diode can also be used to pull−up the pin and stop the controller for adjustable OVP protection. 5 CS Current Sense 6 GND − 7 DRV Driver Output The driver’s output to an external MOSFET 8 VCC IC Supply Pin This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 18 V and turns off when VCC goes below 8.8 V (typical values). After start−up, the operating range is 9.4 V up to 26 V (VCC (OVP ) minimum level). Connected to the auxiliary winding, this pin detects the core reset event. This pin observes the input voltage rail and protects the LED driver in case of too low mains conditions (brown−out). This pin also observes the input voltage rail for: − Power Factor Correction − Valley lockout − Step dimming This pin monitors the primary peak current. Controller ground pin. www.onsemi.com 3 NCL30185 Internal Circuit Architecture Enable Over Voltage Protection (Auto−recovery or Latched) V DD STOP Aux_SCP V REF OFF Over Temp. Protection VCC UVLO Fault Management VCC Management Latch (Auto−recovery or Latched) SD Thermal Foldback Internal Thermal Shutdown V TF VCC_max VCC Over Voltage Protection WOD_SCP BO_NOK DRV FF_mode V VS V REF VCC FF_mode ZCD Zero Crossing Detection Logic (ZCD Blanking, Time−Out, ...) Clamp Circuit Valley Selection Frequency Foldback Aux. Winding Short Circuit Prot. Aux_SCP Q CS_ok Q R Line feed−forward CS DRV S VREFX V VS VVS STOP VREFX Power Factor and Constant−Current Control Leading Edge Blanking CS_reset Ipkmax Maximum on time STOP t on,max Ipkmax Max. Peak Current Limit COMP BO_NOK UVLO VVS CS_ok CS Short Protection STEP_DIM t on,max Winding and Output diode Short Circuit Protection VREFX Dimming control WOD_SCP VS Brown−Out VREF GND VTF Figure 3. Internal Circuit Architecture www.onsemi.com 4 NCL30185 Table 2. MAXIMUM RATINGS TABLE Symbol Rating Value Unit VCC(MAX) ICC(MAX) Maximum Power Supply voltage, VCC pin, continuous voltage Maximum current for VCC pin −0.3 to 30 Internally limited V mA VDRV(MAX) IDRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage Maximum current for DRV pin −0.3, VDRV (Note 1) −300, +500 V mA VMAX IMAX Maximum voltage on low power pins (except DRV and VCC pins) Current range for low power pins (except DRV and VCC pins) −0.3, 5.5 (Notes 2 and 5) −2, +5 V mA RθJ−A Thermal Resistance Junction−to−Air 180 °C/W TJ(MAX) Maximum Junction Temperature 150 °C Operating Temperature Range −40 to +125 °C Storage Temperature Range −60 to +150 °C ESD Capability, HBM model (Note 3) 3.5 kV ESD Capability, MM model (Note 3) 250 V ESD Capability, CDM model (Note 3) 2 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise. 2. These levels are low enough not to exceed the maximum ratings of the internal ESD 5.5−V Zener diode. More positive and negative voltages can be applied if the pin current stays within the −2−mA / 5−mA range. 3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E, Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E. 4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA 5. Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range. Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V) Test Condition Symbol Min Typ Max VCC rising VCC rising VCC falling VCC(on) VCC(off) VCC(HYS) VCC(reset) 16.0 8.2 8 4 18.0 8.8 − 5 20.0 9.4 − 6 VCC Over Voltage Protection Threshold VCC(OVP) 25.5 26.8 28.5 V VCC(off) noise filter VCC(reset) noise filter tVCC(off) tVCC(reset) − − 5 20 − − ms ICC(start) − 13 30 mA 58 75 mA Description Unit STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Operating Voltage Hysteresis VCC(on) – VCC(off) Internal logic reset V Startup current Startup current in fault mode Supply Current Device Disabled/Fault Device Enabled/No output load on pin 7 Device Switching (FSW = 65 kHz) ICC(sFault) mA VCC > VCC(off) Fsw = 65 kHz CDRV = 470 pF, Fsw = 65 kHz ICC1 ICC2 ICC3 0.8 – − 1.0 2.5 3.0 1.2 4.0 4.5 Maximum Internal current limit VILIM 0.95 1.00 1.05 V Leading Edge Blanking Duration for VILIM tLEB 240 300 360 ns IFF 35 40 45 mA CURRENT SENSE Line feed−forward current DRV high, VVS = 2 V 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. www.onsemi.com 5 NCL30185 Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V) Description Test Condition Symbol Min Typ Max Unit tILIM − 100 150 ns CURRENT SENSE Propagation delay from current detection to gate off−state Maximum on−time ton(MAX) 26 36 46 ms Threshold for immediate fault protection activation VCS(stop) 1.35 1.50 1.65 V Leading Edge Blanking Duration for VCS(stop) tBCS − 150 − ns Current source for CS to GND short detection ICS(short) 400 500 600 mA VCS(low) 30 65 100 mV Drive Resistance DRV Sink DRV Source RSNK RSRC − − 13 30 − − Drive current capability DRV Sink (Note 6) DRV Source (Note 6) ISNK ISRC − − 500 300 − − Current sense threshold for CS to GND short detection VCS rising GATE DRIVE W mA Rise Time (10% to 90%) CDRV = 470 pF tr – 40 − ns Fall Time (90% to 10%) CDRV = 470 pF tf – 30 − ns DRV Low Voltage VCC = VCC(off)+0.2 V CDRV = 470 pF, RDRV=33 kW VDRV(low) 8 – − V DRV High Voltage VCC = VCC(MAX) CDRV = 470 pF, RDRV=33 kW VDRV(high) 10 12 14 V Upper ZCD threshold voltage VZCD rising VZCD(rising) − 90 150 mV Lower ZCD threshold voltage VZCD falling VZCD(falling) 35 55 − mV VZCD(HYS) 15 − − mV ZERO VOLTAGE DETECTION CIRCUIT ZCD hysteresis Propagation Delay from valley detection to DRV high VZCD falling TDEM − 100 300 ns Blanking delay after on−time VREFX > 30% VREF TZCD(blank1) 1.12 1.50 1.88 ms Blanking Delay at light load VREFX < 25% VREF TZCD(blank2) 0.56 0.75 0.94 ms TTIMO 5.0 6.5 8.0 ms RZCD(PD) − 200 − kW Reference Voltage at TJ = 25°C VREF 245 250 255 mV Reference Voltage TJ = 25°C to 100°C VREF 242.5 250.0 257.5 mV Reference Voltage TJ = −40°C to 125°C VREF 240 250 260 mV VCS(low) 20 50 100 mV Vratio − 4 − − GEA 40 50 200 60 mS Timeout after last DEMAG transition Pulling−down resistor VZCD = VZCD(falling) CONSTANT CURRENT AND POWER FACTOR CONTROL Current sense lower threshold VCS falling Vcontrol to current setpoint division ratio Error amplifier gain VREFX=VREF (no dimming) VREFX=25%* VREF 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. www.onsemi.com 6 NCL30185 Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V) Description Test Condition Symbol Min Typ Max Unit VREFX=VREF (no dimming) VREFX=25%* VREF IEA ±60 ±240 mA No dimming, COMP pin grounded IEA_STUP 140 mA CONSTANT CURRENT AND POWER FACTOR CONTROL Error amplifier current capability COMP Pin Start−up Current Source LINE FEED FORWARD KLFF 18 20 22 mS DRV high, VVS = 2 V IFF 35 40 45 mA VVS > 5 V Ioffset(MAX) 80 100 120 mA Threshold for high− line range (HL) detection VVS rising VHL 2.28 2.40 2.52 V Threshold for low−line range (LL) detection VVS falling VLL 2.18 2.30 2.42 V Blanking time for line range detection tHL(blank) 15 25 35 ms Valley Lockout First step valley in High−Line. Second step valley in High−Line. Third step valley in High−Line. First step valley in Low−Line. Second step valley in Low−Line. Third step valley in Low−Line. VHL100% VHL70% VHL25% VLL100% VLL70% VLL25% VVS to ICS(offset) conversion ratio Line feed−forward current on CS pin Offset current maximum value VALLEY LOCKOUT SECTION 2 3 6 1 2 5 FREQUENCY FOLDBACK Additional dead time VREFX = 25%*VREF tFF1LL 1.4 2.0 2.6 ms Additional dead time VREFX = 5%*VREF tFF2HL − 40 − ms FSW = 65 kHz TSHDN 130 150 170 _C Thermal Shutdown Hysteresis TSHDN(HYS) − 50 – _C Threshold voltage for output short circuit or aux. winding short circuit detection VZCD(short) 0.8 1.0 1.2 V tOVLD 70 90 110 ms Auto−recovery timer duration trecovery 3 4 5 s SD pin Clamp series resistor RSD(clamp) FAULT PROTECTION Thermal Shutdown (Note 6) Short circuit detection Timer Clamped voltage VZCD < VZCD(short) 1.6 kW SD pin open VSD(clamp) 1.13 1.35 1.57 V VSD rising VOVP 2.35 2.50 2.65 V Delay before OVP or OTP confirmation (OVP and OTP) TSD(delay) 22.5 30.0 37.5 ms Reference current for direct connection of an NTC (Note 8) IOTP(REF) 80 85 90 mA SD pin detection level for OVP Fault detection level for OTP (Note 7) VSD falling VOTP(off) 0.47 0.50 0.53 V SD pin level for operation recovery after an OTP detection VSD rising VOTP(on) 0.66 0.70 0.74 V 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. www.onsemi.com 7 NCL30185 Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V) Description Test Condition Symbol Min OTP blanking time when circuit starts operating (Note 8) tOTP(start) 250 SD pin voltage at which thermal fold−back starts (VREF is decreased) VTF(start) 0.94 SD pin voltage at which thermal fold−back stops (VREF is clamped to VREF50) VTF(stop) Typ Max Unit 370 ms 1.00 1.06 V 0.64 0.69 0.74 V FAULT PROTECTION VTF(start) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C RTF(start) 10.8 11.7 12.6 kW VTF(stop) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C RTF(stop) 7.4 8.1 8.8 kW VOTP(off) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C ROTP(off) 5.4 5.9 6.4 kW VOTP(on) over IOTP(REF) ratio (Note 7) TJ = +25°C to +125°C ROTP(on) 7.5 8.1 8.7 kW VREFX @ VSD = 600 mV (percent of VREF) SD pin falling, no OTP detection VREF(50) 40 50 60 % Brown−Out ON level (IC start pulsing) VS rising VBO(on) 0.95 1.00 1.05 V Brown−Out OFF level (IC shuts down) VS falling VBO(off) 0.85 0.90 0.95 V BROWN−OUT ms BO comparators delay tBO(delay) 30 Brown−Out blanking time tBO(blank) 15 25 35 ms VS pin Pulling−down Current VS = VBO(on) IBO(bias) 50 250 450 nA Step Dimming Reset Time VS < VBO(off) tstep−reset 2.4 3.2 4.0 s 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. www.onsemi.com 8 NCL30185 TYPICAL CHARACTERISTICS 20.0 9.4 9.3 19.5 9.2 9.1 18.5 VCC(off) (V) VCC(on) (V) 19.0 18.0 17.5 17.0 −25 0 25 50 75 100 125 150 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 4. VCC Start−up Threshold vs. Temperature Figure 5. VCC Minimum Operating Voltage vs. Temperature 11.5 6.0 11.0 5.8 5.6 VCC(reset) (V) 5.4 10.0 9.5 9.0 5.2 5.0 4.8 4.6 8.5 4.4 8.0 7.5 −50 −25 TJ, JUNCTION TEMPERATURE (°C) 10.5 VCC(hys) (V) 8.7 8.6 8.5 8.4 8.3 8.2 −50 16.5 16.0 −50 9.0 8.9 8.8 −25 0 25 50 75 100 125 4.2 4.0 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Hysteresis (VCC(on) − VCC(off)) vs. Temperature Figure 7. VCC(reset) vs. Temperature www.onsemi.com 9 NCL30185 TYPICAL CHARACTERISTICS 40 28.0 27.8 35 30 27.2 27.0 ICC(start) (mA) VCC(ovp) (V) 27.6 27.4 26.8 26.6 26.4 25 20 15 10 26.2 26.0 25.8 25.6 −50 5 −25 0 25 50 75 100 125 0 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 8. VCC Over Voltage Protection Threshold vs. Temperature Figure 9. Start−up Current vs. Temperature 2.0 150 1.8 125 ICC1 (mA) ICC(sfault) (mA) 1.6 100 75 50 1.4 1.2 1.0 0.8 25 0.6 −25 0 25 50 75 100 125 0.4 −50 150 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 10. Start−up Current in Fault Mode vs. Temperature Figure 11. ICC1 vs. Temperature 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 −50 125 150 5.0 4.5 4.0 ICC3 (mA) ICC2 (mA) 0 −50 3.5 3.0 2.5 2.0 1.5 −25 0 25 50 75 100 125 150 1.0 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 12. ICC2 vs. Temperature Figure 13. ICC3 vs. Temperature www.onsemi.com 10 125 150 NCL30185 1.05 400 1.04 380 360 1.02 340 1.01 320 TLEB (ns) 1.03 1.00 0.99 280 260 0.97 240 0.96 0.95 −50 220 −25 0 25 50 75 100 125 200 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 14. Maximum Internal Current Limit vs. Temperature Figure 15. Leading Edge Blanking vs. Temperature 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 −50 50 48 46 44 42 40 38 36 34 −25 0 25 50 75 100 125 32 30 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 16. Current Limit Propagation Delay vs. Temperature Figure 17. Maximum On−time vs. Temperature 1.60 220 210 1.58 200 190 1.56 1.54 1.52 TBCS (ns) VCS(stop) (V) 300 0.98 TON(max) (ms) TILIM (ns) VILIM (V) TYPICAL CHARACTERISTICS 1.50 1.48 1.46 1.44 1.42 1.40 1.38 −50 −25 0 25 50 75 100 125 150 180 170 160 150 140 130 120 110 100 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 18. VCS(stop) vs. Temperature Figure 19. Leading Edge Blanking Duration for VCS(stop) vs. Temperature www.onsemi.com 11 NCL30185 TYPICAL CHARACTERISTICS 600 100 580 90 560 80 VCS(low) (mV) ICS(short) (mA) 540 520 500 480 460 −25 0 25 50 75 100 125 20 −50 150 25 50 75 100 125 150 Figure 20. ICS(short) vs. Temperature Figure 21. VCS(low), VCS Rising vs. Temperature 14 12 RSRC (W) RSNK (W) 0 TJ, JUNCTION TEMPERATURE (°C) 16 10 8 6 4 −25 0 25 50 75 100 125 150 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 22. Sink Gate Drive Resistance vs. Temperature Figure 23. Source Gate Drive Resistance vs. Temperature 50 45 45 40 40 35 35 30 30 tF (ns) 50 25 25 20 20 15 15 10 10 5 0 −50 −25 TJ, JUNCTION TEMPERATURE (°C) 18 tr (ns) 50 30 20 2 0 −50 60 40 440 420 400 −50 70 −25 0 25 50 75 100 125 150 5 0 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 24. Gate Drive Rise Time vs. Temperature Figure 25. Gate Drive Fall Time (CDRV = 470 pF) vs. Temperature www.onsemi.com 12 125 150 NCL30185 TYPICAL CHARACTERISTICS 9.8 15.0 9.6 14.5 14.0 VDRV(high) (V) VDRV(low) (V) 9.4 9.2 9.0 8.8 12.0 11.0 8.4 8.2 −50 −25 0 25 50 75 100 125 10.5 10.0 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 26. DRV Low Voltage vs. Temperature Figure 27. DRV High Voltage vs. Temperature 150 80 140 130 75 120 110 65 VZCD(falling) (mV) 70 100 90 80 70 60 55 50 45 60 50 40 40 30 −50 35 30 −50 −25 0 25 50 75 100 125 150 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 28. Upper ZCD Threshold Voltage vs. Temperature Figure 29. Lower ZCD Threshold vs. Temperature 50 2.0 45 1.9 40 1.8 35 1.7 30 25 20 15 10 5 0 −50 −25 TJ, JUNCTION TEMPERATURE (°C) tZCD(blank1) (ms) VZCD(rising) (mV) 13.0 12.5 11.5 8.6 VZCD(HYS) (mV) 13.5 1.6 1.5 1.4 1.3 1.2 −25 0 25 50 75 100 125 150 1.1 1.0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 30. ZCD Hysteresis vs. Temperature Figure 31. ZCD Blanking Delay vs. Temperature www.onsemi.com 13 NCL30185 TYPICAL CHARACTERISTICS 7.8 256 255 254 253 7.6 7.4 252 VREF (mV) TTIMO (ms) 7.2 7.0 6.8 6.6 6.4 246 −25 0 25 50 75 100 125 245 244 −50 150 25 50 75 100 125 150 Figure 32. ZCD Time−out vs. Temperature Figure 33. Reference Voltage vs. Temperature 110 60 58 90 56 54 70 GEA (mS) VCS(low) (mV) 0 TJ, JUNCTION TEMPERATURE (°C) 100 60 50 52 50 48 40 30 46 20 10 −50 44 −25 0 25 50 75 100 125 42 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 34. Current Sense Lower Threshold (VCS Falling) vs. Temperature Figure 35. Error Amplifier Trans−conductance Gain vs. Temperature 44 21.5 43 21.0 42 20.5 41 IFF (mA) 22.0 20.0 40 19.5 39 19.0 38 18.5 37 18.0 −50 −25 TJ, JUNCTION TEMPERATURE (°C) 80 KLFF (mS) 249 248 247 6.2 6.0 5.8 −50 251 250 −25 0 25 50 75 100 125 150 36 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 36. Feedforward VVS to ICS(offset) Conversion Ratio vs. Temperature Figure 37. Line Feedforward Current on CS Pin (@ VVS = 2 V) vs. Temperature www.onsemi.com 14 NCL30185 TYPICAL CHARACTERISTICS 120 2.55 115 2.50 2.45 105 VHL (V) Ioffset(MAX) (mA) 110 100 95 2.40 2.35 90 2.30 85 80 −50 −25 0 25 50 75 100 125 2.25 −50 150 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 38. Ioffset(MAX) vs. Temperature Figure 39. Threshold for High−line Range Detection vs. Temperature 2.60 40 2.55 38 36 THL(blank) (ms) 2.50 2.45 VLL (V) −25 2.40 2.35 34 32 30 28 26 2.30 24 2.25 −25 0 25 50 75 100 125 22 20 −50 150 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 40. Threshold for Low−line Range Detection vs. Temperature Figure 41. Blanking Time for Low−line Range Detection vs. Temperature 1.20 115 1.15 110 1.10 105 1.05 100 1.00 0.95 95 90 0.90 85 0.85 80 0.80 −50 −25 TJ, JUNCTION TEMPERATURE (°C) tOVLD (ms) VZCD(short) (V) 2.20 −50 −25 0 25 50 75 100 125 150 75 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 42. Threshold Voltage for Output Short Circuit Detection vs. Temperature Figure 43. Short Circuit Detection Timer vs. Temperature www.onsemi.com 15 NCL30185 TYPICAL CHARACTERISTICS 5.00 2.20 2.10 4.75 RSD(clamp) (kW) Trecovery (s) 4.50 4.25 4.00 3.75 3.50 3.00 −50 1.50 1.40 1.20 1.10 1.00 −50 −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 44. Auto−recovery Timer Duration vs. Temperature Figure 45. SD Pin Clamp Series Resistor vs. Temperature 1.60 2.58 1.55 2.56 1.50 2.54 1.45 2.52 1.40 VOVP (V) VSD(clamp) (V) 1.70 1.60 1.30 3.25 1.35 1.30 2.50 2.48 2.46 1.25 1.20 2.44 1.15 1.10 −50 2.42 −25 0 25 50 75 100 125 2.40 −50 150 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 46. SD Pin Clamp Voltage vs. Temperature Figure 47. SD Pin OVP Threshold Voltage vs. Temperature 91 90 36 89 88 IOTP(REF) (mA) 34 32 30 28 26 24 22 −50 −25 TJ, JUNCTION TEMPERATURE (°C) 38 TSD(delay) (ms) 2.00 1.90 1.80 −25 0 25 50 75 100 125 150 87 86 85 84 83 82 81 80 79 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 48. TSD(delay) vs. Temperature Figure 49. IOTP(REF) vs. Temperature www.onsemi.com 16 NCL30185 12.5 12.4 12.3 12.2 12.1 12.0 11.9 11.8 11.7 11.6 11.5 11.4 11.3 11.2 11.1 11.0 −50 8.8 8.7 RTF(stop) (kW) RTF(start) (kW) TYPICAL CHARACTERISTICS −25 0 25 50 75 100 125 8.2 8.1 8.0 7.9 7.8 7.7 7.6 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 50. RTF(start) vs. Temperature Figure 51. RTF(stop) vs. Temperature 8.8 8.7 8.6 6.4 6.3 6.2 ROTP(on) (kW) 6.1 ROTP(off) (kW) 8.6 8.5 8.4 8.3 6.0 5.9 5.8 5.7 8.5 8.4 8.3 8.2 8.1 8.0 7.9 5.6 −25 0 25 50 75 100 125 7.8 7.7 7.6 −50 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 52. ROTP(off) vs. Temperature Figure 53. ROTP(on) vs. Temperature 55 1.05 54 1.04 53 1.03 52 1.02 VBO(on) (V) VREF(50) (%) 5.5 5.4 −50 51 50 49 1.01 1.00 0.99 48 0.98 47 0.97 46 45 −50 0.96 0.95 −50 −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 54. Ratio VREF(50) over VREF vs. Temperature Figure 55. Brown−out ON Level vs. Temperature www.onsemi.com 17 NCL30185 TYPICAL CHARACTERISTICS 0.95 0.94 0.93 tBO(blank) (ms) 0.91 0.90 0.89 0.88 0.87 0.86 0.85 −50 −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 56. Brown−out OFF Level vs. Temperature Figure 57. Brown−out Blanking Time vs. Temperature 500 450 400 350 IBO(bias) (nA) VBO(off) (V) 0.92 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 −50 300 250 200 150 100 50 0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 58. VS Pin Pulling−down Current vs. Temperature www.onsemi.com 18 150 NCL30185 Application Information The NCL30185 is a driver for power−factor corrected flyback and non−isolated buck−boost and SEPIC converters. It implements a current−mode, quasi−resonant architecture including valley lockout and frequency fold−back capabilities for maintaining high−efficiency performance over a wide load range. A proprietary circuitry ensures both accurate regulation of the output current (without the need for a secondary−side feedback) and near−unity power factor correction. The circuit contains a suite of powerful protections to ensure a robust LED driver design without the need for extra external components or overdesign. • Quasi−Resonance Current−Mode Operation: implementing quasi−resonance operation in peak current−mode control, the NCL30185 optimizes the efficiency by turning on the MOSFET when its drain−source voltage is minimal (valley). In light−load conditions, the circuit changes valleys to reduce the switching losses. For stable operation, the valley at which the MOSFET switches on remains locked until the input voltage or the output current set−point significantly changes. • Primary−Side Constant−Current Control with Power Factor Correction: a proprietary circuitry allows the LED driver to achieve both near−unity power factor correction and accurate regulation of the output current without requiring any secondary−side feedback (no optocoupler needed). A power factor as high as 0.99 and an output current deviation below ±2% are typically obtained. • Step dimming: The step dimming function decreases the output current from 100% to 5% of its nominal value in 3 discrete steps. Whenever a brown−out is detected, the output current is decreased by reducing the reference voltage VREF. The step−dimming function is reset if the VS pin remains below the lower brown−out threshold (VBO(off)) for more than 3 s typically. • Main protection features: ♦ Over Temperature Thermal Fold−back / Shutdown/ Over Voltage Protection: the NCL30185 features a gradual current foldback to protect the driver from excessive temperature down to 50% of the programmed current. This represents a power reduction of the LED by more than 50%. If the temperature continues to rise after this point to a ♦ ♦ ♦ ♦ ♦ second level, the controller stops operating. This mode would only be expected to be reached if there is a severe fault. The first and second temperature thresholds depend on the value of the NTC connected to the SD pin. Note, the SD pin can also be used to shutdown the device by pulling this pin below the VOTP(off) min level. A Zener diode can also be used to pull−up the pin and stop the controller for adjustable OVP protection. Both protections are latching−off (A version) or auto−recovery (the circuit can recover operation after 4−s delay has elapsed − B version). Cycle−by−cycle peak current limit: when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is immediately turned off for that switch cycle. Winding or Output Diode Short−Circuit Protection: an additional comparator senses the CS signal and stops the controller if it exceeds 150% x VILIM for 4 consecutive cycles. This feature can protect the converter if a winding is shorted or if the output diode is shorted or simply if the transformer saturates. This protection is latching−off (A version) or auto−recovery (B version). Output Short−circuit protection: if the ZCD pin voltage remains low for a 90−ms time interval, the controller detects that the output or the ZCD pin is grounded and hence, stops operation. This protection is latching−off (A version) or auto−recovery (B version). Open LED protection: if the VCC pin voltage exceeds the OVP threshold, the controller shuts down and waits 4 seconds before restarting switching operation. Floating or Short Pin Detection: the circuit can detect most of these situations which helps pass safety tests. Power Factor and Constant Current Control The NCL30185 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, VS and CS pin voltages (signals ZCD, VVS and VCS of Figure 59). This circuitry generates the current setpoint (VCONTROL/4) and compares it to the current sense signal (VCS) to dictate the MOSFET turning off event when VCS exceeds VCONTROL/4. www.onsemi.com 19 NCL30185 ZCD VCS STOP VREFX VVS PWM Latch reset Power Factor and Constant−Current Control COMP C1 Figure 59. Power Factor and Constant−Current Control • The COMP pin is grounded when the circuit is off. The As illustrated in Figure 59, the VS pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half−line period, it is equal to the output current reference (VREFX). This averaging process is made by an internal Operational Trans−conductance Amplifier (OTA) and the capacitor connected to the COMP pin (C1 of Figure 59). Typical COMP capacitance is 1 mF and should not be less than 470 nF to ensure stability. The COMP ripple does not affect the power factor performance as the circuit digitally eliminates it when generating the current setpoint. If the VS pin properly conveys the sinusoidal shape, power factor will be close to unity and the Total Harmonic Distortion (THD) will be low. In any case, the output current will be well regulated following the equation below: I out + V REFX 2N PSR sense • (eq. 1) Where: • NPS is the secondary to primary transformer turns NPS = NS/NP • Rsense is the current sense resistor (see Figure 1). • VREFX is the output current internal reference. VREFX = VREF (250 mV typically) at full load. • The output current reference (VREFX) is 250 mV typically (VREF). In the event that step dimming is engaged, VREFX takes a lower value based on the step−dimming level (see “step dimming” section) or if the temperature is high enough to activate the thermal fold−back (see “protections” section). If a major fault is detected, the circuit enters the latched−off or auto−recovery mode and the COMP pin is grounded (except in an UVLO condition). This ensures a clean start−up when the circuit resumes operation. • Start−up Sequence Generally an LED lamp is expected to emit light in < 1 sec and typically within 300 ms. The start−up phase consists of the time to charge the VCC capacitor, initiate startup and begin switching and the time to charge the output capacitor until sufficient current flows into the LED string. To speed−up this phase, the following defines the start−up sequence: average COMP voltage needs to exceed the VS pin peak value to have the LED current properly regulated (whatever the current target is). To speed−up the COMP capacitance charge and shorten the start−up phase, an internal 80−mA current source adds to the OTA sourced current (60 mA max typically) to charge up the COMP capacitance. The 80−mA current source remains on until the OTA starts to sink current as a result of the COMP pin voltage sufficient rise. At that moment, the COMP pin being near its steady−state value, it is only driven by the OTA. Whatever the step−dimming state is, the output current reference is set maximum (VREFX = VREF) until the ZCD pin voltage reaches the 1−V VZCD(short) threshold. This prevents the circuit from detecting an output short (AUX_SCP protection trips if the ZCD pin voltage does not exceed 1−V VZCD(short) threshold within a 90−ms delay) just because dimming would make the output voltage charge up slowly. If the system cannot start−up in one VCC cycle, the AUX_SCP 90−ms blanking time is not reset and VREFX remains maximum for all the necessary VCC cycles until the ZCD pin voltage reaches the 1−V VZCD(short) threshold. If VCC drops below the VCC(off) threshold because the circuit fails to start−up properly on the first attempt, a new try takes place as soon as VCC is recharged to VCC(on). The COMP voltage is not reset at that moment. Instead, the new attempt starts with the COMP level obtained at the end of the previous operating phase. If the load is shorted, the circuit will operate in hiccup mode with VCC oscillating between VCC(off) and VCC(on) until the AUX_SCP protection trips (AUX_SCP is triggered if the ZCD pin voltage does not exceed 1 V within a 90−ms operation period of time thus indicating a short to ground of the ZCD pin or an excessive load preventing the output voltage from rising). The NCL30185A latches off in this case. With the B version, the AUX_SCP protection forces the 4−s auto−recovery delay to reduce the operation duty−ratio. Figure 60 illustrates a start−up sequence with the output shorted to ground, in this second case. www.onsemi.com 20 NCL30185 VCC(on) VCC VCC(off) (‧‧‧ ) (‧‧‧ ) time AUX_SCPtrips as t 1 + t2 + t3 = tOVLD (tOVLD ^90 ms) DRV t1 t3 t1 t2 t3 time t2 trecovery (^4 s ) trecovery (^4 s ) Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery version) Step Dimming is selected by VREFX. This avoids long startup time while dimming at low output current value. The step dimming function decreases the output current from 100% to 5% of its nominal value in 3 discrete steps. The table below shows the different steps value and the corresponding reference voltage value. Each time a brown−out is detected, the output current is decreased by decreasing the reference voltage VREF. A counter is incremented by the BO_NOK (brown−out not OK) signal and selects one of the four corresponding reference thresholds: VREF, VREF70, VREF25, VREF5. After counting up to 4, the counter is reset. VCC C1 C2 Table 4. DIMMING STEPS Dimming Step Iout ON 100% 1 70% 2 25% 3 5% Figure 61. Split VCC Supply The step−dimming function is reset if the VS pin is maintained below the VBO(off) brown−out threshold for the Tstep_reset time. Tstep_reset is 3 s typically. In other words, any brown−out event that is longer than Tstep_reset, leads the controller to re−start at 100% current setting. Note: The step dimming state is memorized until VCC crosses VCC(reset) or VVS is below VBO(off) for 3 s (typical). The circuit consumption is optimized (in particular, it equals ICC(fault) when VCC is lower than VCC(off)) so that the VCC voltage does not drop too fast for the step dimming brown−out event. The power supply designer should use a split VCC circuit as shown in Figure 61 where a small capacitor C1 is used for a fast start−up while a larger C2 capacitance provides the necessary storage capability for step dimming. During step dimming, at startup, the controller generates the first DRV pulses after 1 time−out pulse even if a higher valley number Zero Crossing Detection Block The ZCD pin detects when the drain−source voltage of the power MOSFET reaches a valley by crossing below the 55−mV internal threshold. At startup or in case of extremely damped free oscillations, the ZCD comparator may not be able to detect the valleys. To avoid such a situation, the NCL30185 features a time−out circuit that generates pulses if the voltage on ZCD pin stays below the 55−mV threshold for 6.5 ms. The time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case the free oscillations are too damped. www.onsemi.com 21 NCL30185 t ZCD(blank1) t ZCD(blank) FF_mode t ZCD(blank2) ZCD VZCD(TH) + − Clock Time−Out V ZCD(short) + + − − S Q Aux_SCP Q 90−ms Timer R 4−s Timer (auto−recovery version) Vcc<Vcc(reset) (latching−off version) Figure 62. Zero Current Detection Block • After the appropriate number of “clock” pulses in If the ZCD pin or the auxiliary winding happen to be shorted, the time−out function would normally make the controller keep switching and hence lead to improper LED current value. The “AUX_SCP” protection prevents such a stressful operation: a secondary timer starts counting that is only reset when the ZCD voltage exceeds the VZCD(short) threshold (1 V typically). If this timer reaches 90 ms (no ZCD voltage pulse having exceeded VZCD(short) for this time period), the controller detects a fault and stops operation for 4 seconds (B version) or latches off (A version). The “clock” shown in Figure 62 is used by the “valley selection frequency foldback” circuitry of the block diagram (Figure 3), to generate the next DRV pulse (if no fault prevents it): • Immediately when the clock occurs in QR mode (heavy load) thermal foldback or step−dimming mode (see Table 5) For an optimal operation, the maximum ZCD level should be maintained below 5 V to stay safely below the built in clamping voltage of the pin. Line Range Detection and Valley Lockout As sketched in Figure 63, this circuit detects the low−line range if the VS pin remains below the VLL threshold (2.3 V typical) for more than the 25−ms blanking time. High−line is detected as soon as the VS pin voltage exceeds VHL (2.4 V typical). These levels roughly correspond to 184−V rms and 192−V rms line voltages if the external resistors divider applied to the VS pin is designed to provide a 1−V peak value at 80 V rms. Figure 63. Line Range Detection www.onsemi.com 22 NCL30185 Quasi−square wave resonant systems have a wide switching frequency excursion. The switching frequency increases when the output load decreases or when the input voltage increases. The switching frequency of such systems must be limited. Table 5. VALLEY SELECTION Load Low Line High Line 100% Valley 1 (QR) Valley 2 70% Valley 2 Valley 3 25% Valley 5 Valley 6 5% Frequency foldback Frequency foldback A decimal counter counts the valley detected by the ZCD logic block. In the low−line range, conduction losses are generally dominant. Hence, only a short dead−time is necessary to reach the MOSFET valley. In high−line conditions, switching losses generally are the most critical. It is thus efficient to skip a valley to lower the switching frequency. Hence, when the current is not dimmed, the NCL30185 optimizes the efficiency over the line range by turning on the MOSFET at the first valley in low−line conditions and at the second valley in the high−line case. This is illustrated in Figure 64 that sketches the MOSFET Drain−source voltage in both cases. In dimming cases, more valleys can be skipped. Table 5 summarizes the valley selection as a function of the output current. Figure 64. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line (right) Frequency Foldback (FF) Line Feedforward The valley lockout function can make the circuit skip operation until the 5th valley (6th valley) is detected in low−line case (high−line case) as obtained at 25% of the nominal load. At the lowest step (5% of the nominal load), the switching frequency is decreased by further adding dead−time after the 5th valley (low line) or the 6th valley (high line) is detected. This extra dead−time is typically 40 ms. As illustrated by Figure 65, the input voltage is sensed by the VS pin and converted into a current. By adding an external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the input voltage is added to the CS signal for the MOSFET on−time to compensate for the Ipeak increase due to the propagation delay. Bulk rail vDD VS I CS(offset) CS RCS Rsense Q_drv Figure 65. Line Feed−Forward Schematic In Figure 65, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise. www.onsemi.com 23 NCL30185 Protections The circuit incorporates a large variety of protections to make the LED driver very rugged. Among them, we can list: abnormally steep slope of the current, internal propagation delays and the MOSFET turn−off time will make possible the current rise up to 50% or more of the nominal maximum value set by VILIM. As illustrated in Figure 66, the circuit uses this current overshoot to detect a winding short circuit. The leading edge blanking (LEB) time for short circuit protection (LEB2) is significantly faster than the LEB time for cycle−by−cycle protection (LEB1). Practically, if four consecutive switching periods lead the CS pin voltage to exceed (VCS(stop)=150% *VILIM), the controller enters auto−recovery mode in version B (4−s operation interruption between active bursts) and latches off in version A. Similarly, this function can also protect the power supply if the output diode is shorted or if the transformer simply saturates. Output Short Circuit Situation An overload fault is detected if the ZCD pin voltage remains below VZCD(short) for 90 ms. In such a situation, the circuit stops generating pulses until the 4−s delay auto−recovery time has elapsed (B version) or latches off (A version). Winding or Output Diode Short Circuit Protection If a transformer winding happens to be shorted, the primary inductance will collapse leading the current to ramp up in a very abrupt manner. The VILIM comparator (current limitation threshold) will trip to open the MOSFET and eventually stop the current rise. However, because of the S DRV Q Vdd aux UVLO Q TSD CS LEB1 + V control / 4 UVLO PWMreset VCC Vcc management BONOK R − latch 4−s timer + VCCreset (grand reset) STOP Ipkmax − V ILIMIT AUX_SCP SD Pin OVP (OVP2) LEB2 + − WOD_SCP VCC(ovp) 4−pulse counter OTP V CS(stop) S S OFF Q Q R 4−s timer latch Q Q AUTO − RECOVERY (B version) R LATCHING − OFF (A version) VCCreset Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits VCC Over Voltage Protection Programmable Over Voltage Protection (OVP2) The circuit stops generating pulses if VCC exceeds VCC(OVP) and enters auto−recovery mode. This feature protects the circuit if the output LED string happens to open or is disconnected. Connect a Zener diode between VCC and the SD pin to set a programmable VCC OVP (DZ of Figure 67). The triggering level is (VZ+VOVP) where VOVP is the 2.5−V internal threshold. If this protection trips, the NCL30185A latches off while the NCL30185B enters the auto−recovery mode. www.onsemi.com 24 NCL30185 Vdd I OTP(REF) NCL30185B (auto−recovery version) SD Pin OVP (OVP2) DETECTION S + VCC − VOVP TSD(delay) DZ Q Q OFF R SD 4−s Timer OTP DETECTION − NTC NCP30185A (latching−off version) + TOTP(start) VOTP(off) / V OTP(on) S Thermal Foldback Q Q Latch R VTF Clamp grand reset Rclamp Vclamp Figure 67. Thermal Foldback and OVP/OTP Circuitry The SD pin is clamped to about 1.35 V (Vclamp ) through a 1.6−kW resistor (Rclamp ). It is then necessary to inject about ǒ circuit gradually reduces the LED current down 50% of its initial value when VSD reaches VTF(stop), in accordance with the characteristic of Figure 68 (Note 9). If this thermal foldback cannot prevent the temperature from rising (testified by VSD drop below VOTP), the circuit latches off (A version) or enters auto−recovery mode (B version) and cannot resume operation until VSD exceeds VOTP(on) to provide some temperature hysteresis (around 10°C typically). The OTP thresholds nearly correspond to the following resistances of the NTC: • Thermal foldback starts when RNTC ≤ RTF(start) (11.7 kW, typically) • Thermal foldback stops when RNTC ≤ RTF(stop) (8.0 kW, typically) • OTP triggers when RNTC ≤ ROTP(off) (5.9 kW, typically) • OTP is removed when RNTC ≥ ROTP(on) (8.0 kW, typically) (Note 10) Ǔ V OVP * V clamp R clamp that is ǒ2.501.6* k1.35 ^ 700 mAǓ typically, to trigger the OVP protection. This current helps ensure an accurate detection by using the Zener diode far from its knee region. Programmable Over Temperature Foldback Protection (OTP) Connect an NTC between the SD pin and ground to detect an over−temperature condition. In response to a high temperature (detected if VSD drops below VTF(start)), the 9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if step−dimming is not engaged or a lower one based on the step−dimming value. 10. This condition is sufficient for operation recovery of the B version. For the A version which latches off when OTP triggers, the circuit further needs to be reset by a VCC drop below VCC(reset). www.onsemi.com 25 NCL30185 At startup, when VCC reaches VCC(on), the OTP comparator is blanked for at least 180 ms in order to allow the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. This avoids flickering of the LED light during turn on. Brown−Out Protection The NCL30185 prevents operation when the line voltage is too low for proper operation. As illustrated in Figure 69, the circuit detects a brown−out situation if the VS pin remains below the VBO(off) threshold (0.9 V typical) for more than the 25−ms blanking time. In this case, the controller stops operating. Operation resumes as soon as the VS pin voltage exceeds VBO(on) (1.0 V typical) and VCC is higher than VCC(on). To ease recovery, the circuit overrides the VCC normal sequence (no need for VCC cycling down below VCC(off)). Instead, its consumption immediately reduces to ICC(start) so that VCC rapidly charges up to VCC(on). Once done, the circuit re−starts operating. Figure 68. Output Current Reduction versus SD Pin Voltage BONOK VS pin + 25−ms blanking time − 1.0 V / 0.9 V Figure 69. Brown−out Circuit • Fault of the GND connection Die Over Temperature (TSD) The circuit stops operating if the junction temperature (TJ) exceeds 150°C typically. The controller remains off until TJ goes below nearly 100°C. If the GND pin is properly connected, the supply current drawn from the positive terminal of the VCC capacitor, flows out of the GND pin to return to the negative terminal of the VCC capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non−connection of the GND pin is monitored by detecting that one of the ESD diode is conducting. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 ms, the circuit stops generating DRV pulses. Pin Connection Faults • The circuit addresses most pin connection fault cases: CS pin short to ground The circuit senses the CS pin impedance every time it starts−up and after DRV pulses terminated by the 36−ms maximum on−time. If the measured impedance does not exceed 120 ohm typically, the circuit stops operating. In practice, it is recommended to place a minimum of 250−ohm in series between the CS pin and the current sense resistor to take into account possible parametric deviations. More generally, incorrect pin connection situations (open, grounded, shorted to adjacent pin) are covered by AND9204/D. www.onsemi.com 26 NCL30185 Fault Modes In this mode, the DRV pulses generation is interrupted. In the case of a latching−off fault, the circuit stops pulsing until the LED driver is unplugged and VCC drops below VCC(reset). At that moment, the fault is cleared and the circuit could resume operation. In the auto−recovery case, the circuit cannot generate DRV pulses for the auto−recovery 4−s delay. When this time has elapsed, the circuit recovers operation as soon as the VCC voltage has exceeded VCC(on). In the B version, all these protections are auto−recovery. The SD pin OTP and OVP, WOD_SCP and AUX_SCP are latching off in the A version (see Table 6). The circuit turns off whenever a major faulty condition prevents it from operating: • Severe OTP (VSD level below VOTP(off)) • VCC OVP • OVP2 (additional OVP provided by SD pin) • Output diode short circuit protection: “WOD_SCP high” • Output / Auxiliary winding Short circuit protection: “Aux_SCP high” • Die over temperature (TSD) Table 6. PROTECTION MODES AUX_SCP WOD_SCP SD Pin OTP SD Pin OVP NCL30185A* Latching off Latching off Latching off Latching off NCL30185B Auto−recovery Auto−recovery Auto−recovery Auto−recovery ORDERING INFORMATION Device Package Type Shipping NCL30185ADR2G* SOIC−8 (Pb−Free/Halide Free) 2500/Tape & Reel NCL30185BDR2G SOIC−8 (Pb−Free/Halide Free) 2500/Tape & Reel *Please contact local sales representative for availability www.onsemi.com 27 NCL30185 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 28 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCL30185/D