AND9200/D 4 Key Steps to Design a NCL30088‐Controlled LED Driver Description This paper proposes the key steps to rapidly design a NCL30088-driven flyback converter to power an LED string. The process is illustrated by a practical 10 W, universal mains application: • Maximum Output Power: 10 W • Input Voltage Range: 90 to 265 V rms • Output Voltage Range: 12 to 20 V dc • Output Current: 500 mA www.onsemi.com APPLICATION NOTE Introduction • Output Short-circuit Protection (AUXSCP): If the ZCD The NCL30088 is a driver for power-factor corrected flyback, non-isolated buck-boost and SEPIC converters. The current-mode, quasi-resonant architecture optimizes the efficiency by turning on the MOSFET when the drain-source voltage is minimal (valley). At high line, the circuit delays the MOSFET turn on until the second valley is detected to reduce the switching losses. An internal proprietary circuitry controls the input current in such a way that a power factor as high as 0.99 and an output current deviation below ±2% are typically obtained without the need for a secondary-side feedback. The circuit further contains a suite of powerful protections to ensure a robust LED driver design without the need for extra components or overdesign. Among them, one can list: • Over Temperature Thermal Fold-back: connecting a NTC to the SD pin allows for gradual reduction of the LED current down to 50% of its nominal value when the temperature is excessive. If the current reduction does not prevent the temperature from reaching a second level, the controller stops operating (SD_OTP). • Over Voltage Protection (SD_OVP): A Zener diode can further be used on the SD pin to provide an adjustable OVP protection (SD OVP). • Cycle-by-cycle Peak Current Limit: when the current sense voltage exceeds the internal threshold (VILIM ), the MOSFET immediately turns off (cycle-by-cycle current limitation). • Winding and Output Diode Short-circuit Protection (WODSCP): an additional comparator stops the controller if the CS pin voltage exceeds (150% ⋅ VILIM ) for 4 consecutive cycles. This feature can protect the converter if a winding or the output diode is shorted or simply if the transformer saturates. © Semiconductor Components Industries, LLC, 2016 April, 2016 - Rev. 2 • • pin voltage remains low for a 90-ms time interval, the controller stops pulsating until 4 seconds has elapsed. Open LED Protection: if the VCC pin voltage exceeds the OVP threshold, the controller shuts down and waits 4 seconds before restarting switching operation. Floating/Short Pin Detection: the circuit can detect most of these situations which helps pass safety tests. Selecting the Right NCL30088 Version There exist four NCL30088 versions. They differ in: • Their respective protection mode. The WODSCP, AUXSCP and the SD over-temperature (OTP) and over-voltage (OVP) protections are latching-off (A and C versions) or auto-recovery (the circuit resumes operation after a 4-second delay – B and D versions). • The internal duty-ratio limitation. NCL30088A/B duty-ratio is internally limited to 50% at the top of the lowest line sinusoid. They are recommended if the lowest line peak voltage is higher than the inductor demagnetization voltage, i.e.,: ♦ If ǒǸ2 @ (V ) w V ) V Ǔ with non-isolated in,rms LL out converters, ♦ ǒ f Ǔ np If Ǹ2 @ (V in,rms) LL w n (V out ) V f) in flyback s applications where (Vin,rms )LL is the lowest-line rms voltage (85 or 90 V rms in general) and (Vf ) is the output diode forward voltage. The C and D versions that allow the duty-ratio to reach 60% at the top of the lowest line sinusoid, must be preferred otherwise. See Table 1. 1 Publication Order Number: AND9200/D AND9200/D Table 1. SELECTING THE RIGHT NCL30088 VERSION WODSCP, AUXSCP, SD_OTP and SD_OVP Protection Mode NCL30088A (Note 3) NCL30088B NCL30088C (Note 3) NCL30088D Output Voltage Range for Non-isolated Converters (Note1) Output Voltage Range for Flyback Converters (Note 2) V out ) V f v Ǹ2 (V in,rms) LL n V out ) V f v n s Ǹ2 (V in,rms) LL V out ) V f v Ǹ2 (V in,rms) LL n V out ) V f v n s Ǹ2 (V in,rms) LL Latching Off V out ) V f v 3 @ Ǹ2 (V in,rms) LL 2 n V out ) V f v n s @ 3 @ Ǹ2 (V in,rms) LL p 2 Auto-recovery V out ) V f v 3 @ Ǹ2 (V in,rms) LL 2 n V out ) V f v n s @ 3 @ Ǹ2 (V in,rms) LL p 2 Latching Off Auto-recovery p p 1. (Vin,rms )LL is the lowest-line rms voltage (e.g., 85 V rms), (Vf ), the output diode forward voltage. 2. (Vin,rms )LL is the lowest-line rms voltage (e.g., 85 V rms), (Vf ), the output diode forward voltage. 3. Please contact local sales representative for availability. As an example, let’s assume that we must design a 90 to 265 V rms, non-isolated buck-boost converter whose output can be as high as 150 V. Let’s see if A/B version can be used. Ǹ2 (V Ǹ in,rms) LL + 2 @ 90 ^ 127V v V out ) V f ^ 150V Eq. 1 indicates that the Table 1 condition of using the A and B versions in non-isolated converters applications is not (eq. 1) met. Hence, the A/B version is not recommended while the C or D version is ok since: 3 @ Ǹ2 (V 3 @ Ǹ2 @ 90 ^ 191V w V ) V ^ 150V out in,rms) LL + f 2 2 (eq. 2) at the lowest line voltage but will meet the target when the input voltage level is sufficient. Thus, you can start with the NCL30088A or the NCL30088B and consider the NCL30088C or NCL30088D if the LED current is too low at the lowest line levels. By the way, a symptom of the duty-ratio limitation effect can be observed as shown by Figure 1 where the input current is clamped by the over-current protection during normal load conditions. Generally speaking, the A and B versions are typically preferred in narrow-mains non-isolated converters or flyback LED drivers [the turns ratio of isolated flyback converters, gives some flexibility − see Table 1 conditions]. C and D versions are generally to be selected for wide-mains, non-isolated converters. If the duty-ratio limitation is exceeded by your application, the LED current will be below its nominal value VCC ILED The current is clamped to (VILIM / Rsense) MOSFET current Figure 1. Current Over-current Limitation (VILIM is the Over-current Threshold, Rsense the Current Sense Resistor) Our application of interest is a flyback converter. In this case, the turns ratio must be considered when selecting the appropriate version. We will see that in this specific case, the NCL30088B is the appropriate option. www.onsemi.com 2 AND9200/D LED Driver Dimensioning D1 RSTUP Aux RC . . RS1 COUT . DC RZCD1 CC NCL30088 RS2 1 8 2 7 3 6 4 5 Q1 RLFF CZCD RZCD2 CCOMP CSD RTH DZ C2 C1 CCS RSENSE Figure 2. Basic Schematic STEP 1: POWER COMPONENTS SELECTION This leads in our case to: Basically, the transformer, the output capacitor and the power silicon devices are dimensioned “as usual”, that is, as done with any other PF corrected, quasi-resonant flyback converter. This chapter does not detail this process, but highlights the major points. n AUX v n S @ 25.5 ^ 1.3 @ n S 20 ) 1 (eq. 5) Practically, we will select (nAUX = nS). In this case, VCC will be in the range of Vout , with some deviations due to the imperfect coupling. Transformer Selection Selecting the Auxiliary Winding Number of Turns An auxiliary winding is necessary for zero current detection and to provide the VCC voltage. The output voltage of a LED driver generally exhibits a large range. The VCC voltage provided by the auxiliary winding will vary in a similar manner. The NCL30088 features a large VCC range to address these variations. Practically, after start-up, the operating range is 9.4 V up to 25.5 V. NOTE: (VCC(OVP) )min = 25.5 V is the threshold minimum value of the VCC over-voltage protection. This safety feature protects the circuit if the LED string happens to be disconnected. Selecting the Secondary Winding Number of Turns In general, NPS , the secondary to primary transformer turns ratio (NPS = nS / nP) [nP designates the primary number of turns, nS , the secondary number of turns] is selected as low as possible so that the input current stress is reduced. NPS cannot be too small however. NPS sets the amount of voltage reflected during the off-time (see Figure 3) and hence, must be high enough to limit the voltage stress across the primary-side MOSFET. Indeed, the voltage to be sustained by the primary-side MOSFET and the output diode are: The auxiliary winding number of turns can be selected so that the auxiliary voltage is slightly below (VCC(OVP))min when the output voltage is at a maximum factoring in impact of the 100/120-Hz ripple. Practically, this criterion turns into: V diode,max + N PS Ǹ2 (V in,rms) max ) V out ) V f ) V D*ov n AUX n S (V out,max ) V f) v (V CC(OVP)) min ) V f V DS,max + Ǹ2 (V in,rms) max ) (V CC(OVP)) min ) V f V out,max ) V f (eq. 6) Where: • NPS is the secondary to primary transformer turns ratio NPS = nS / nP • VQ−ov is the MOSFET overvoltage shown in Figure 3. This overshoot is due to the leakage inductor reset. It is limited by the clamping network consisting of DC , CC and RC of Figure 2. • VD−ov is a similar overshoot that occurs across the output diode when the MOSFET turns on. (eq. 3) Hence: n AUX v n S @ V out ) V f ) V Q*ov N PS (eq. 4) www.onsemi.com 3 AND9200/D The clamping network is often designed so that VQ−ov is between 50% and 100% of the reflected voltage: V Q*ov + k C @ v out ) V f with 0.5 v k c v 1.0 N PS V ds,max + Ǹ2 @ (V in,rms) HL ) N PS (eq. 8) Some derating is generally requested. The typically-applied 15% safety factor implies that the MOSFET voltage does not exceed 85% of its breakdown voltage. Hence: (eq. 7) We can estimate the maximum voltage reached on the drain node, considering Vout(OVP) level as the maximum output voltage: V ds,max + Ǹ2 @ (V in,rms) HL ) (1 ) k c)(V out(OVP) ) V f) (1 ) k c)(V out(OVP) ) V f) N PS v 85%V DSS (eq. 9) 85%V DSS* Ǹ2 @ (V in,rms) HL nP v nS (1 ) k c)(V )V) Where VDSS is the MOSFET breakdown voltage. out(OVP) Finally: (eq. 10) f Figure 3. MOSFET Drain-source Voltage (Yellow Trace) and Current (Blue) In our application, (Vin,rms )HL is 265 V rms and (Vout(OVP) + Vf ) is about 28 V. With a 600 V MOSFET, nP 85% @ 600* Ǹ2 @ 265 ^ 4.8 n S (1 ) k c) v 28 f sw + nP 85% @ 800* Ǹ2 @ 265 ^ 10.9 (eq. 12) n S (1 ) k c) v 28 We select the second option (800 V MOSFET) with nP n S + 6 and (kc = 80%), which meets Eq. 12 requirements n since nP (1 ) k c) + 6 @ 180% + 10.8 v 10.9 . S It can be easily checked that the Table 1 condition of using the A or B version is met. The NCL30088B will be used for this application. ǒ Ǔ Ǔ 2 (eq. 13) The switching frequency is a rising function of the rms line voltage. At a given line magnitude, the switching frequency is yet higher near the line zero crossing and decays as the line voltage rises due to the (nin (t)) term. Note that when high-line conditions are detected (see NOTE), the NCL30088 does not operate in quasi-resonant mode but delays the MOSFET turn on until the 2nd valley is detected (see Figure 4). This reduces the switching frequency upper range and optimizes the high-line efficiency. NOTE: The input voltage is sensed by the VS pin for brown-out protection, feedforward and line range detection. High-line conditions are detected when the VS pin voltage exceeds 2.4 V typically. See data sheet for more details. (eq. 11) With a 800 V MOSFET, ǒ ǒ (V in,rms) 2 V out ) V f @ 2L PP in,avg N PS n in(t) ) V out ) V f Ǔ Selecting the Primary Inductance Assuming a quasi-resonant operation and neglecting the small delay necessary for detecting the MOSFET drain-source valley, the primary inductance dictates the switching frequency as follows: www.onsemi.com 4 AND9200/D Figure 4. Quasi-Resonant Mode in Low Line (Left), Turn On at Valley 2 when in High Line (Right) The primary inductor will be selected with respect to the targeted switching frequency range, keeping in mind that: • High switching frequency levels reduce the size of the storage elements • Conversely, increasing the switching frequency leads to more switching noise and losses. Also, EMI filtering may be tougher because of the EMI generated at the switching frequency and close harmonic levels. Most power supplies have to meet standards which apply to frequencies above 150 kHz. That is why SMPS designers often select FSW = 130 kHz to keep the fundamental component below 150 kHz and then out of the regulation scope. Often, 65 kHz is also chosen to not to have to damp harmonic 2 too. • nominal line voltage when ǒ n in(t) + V in,pkń2 Ǔ Our application is a wide-range one. Let us compute LP so that at 115 V rms, the switching frequency is below fsw,T = 65 kHz: ȡ ȧ ȢN LP w (P in,avg) max (V in,rms) LL (P in,avg) max (I L,pk) max + 2 Ǹ3 (V in,rms) LL ǒ @ 1) Ǹ ǒ Ǹ (I L,rms) max + 2 12 @ @ Ǹ3 90 1) 1) 2 @ 65 @ 10 3 @ 12 90 6 N PS(V in,rms) LL V out ) V f @ 2 ǒ 12 ) 1 Ǹ2@115 6@2 (eq. 14) f Ǔ ) 12 ) 1 Ǔ 16 Ǹ2 @ (V in,rms) LL 1) In our application, assuming an efficiency of 84% ((Pin,avg )max = 12 W), Eq. 16 and Eq. 17 lead to: 12 (I L,pk) max + 2 Ǹ2 @ @ 90 PS ) V out 2 ^ 2 mH (eq. 15) Finally we have to consider the primary current magnitude constraints: in,pk (I L,pk) max + 2 Ǹ2 @ Ǹ2@V in,rms Which leads to: 115 2 ȣ ȧ ) VȤ 2 V out ) V f (V in,rms) 2 LP w @ 2f sw,TP in,avg As the rule of thumb, let us select LP as follows: • In wide mains application: choose LP so that the switching frequency is below 65 kHz at the low-line range nominal voltage (typically 115 V rms) over a large part of the sinusoid. Practically, we can select that the frequency target will have to meet starting from (V ń2) that is ǒǸ2 @ 115ń2Ǔ. This arbitrary choice relies on the idea that for below this line voltage level the input current is relatively small and easy to filter. Check that at the high-line nominal voltage (230 V rms typically), the switching frequency stays below 65 kHz thanks to the valley-2 operation. Similarly, in a narrow mains operation case, select LP so that the switching frequency is below 65 kHz at the 3p @ Ǔ 20 ) 1 V out)V N PS f (eq. 16) ) 6p @ (V in,rms) LL 4@ ǒ V out)V N PS ^ 0.65 A 16 Ǹ2 @ 90 6p @ 90 2 ) ^ 350 mA 3p @ 6 @ 21 4 @ (6 @ 21) 2 We selected transformer 750871144 from Wurth Elektronik with the following characteristics: LP = 1.9 mH, nP / nAUX = nP / nS = 6. www.onsemi.com 5 Ǔ 2 2 (eq. 17) f (eq. 18) (eq. 19) AND9200/D Power Switches a circuit requires a diode, a resistor and a capacitor (DC , RC and CC of Figure 2): • The capacitor CC absorbs the leakage inductor energy when the MOSFET turns off. The voltage rating of this capacitor must be equal to the MOSFET breakdown voltage or higher. Note that similarly to the snubber capacitor, the CC negative terminal should preferably be connected to the MOSFET source rather than to ground. • The resistor RC loads CC to ensure that the CC voltage does not drift up but stabilize at a level which ensures a proper MOSFET protection (the MOSFET voltage is clamped to the CC voltage by means of DC ). • The diode DC prevents CC from discharging when the MOSFET turns on. This diode is generally a fast-recovery diode. A low-value resistor (R14 of Figure 9) is inserted to limit the current spike which otherwise occurs when the MOSFET turning off, CC abruptly charges. Do not oversize this series resistor. The leakage current flowing through it creates a voltage drop. The MOSFET voltage is clamped to the CC voltage PLUS the series resistor voltage. In our case, the maximum leakage current is (V ILIMńR sense) that is (1Vń1.5W ^ 667mA). In our design, a 22 W resistor is implemented that results in an overshoot less than (22W @ 0.667 ^ 17V). MOSFET The voltage constraints on the MOSFET have been discussed in the transformer section. Conduction losses depend on the MOSFET rms current which can be computed with the following equation: (P in,avg) max (I Q,rms) max + 2 Ǹ3 (V in,rms) LL Ǹ 1) 8 Ǹ2 @ (V in,rms) LL 3p @ V out)V N f PS (eq. 20) A NDD03N80 MOSFET is selected (DPAK, 800 V, 4.5 W). Output Diode Similarly, the voltage constraints have been discussed in the previous section. Losses are mainly produced by the average current flowing through the diode. This average is simply the LED current (0.5 A in our case). A 200-V, 2-A SMB diode is selected (MURS220). Snubber and Clamping Network A snubber capacitor can be placed across the MOSFET to reduce the dV/dt and lower the switching noise. A 47-pF, 1,000-V capacitor is placed in our application (C2 of Figure 9). Note that for optimal operation, it is recommended to connect the snubber capacitor between the MOSFET drain and source terminals rather than between drain and ground. When the MOSFET turns off, the magnetizing inductor energy is conveyed to the secondary side and charges the output. The leakage inductor current cannot be used by the output. It must be diverted from the MOSFET. If not, the MOSFET drain-source voltage would rise to destructive levels. A clamping network is hence necessary. Such )V ) f out(OVP) N PS (1)k c )@(V ER + @ Eq. 8 gives the maximum voltage (1 ) k c)(V out(OVP) ) V f) Ǹ2 @ (V in,rms) HL ) N PS the MOSFET must sustain. This voltage is the CC maximum voltage. Hence, the energy that RC can consume and re-inject to the input over a switching cycle is given by: ǒ ǒ Ǔ )V ) f out(OVP) N PS (1)k c )@(V Ǔ ) Ǹ2 @ (V in,rms) HL @ T SW (eq. 21) RC C The energy due to the leakage inductor must be handled. V ILIM It is maximal when the primary current exceeds its R sense limit where VILIM is the over-current protection threshold and Rsense , the current sense resistor: ǒ Ǔ ǒ V ILIM EL + 1 L leak leak 2 R sense Ǔ@ 2 )V ) f out(OVP) N PS (1)k c )@(V )V ) (V )V ) f f out(OVP) out(OVP) * N N PS PS (1)k c )@(V + This energy of Eq. 21 must be equal or higher than the leakage inductor energy defined in Eq. 22. From this, we can deduce the following minimum RC value: (V RC v )V ) f out(OVP) N PS @ ǒ )V ) f out(OVP) N PS (1)k c )@(V 1 2@k C L leak ǒ V ILIM R sense Ǔ ) Ǹ2 @ (V in,rms) HL Ǔ 2 (eq. 22) Ǔ (eq. 23) 2 @ f SW www.onsemi.com 6 ǒ 1 ) kC V ILIM L 2 @ k C leak R sense AND9200/D Ǹ Select the CC capacitor so that the time constant (RC ⋅ CC ) is large compared to a switching period, practically, in the range of 1 ms. Since in our application, we have selected (kC = 80%), it comes: RC v 28 @ 6 ǒ(180% @ 28 @ 6) ) Ǹ2 @ 265Ǔ 1 2@80% 1 Ǔ 20m ǒ1.5 @ 65k 2 ȡ ȧǒ Ȣ C out,min + ^ 315 kW (180% @ 28 @ 6) 2 ^ 290mW 315k Two 470 kW, 1/2W resistors are placed in parallel for the following effective resistance: (470 k || 470 k = 235 kW). A 4.7 nF/100 V capacitor is implemented for CC that with RC forms a 1.1 ms time constant. This resistor will dissipate The power delivered by PFC converters exhibits a large ac component at twice the line frequency. To some extend, the output capacitor compensates for it but yet, the output current exhibits some ripple inversely proportional to the capacitor value (Cout ). Below equation expresses the current ripple: C out,min + Ǹ S 2 @ (eq. 26) 4p @ f line,min @ R LED,min (eq. 27) Ǹǒ Ǔ *1 2 2 1 2 @ 100p @ 6 ^ 460 mF (eq. 28) A 470 F/35 V is implemented. Bulk Capacitor Heating: It must also be checked that the ESR is low enough to prevent the rms current that flows through it, from overheating the bulk capacitor. This capacitor rms current can be estimated using the following expression. From Eq. 25, the following minimum value for Cout can be deduced (Eq. 26): P pk*pk I out,nom In our application the minimum LED dynamic resistance is estimated to be 6 W and the minimum line frequency is 50 Hz. In this case, the minimum output capacitor value is: (eq. 25) ȡ32 Ǹ2 n ȧ 9p @ ǒn Ǔ Ȣ 2 DI outǓ (DI out) pk*pk +1 I out,nom Output Capacitor (I C,rms) max + 2 Cout must then be large enough to avoid an excessive current ripple which could reduce the LED reliability. The flicker index is commonly specified below 0.15. This requirement corresponds to a 100% peak-to-peak ripple in a PF-corrected LED driver with a sinusoidal output current shape This criterion (100% peak to peak ripple), leads to: (eq. 24) (DI out) pk*pk 2 + I out,nom Ǹ1 ) (4p @ fline @ R LED @ C out)2 ȣ ȧ*1 Ȥ (P in,avg) max V in,rms @ 2 V out)V N PS ȡ 9p V ȣȣ ȧ1 ) 16 Ǹ2 @ ȧȧ*I Ȣ ȤȤ 2 f in,rms V out)V f N PS 2 (eq. 29) out,nom It remains wise to check the output capacitor heating in the lab. STEP 2: OUTPUT CURRENT SETTING As explained in the data sheet, the output current is regulated to equal the following Iout,nom nominal output current: V REF I out,nom + 2N PSR sense R sense + V REF 2N PSI out,nom (eq. 31) The power dissipated by Rsense can be computed by the following equation: (eq. 30) ǒ Ǔ ȡȧ P in,avg P Rsense + 4 R sense 3 V in,rms Where: • NPS is the secondary to primary transformer turns ratio NPS = nS / nP • Rsense is the current sense resistor (see Figure 2) • VREF is the output current internal reference. In our application: • NPS = 1/6 • Iout,nom = 500 mA • (Pin,avg )max = 12 W • (Vin,rms )LL = 90 V • Vout,min = 10 V Hence once the transformer is designed, NPS is known and the only current sense resistor dictates the output current level. www.onsemi.com 7 2 1) Ȣ ȣ ȧ (eq. 32) Ȥ 8 Ǹ2 @ V in,rms V out 3p @ N PS AND9200/D Hence: R sense + 250 @ + 1.5 W 2 @ 16 @ 500 @ 10 *3 10 *3 And: ǒ Ǔ P Rsense + 4 1.5 12 90 3 2 ǒ 1) Ǔ 8 Ǹ2 @ 90 10 3p @ 1ń6 R S2 @ Ǹ2 (V in,rms) BOH + V BO(on) R S1 ) R S2 (eq. 33) Where VBO(on) is the internal threshold (1 V typically) the VS pin voltage must exceed to allow circuit operation. In other words, ^ 100 mW R S1 + R S2 (eq. 34) Input Voltage Sensing and Feedforward: A portion of the input voltage must be applied to the VS pin to provide the circuit with the sinusoidal reference necessary for shaping the input current (PFC). The obtained current reference is further modulated so that when averaged over a half-line period, it is equal to the output current reference (VREF ). This averaging process is made by an internal Operational Trans-conductance Amplifier (OTA) and the capacitor connected between the COMP pin (pin3) and ground. The recommended minimum COMP capacitance is 1 mF. R S1 + 47 @ 10 3 @ (eq. 36) ǒ Ǔ Ǹ2 @ 81 *1 [ 5.4 MW 1 (eq. 37) Feedforward The NCL30088 computes the current setpoint (Vcontrol ) for power factor correction and proper regulation of the LED current. Now, the MOSFET cannot turn off at the very moment when the current-sense voltage exceeds Vcontrol . There actually exists a propagation delay tprop (Figure 5) for which the primary current keeps rising. As a result, the primary current does not exactly peak to the expected (Vcontrol / Rsense ) value but to a higher level. The output current is hence also affected. Optimal regulation performance requires the peak current increase caused by tprop to be compensated. Input Voltage Sensing A resistors divider (RS1 and RS2 of Figure 2) provides pin 2 with the VS signal. The scale-down factor is computed in accordance with the brown-out protection. If (Vin,rms )BOH is the targeted minimum line rms voltage necessary for entering operation, RS1 and RS2 must comply with: Rsense Ǔ Ǹ2 @ (V in,rms) BOH *1 V BO(on) It is generally recommended not to have a single resistor placed between a high-voltage rail and a low potential node. Instead, two or more resistors are to be placed in series. In our case, we use two 2,700 kW resistors for RS1. COMP Pin Capacitor A 1 mF capacitor is to be placed between COMP pin and ground. Vcontrol ǒ RS2 values in the range of 50 kW generally provide a good tradeoff between losses and noise immunity. In our application, we select 47 kW. Our system being supposed to enter operation when the line voltage exceeds 81 V rms: Two 3 W resistors are placed in parallel. IL (eq. 35) DIL,pkH High Line DIL,pkL Low Line tprop tprop Figure 5. Propagation Delay Effect on Peak Current www.onsemi.com 8 time AND9200/D However, for a first approximation, we can calculate RLFF, using tprop = 200 ns. Then, the offset resistor value can be fine-tuned on the bench so that the output current characteristic is nearly flat over the line voltage range. Using Eq. 40, we can calculate the first value of RLFF for our design: The NCL30088 compensates for the propagation delay by sourcing a current proportional to the VS pin voltage out of the CS pin during the on-time. Placing a resistor RLFF between the CS pin and the sense resistor, the following offset is hence obtained: V CS(offset) + K LFF n S (t)R LFF (eq. 38) ǒ Where the VS pin voltage vS (t) equates: n S(t) + R S2 n (t) R S1 ) R S2 in R LFF + 1 ) (eq. 39) ǒ R S1 R S2 Ǔ t L RK prop P Sense prop P Sense + LFF (eq. 41) Ǔ + 1 ) 5400 200n 47 1900m Ǔ R LFF + 1 ) Ǔ t L RK ǒ Since the CS pin offset must compensate for R sense @ n in(t) @ t prop R sense @ DI L,pk + , the offset resistor LP value can be computed as follows: ǒ R S1 R S2 1.5 ^ 915W 20m After experiments in the lab, RLFF value was decreased to 820 W. Important Note: As indicated in the NCL30088 data sheet, RLFF must be selected higher than 250 W. If not, the circuit may improperly detect that the CS pin is grounded. (eq. 40) LFF Where: • KLFF is the VS pin voltage to CS pin current conversion ratio. Its typical value is 20 mS. • RS1 and RS2 are the input voltage sensing resistors (see Figure 2). Selecting the CS Pin Capacitor The shape of the current-sense voltage influences the output current regulation. If the CS pin filter (RLFF, CCS ) is too big, the output current setpoint will vary (Iout higher than expected value). Thus, once RLFF has been chosen, it is important to keep the value of CCS as small as possible to have an optimal output current regulation. CCS should be in the range of 10–100 pF. Finally: (see Table 2) Parameter tprop includes the controller internal delay of the controller (about 50 ns) and the MOSFET turning off time. Thus, it varies with respect to the chosen MOSFET and the way it is driven (value of the gate resistors for instance). As a consequence, it is difficult to predict its exact value prior to evaluating the LED driver design. Table 2. RS1 RS2 CCOMP RSENSE RLFF CCS 5400 kW (two 2.7 MW placed in series) 47 kW 1 mF 1.5 W (two 3 W resistors in parallel) 820 W − • The output current value depends on the sense resistor NCL30088 proprietary regulation technique ensures a very precise LED current control. Please note that sources of deviation are however to be considered. They are detailed in [3]. Let’s recall the main points: • The NCL30088 regulates the total current provided by the converter, that are, the LED current plus the VCC current. Hence, the actual output current is: I out,nom + In general, the N N P @ V REF * Aux I CC NS 2 @ N S @ R sense ǒNN Aux S • (eq. 42) (Rsense ). Select a precise resistor and avoid long tracks that lead to an additional series resistance. If Rsense is 1 W and that the circuit additionally senses the voltage across a 20 mW track, the total sensing resistor will be 1.02 W instead of 1 W. Ultimately, the output current will 2% below target. Avoid inductive sense resistor. If not, the output current will be less than the target because of the offset the series inductor causes on the CS pin voltage: l Rsense @ n in(t) where l Rsense is the Rsense parasitic LP inductance. ǒ Ǔ I CC term is small compared to the target LED current and can be ignored. If not, Rsense should be reduced to compensate for the circuit consumption. www.onsemi.com 9 Ǔ AND9200/D STEP 3: SD PIN MANAGEMENT Selecting the Thermistor The Thermal Foldback and Shutdown block of the NCL30088 is inherited from the NCL30082 and its functioning and design is detailed in application note AND9131/D ([2]). Only key points will be highlighted here. The resistance of a Negative Coefficient Temperature thermistor (NTC) reduces when its temperature rises. An NTC is to be placed between the SD pin and ground to detect an over-temperature condition. In response to a high temperature, the circuit gradually reduces the LED current down 50% of its nominal value. If despite the current reduction, the temperature still increases, the circuit will eventually stop operation. In general a 50% reduction in current is more than a 50% drop dissipated power as the LED forward voltage will decrease as the current is folded back. More specifically, as shown by Figure 6, Rth designating the NTC resistance: • The circuit starts to gradually reduce the output current when Rth drops below RTF(start) and continues diminishing it until Rth goes below RTF(stop). • At that moment, it maintains the output current at 50% of its nominal level as long as Rth is between RTF(stop) and ROTP(off). If on the contrary, a temperature decay leads Rth to rise above RTF(stop), the current increases according the precedent characteristics. If Rth exceeds RTF(start), full current capability is recovered. • The LED driver totally stops operating if Rth drops below ROTP(off) and stays off until the temperature having reduced, Rth exceeds ROTP(on). At that moment, the circuit resumes (NCL30088B and NCL30088D only – A and C versions latch off) and delivers 50% of the nominal current. • If Rth further rises, the current regulation grows as well until Rth reaches RTF(start). At that moment, the LED driver provides the full current. Selecting the SD Over-voltage Zener Diode A Zener diode can be placed between the VCC and the SD pins. The circuit detects an OVP fault if the SD pin voltage exceeds 2.5 V. Note that the NCL30088 ensures that a 700 mA minimum current flows through the Zener diode in this case (see [1]) so that it can be operated far from its knee region. The SD OVP threshold on VCC is: (V CC) SD,OVP + V Z ) V OVP (eq. 43) Where VOVP is the 2.5-V SD OVP threshold. An SD OVP fault is detected if VCC exceeds (VCC )SD,OVP. For instance, if you applied a Zener diode exhibiting an 18-V Zener breakdown voltage (when biased by a 700 mA current), the SD_OVP protection will trip when VCC exceeds (18.0 + 2.5) volts, that is, 20.5 V. In this case, the NCL30088B/D stops operating for the auto-recovery 4 s delay. At the end of this time, the circuit attempts to resume operation. If the fault is still present, the circuit again detects an SD OVP fault and stops for 4 s. Finally, the NCL30088B or NCL30088D enters a safe, very low duty-ratio burst mode. An SD OVP fault leads the NCL30088A and NCL30088C to latch off until the LED driver is unplugged and VCC drops below VCC(reset). At that moment, the fault is cleared and the circuit can resume operation. Such a programmable protection feature is useful if the fixed VCC OVP protection which trips when VCC exceeds VCC(OVP) (26.8 V typically) does not clamp the output voltage at a low enough level. This is not the case in our application. No Zener diode is hence implemented. Figure 6. Thermal Foldback Characteristics and Over-temperature Protection www.onsemi.com 10 AND9200/D As an example, if thermistor NB12P00104JBB from AVX is implemented: • The circuit starts to reduce the output current at about 82°C ambient temperature. • The circuit stops operation at about 104°C ambient temperature. • The circuit recovers operating at about 90°C ambient temperature. capacitor must not exceed 4.7 nF so that it can charge to its nominal level before the OTP blanking time has elapsed. NOTE: At start-up, the controller blanks the SD function until a delay of 250 ms minimum (OTP blanking time), has elapsed, to provide CSD with enough time to properly charge above the 0.5 V over-temperature threshold. If not, the low SD pin voltage will be considered as caused by the low-resistance of an NTC in excessive temperature conditions. Selecting the SD Pin Capacitor A small capacitor can be placed between the SD pin and ground to prevent the pin from picking up possible surrounding noise. Please note that the value of this Finally: (see Table 3) Table 3. DZ Rth CSD N/A NB12P00104JBB (AVX) 1 nF STEP 4: AUXILIARY WINDING AND VCC MANAGEMENT VCC Capacitor Refueling VCC Capacitor Value and Startup Circuitry In nominal operation, the auxiliary winding provides the VCC voltage as shown by Figure 2. The auxiliary winding number of turns (naux ) is computed in the transformer section of the “Step 1” paragraph. Note that during the on-time, diode DAUX of Figure 2 rectifies the auxiliary voltage to provide VCC . Hence, neglecting the turn on spike, DAUX must be able to sustain: When off (that is until VCC has reached the 18-V start-up level), the NCL30088 consumes a very low current (13 mA typically, 30 mA maximum). Thus, high-impedance, low dissipation, resistors can be used to charge the VCC capacitor at start-up. Note however, that faults like a VCC over-voltage condition lead the LED driver to stop operation and refrain from attempting to recover until a 4 s delay is elapsed. A low duty-ratio burst mode of operation is hence obtained as long as the fault is present. VCC cycles up and down in such a case. For this time, the (off-mode) consumption is slightly higher (75 mA max.). It is hence recommended to have the startup current (Istartup in Figure 7) above 75 mA. If not, VCC may collapse and the circuit reset before the 4 s delay has elapsed. As detailed in application note AND9131/D [2], the startup resistor Rstartup can either be connected to the bulk rail or to half-wave (Figure 7). Connecting the startup resistor to the half-wave allows decreasing the power dissipated in the startup resistor. VD AUX + V CC ) ǒnn AUX P @ Ǹ2 @ (V in,rms) HL Ǔ (eq. 44) The VCC highest value is the maximum voltage the VCC(OVP) threshold can take (28.5 V). Therefore: VD AUX + (V CC(OVP)) max ) ǒnn AUX P @ Ǹ2 @ (V in,rms) HL Ǔ (eq. 45) In our case: VD AUX + (V CC(OVP)) max ) ǒ ǒnn AUX P Ǔ Ǔ @ Ǹ2 @ (V in,rms) HL ^ ^ 28.5 ) 1 @ Ǹ2 @ 265 ^ 91 V 6 (eq. 46) Due to the turn on spike, some significant headroom is necessary. Selecting a diode exhibiting at least twice the computed VRRM value seems a good practice. A 250 V/0.2 A BAV21 diode is implemented in our application. www.onsemi.com 11 AND9200/D Figure 7. The Startup Resistor can be Connected to the Bulk Rail or to the Half Wave Calculating the VCC Capacitor output capacitor (no current flows through the LED string). treg lasts until the output voltage reaches the level at which VCC starts to be charged. In general, we try to minimize the CVcc capacitor by allowing a nearly maximal VCC capacitor discharge, that is, down to a value close to the UVLO level. At that moment, the output voltage will nearly be n V out + (V CC(off)) max n s and treg can then computed as aux follows: The VCC capacitor value (CVcc ) must be large enough to feed the controller until the auxiliary winding voltage Vaux is sufficiently large to supply the controller. The time duration where the controller is supplied by the only CVcc capacitor is noted treg (Figure 8). The circuit enters operation when the VCC capacitor is charged to the VCC(on) startup level. For the treg duration, the VCC capacitor must be able to maintain the VCC voltage above the UVLO level (VCC(off)) while providing the current consumed by the circuit (ICC2 specified in the data sheet) and the current necessary to drive the MOSFET. We can estimate treg by considering that for this period of time, all the LED driver output current is absorbed by the C Vcc w ǒ Ǔ t reg ^ ǒ C out n (V CC(off)) max n s aux I out Ǔ (eq. 47) Now, using the minimum value of the UVLO hysteresis (minimum value of VCC(on) − VCC(off)), the minimum VCC capacitor value comes: (I CC2 ) Q gf sw)t reg ) Q qf sw) (V CC(off)) max (I ns @ C ^ n out @ CC2 @ aux I out (V CC(HYS)) min (V CC(HYS)) min (eq. 48) • Qg is the MOSFET total gate charge • (VCC(HYS) )min is the UVLO hysteresis minimum value Where: • ICC2 is the NCL30088 consumption at 65 kHz when the DRV pin is unloaded (4 mA max) (8 V) Figure 8. VCC Waveform during Startup Once the VCC capacitor value is known, the start-up current needed to charge CVcc can be computed as a function of the maximum acceptable start-up time if specified. Recall anyway that this startup current should not be less than www.onsemi.com 12 AND9200/D 75 mA so that as explained at the beginning of this section, the circuit does not reset in fault mode. Hence: I startup + (V CC(on)) max C Vcc (V CC(on)) max C Vcc ) (I CC(start)) max if ) (I CC(start)) max w 75 mA t startup t startup (eq. 49) I startup + 75 mA otherwise Where: • (VCC(on) )max is the VCC startup threshold maximum value • (ICC(start) )max is the maximum value of the NCL30088 startup consumption (30 mA) • tstartup is the targeted startup time t reg ^ Ǔ (eq. 50) C Vcc w (I CC2 ) Q gf sw)t reg (4m ) 19n 65k)9m ^ ^ 6 mF 8 (V CC(HYS)) min (eq. 51) In our case, assuming a 19-nC gate charge MOSFET, a 65-kHz operation and a 0.5-s target for the startup time, it comes: (Eq. 50 and Eq. 51) I startup + ǒ 470 mF C out n (V CC(off)) max n s + (9.4 @ 1) ^ 9 ms aux I out 500 mA We will select a 10 mF/35 V capacitor. Hence: (V CC(on)) max C Vcc 20 @ 10m ) (I CC(start)) max ^ ) 30m + 430 mA w 75 mA t startup 0.5 Startup Resistor Calculation P startup + Bulk Connection For start-up time, the bulk rail sees the line peak voltage (the input voltage becomes a rectified sinusoid when the LED driver starts to operate), the following formula gives the Rstartup value: Ǹ2 @ (V in,rms) LL R startup + I startup ǒǸ2 @ (Vin,rms) HL*VCCǓ (eq. 52) 2 v R startup 2 @ (V in,rms) HL R startup 2 (eq. 54) Where (Vin,rms )HL is the highest line rms voltage. Half-wave Connection If the resistor is connected to the half-wave: (eq. 53) Ǹ2@(V in,rms) LL R startup1ń2 + Where: • Istartup is the startup current • (Vin,rms )LL is the lowest line rms voltage p I Cvcc ) I CC(start) + R startup p (eq. 55) The maximum power dissipated by the startup resistor connected to the half-wave is thus: The maximum power dissipated by the startup resistor connected to the bulk rail is: P startup1ń2 + ǒ Ǹ2@(V ) in,rms HL *V CC p Ǔ 2 R startup1ń2 R startup1ń2 + p I startup + 90Ǹ2 p 430m 2 (eq. 56) p In Our Application: We selected the half-wave configuration. Since we have computed that the startup current had to be 430 mA or more, we can deduce: (V in,rms) LL Ǹ2 2 (V in,rms) HL (V in,rms) HL v 22 R +2 p R startup p startup P startup1ń2 v ǒ (V Ǹ2 ) in,rms HL p R startup1ń2 Ǔ 2 + ǒ 265Ǹ2 p 94 Ǔ 2 k ^ 151 mW (eq. 58) Three 33-kW, 1/4 W resistors are placed in series. ^ 94 kW (eq. 57) The power dissipated for the startup resistor at maximum input voltage is: www.onsemi.com 13 AND9200/D ZCD Network I ZCD,dmg + RZCD1 of Figure 2 limits: • The current injected into the ZCD pin during the demagnetization time. As indicated in the data sheet, this current must remain below 5 mA. • The current extracted from the ZCD pin during the on-time. This current must not exceed 2 mA. R ZCD1 v 5mA (eq. 60) Where VCC(OVP)max is the VCC maximum value for VCC OVP protection tripping (28.5 V). For optimal output current regulation, it is recommended to keep the ZCD pin voltage below 5 V. This is the goal of RZCD2 of Figure 2. R ZCD2 (V CC,max ) V f) v 5V R ZCD1 ) R ZCD2 During the on-time, the ZCD pin current is maximal at the highest line voltage: Ǹ2 @ (V n in,rms) HL I ZCD,on + naux v 2mA R ZCD1 P V CC(OVP)max ) V f (eq. 61) Where VCC,max is the maximal VCC voltage in normal operation (20 V in our application). Finally, this resistor together with the CZCD capacitor delays the zero-voltage crossing event and helps to tune the turn-on instant when the drain voltage is in the valley. Finally: (see Table 4) (eq. 59) During the demagnetization time, the auxiliary winding voltage is maximal when VCC is at its maximum value, that is, the OVP level. Hence: Table 4. CVCC Rstartup1/2 Rstartup DAUX RZCD1 / RZCD2 CZCD 10 mF / 35 V three 33 kW, 1/4 W resistors in series N/A BAV21 33 kW / 10 kW 22 pF DETAILED SCHEMATIC FOR OUR 10 W, UNIVERSAL MAINS LED DRIVER Figure 9. Application Schematic www.onsemi.com 14 AND9200/D EXPERIMENTAL DATA Output Current Regulation Figure 10 shows the output current as a percentage of its nominal value. We can see that its characteristic is very flat with respect to the temperature. Thermal Foldback starts at about 80°C. As a result, the output current linearly decays to reach 50% of its nominal value at nearly 92°C. The circuit stops operating (SD pin Over Temperature Protection) at approximately 105°C and resumes operation when the temperature drops down to about 90°C. These temperature thresholds depend on the thermistor connected to the SD pin. Below characteristics were obtained with a NB12P00104JBB thermistor manufactured by AVX. 110 100 90 Iout / Iout,nom (%) 80 Start of Thermal Foldback 70 60 50 40 30 SD pin OTP activation 115 Vrms 230 Vrms 20 10 0 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (°C) Figure 10. LED Current Characteristics over the Temperature Range Power Factor Figure 11 shows the power factor measured at two different line magnitudes (115 V rms and 230 V rms). The power factor is extremely stable over the considered temperature range from −40°C to 80°C. Above 80°C, the performance is affected by the thermal foldback which reduces the output current. 1.05 1.00 0.95 PF (−) 0.90 0.85 0.80 0.75 Thermal Foldback and SD pin OTP 0.70 0.65 115 Vrms 230 Vrms 0.60 0.55 0.50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (°C) Figure 11. Power Factor Performance over the Temperature Range www.onsemi.com 15 AND9200/D Fault Situations The NCL30088 incorporates a large suite of protections. Next figures illustrate the circuit capability to address shorted/open situations of the LED string or an output diode failure. Tests have been made with the B version (NCL30088B). Application note AND9204/D discusses in details the NCL30088 behavior under safety tests [4]. VCC VRsense Iline (100 mA/div) Open LED String Situation The LED string being disconnected, the VCC voltage rises and the VCC(OVP) protection trips when VCC exceeds 26.8 V (typically). At that moment, the circuit stops operating for the 4-s auto-recovery delay. The LED driver recovers normal operation when the LEDs are again connected. Figure 12. Current Waveform at 115 V rms VCC The LED string is disconnected Iout (0.5 A/DIV) Figure 13. The System Enters a Safe Low Duty-ratio Burst Mode when the LED String is Disconnected (the LED Driver is Unloaded for about 15 s for this Test) LED String Short Situation In the case of Figure 13, the only VCC(OVP) protection is in play. Note that a Zener diode could have been placed between the VCC and SD pins to select a lower VCC threshold for fault detection (see the SD pin OVP function in the NCL30088 data sheet). Further note that if the VCC(OVP) protection is auto-recovery in all NCL30088 versions, the SD pin OVP can be a latching-off (NCL30088A or NCL30088C) or an auto-recovery (NCL30088B or NCL30088D) protection. As illustrated by Figure 14, if the output is shorted, the AUX_SCP protection makes the LED driver enters a safe, low duty-ratio burst mode. Normal operation is recovered when the short is removed. The same behavior would be obtained with the D version. Note that the NCL30088A and NCL30088C latch off when an output short is detected. No recovery is hence possible with these versions until the LED driver is unplugged and VCC drops below VCC(reset) . At that moment, the fault is cleared and the circuit can resume operation. www.onsemi.com 16 AND9200/D VCC Iout (0.5 A/DIV) The output is shorted Figure 14. The System Enters a Safe Low Duty-ratio Burst Mode when the Output is Shorted (the LED Driver Output is Shorted for about 10 s for this Test) Output Diode Short The LED driver stops operation as soon as 4 faulty DRV pulses are detected (see Figure 16). In this situation, the NCL30088B and NCL30088D attempt to resume operation when the 4-s auto-recovery delay is elapsed. The NCL30088A and NCL30088C remain latched off until the system is reset. Iout (500 mA/div) VCC VDS Rsense voltage Figure 15. NCL30088B Operation when the Output Diode is Shorted www.onsemi.com 17 AND9200/D Iout (500 mA/div) VCC VDS Rsense Voltage Figure 16. The Winding or Output Diode Short Circuit Protection (WODSCP) Trips as soon as 4 Consecutive Faulty DRV Pulses are Detected REFERENCES [3] Stéphanie Cannenterre, Understanding sources of LED current deviations… [4] Joel Turchi, “NCL30088 and NCL30085 Safety Tests Consideration”, Application Note http://www.onsemi.com/pub_link/Collateral/ AND9204−D.PDF [1] NCL30088 Data Sheet, http://www.onsemi.com/pub_link/Collateral/ NCL30088−D.PDF [2] Stéphanie Cannenterre, Application Note AND9131/D, Designing a LED Driver with the NCL30080/81/82/83, http://www.onsemi.com/pub_link/Collateral/ AND9131−D.PDF ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 18 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AND9200/D