Ordering number: ENA0907B LV8013T Bi-CMOS IC Forward/Reverse Motor Driver http://onsemi.com Overview LV8013T is a 1ch forward/reverse motor driver IC using D-MOS FET for output stage. As MOS circuit is used, it supports the PWM input. Its features are that the on resistance (0.3Ω typ) and current dissipation are low. It also provides protection functions such as heat protection circuit and reduced voltage detection and is optimal for the motors that need high-current. Functions • 1ch forward/reverse motor driver • Possible to respond to 3V control voltage and 6V motor voltage device • Low power consumption • Low ON resistance 0.5Ω • Built-in charge pump circuit • Built-in low voltage reset and thermal shutdown circuit • Four mode function forward/reverse, brake, stop. Specifications Maximum Ratings at Ta = 25°C, SGND = PGND = 0V Parameter Symbol Conditions Ratings Unit Supply voltage (For load) VM max -0.5 to 16 V Supply voltage (For control) VCC max -0.5 to 6.0 V Output current IO max DC 1.2 A IO peak1 t ≤ 100ms, f = 5Hz 2.0 A IO peak2 t ≤ 10ms, f = 5Hz 3.8 A -0.5 to VCC+0.5 V Input voltage VIN max Allowable power dissipation Pd max Operating temperature Topr -20 to +75 °C Storage temperature Tstg -55 to +150 °C Mounted on a specified board * 800 mW *Specified board: 30mm × 50mm × 1.6mm, glass epoxy board. Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time. Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 May, 2013 71812 SY/N2608 MS / 80107 MS PC B8-9208 No.A0907-1/6 LV8013T Allowable Operating Conditions at Ta = 25°C, SGND = PGND = 0V Parameter Symbol Conditions Ratings Unit Supply voltage (For load) VM 2.0 to 15.0 Supply voltage (For control) VCC 2.7 to 5.5 V Input signal voltage VIN 0 to VCC V Input signal frequency f max Capacitor for charge pump C1, C2, Duty = 50% V 200 kHz 0.001 to 0.1 μF CVG1, CVG2 Electrical Characteristics at Ta = 25°C, VCC = 5.0V, VM = 12.0V, SGND = PGND = 0V, unless especially specified. Parameter Supply current for load at Symbol Conditions Ratings Remarks min typ Unit max IM1 EN = 0V 1 1.0 μA IM2 VCC = 0V, Each input = 0V 1 1.0 μA ICO EN = 0V, IN1 = IN2 = 0V 2 25 50 μA standby 1 Supply current for load at standby 2 Supply current for control at 12.5 standby Current drain during operation 1 IC1 VCC = 3.3V, EN = 3.3V, VG at no load 3 0.6 1.0 mA Current drain during operation 2 IC2 VCC = 5.0V, EN = 5V, VG at no load 3 0.7 1.2 mA H-level input voltage VIH 2.7V ≤ VCC ≤ 5.5V L-level input voltage VIL 2.7V ≤ VCC ≤ 5.5V H-level input current IIH VIN = 5V 4 12.5 IIL VIN = 0V 4 -1.0 0.6×VCC VCC 0 25 V 0.2×VCC V 50 μA (IN1, IN2, TIN) L-level input current μA (IN1, IN2, TIN) Pull-up resistance (EN) RUP 4 100 200 400 kΩ Pull-down resistance RDN 4 100 200 400 kΩ 0.3 0.5 Ω (EN) Output ON resistance RON Sum of ON resistances at top and 5 bottom Charge pump voltage1 VG1 VCC×2 - 5.4V CLAMP circuit 6 5.15 5.4 5.65 V Charge pump voltage2 VG2 VM + VG1 Voltage raising circuit 6 17.1 17.4 17.6 V Low-voltage detection operation VCS VCC voltage 7 2.1 2.25 2.4 V Tth Design guarantee 8 150 180 210 °C Charge pump capacity 1 VG1LOAD IG1 = 500μA 9 5.0 5.3 Charge pump capacity 2 VG2LOAD IG2 = 500μA 9 16.0 16.5 IG current dissipation IG voltage Thermal shutdown operation temperature 10 V V 350 μA (Fin = 20kHz) Charge pump start time TVG Output TPLH Turn on time CVG = 0.1μF 11 12 1.0 ms 0.5 1.0 μs block Turn off time TPHL 12 0.5 1.0 μs TOUT Turn on time TON C = 500pF 12 0.5 20 μs Turn off time TOFF C = 500pF 12 0.5 20 μs TOUT output voltage H TOH C = 500pF TOUT output voltage L TOL C = 500pF VG2-0.1 VG2 0.05 V 0.1 V * Design guarantee : This characteristics is not measured. Refer to next page for remarks. No.A0907-2/6 LV8013T Remarks 1. It shows current dissipation of VM pin in output OFF state. 2. It shows current dissipation of VCC pin in stand-by state. (The standard current depends on EN pin pull-down resistor.) 3. It shows current dissipation of VCC pin in state of EN = 5V (stand-by), including current dissipation of VG pin. 4. IN1, IN2 and TIN pin are built-in pull-down resistor, EN pin is built-in pull-up resistor. 5. It shows sum of upper and lower saturation voltages of OUT pin. 6. It controls charge-pump oscillation and makes specified voltage. 7. When low voltage is detected, the lower output is turned OFF. 8. When thermal protection circuit is activated, the lower output is turned OFF. When the heat temperature is fallen, it is turned ON again. 9. IG (VG pin load current) = 500μA 10. It shows VG pin current dissipation in state of PWM input for IN pin. 11. It specifies start-up time from 10% to 90% when VG is in non-load state (when setting the capacitor between VG and GND to 0.1μF and VCC is 5V). 12. It specifies 10% to 90% for start-up and 90% to 10% for shut-down. Package Dimensions unit : mm (typ) 3260A Pd max -- Ta Allowable power dissipation, Pd max -- mW 1000 6.5 0.5 6.4 13 4.4 24 12 1 0.5 0.15 0.22 1.2max (1.0) (0.5) Specified board: 30×50×1.6mm3 glass epoxy board. 800 600 480 400 200 0 -20 0 20 40 60 75 80 100 0.08 Ambient temperature, Ta -- °C SANYO : TSSOP24(225mil) VG2 VM OUT2 OUT2 NC PGND PGND NC NC OUT1 OUT1 VM Pin Assignment 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 SGND C2H C2L VG1 C1H C1L VCC IN1 IN2 EN TIN TOUT LV8013T Top view No.A0907-3/6 LV8013T Block Diagram CH2 VG1 OSC,CHARGE_PUMP CL2 VG2 CH1 Low-voltage thermal protection CL1 TOUT OUT1 LEVEL SHIFTER VM VCC IN1 CMOS LOGIC IN2 OUT2 PGND TIN Deffused resistor EN SGND Truth Table EN H L IN1 IN2 TIN OUT1 OUT2 TOUT H H - L L - H L - H L - Forward L H - L H - Reverse L L - Z Z - Standby Tr-OFF - - L - - L - - H - - H - - - L L L Charge Pump Mode Brake ON Tr-ON OFF Standby - : Don’t care, Z : High-Impedance · Current drain becomes zero in the standby mode. (Leak current from EN pin is excluded) · The output side becomes OFF, with motor drive stopped, during voltage reduction and thermal protection. Also, the charge of VG2 is discharged with an internal circuit at decreasing voltage. Pin Function Pin No. Pin name 6 C1L Function Equivalent circuit Voltage raising capacitor connection pin. VCC C1L 5 C1H Voltage raising capacitor connection pin. VG1 C1H 8 IN1 9 IN2 11 TIN · Driver output changeover. VCC · TOUT output control pin. (Built-in pull-down resistor) 200kΩ Continued on next page. No.A0907-4/6 LV8013T Continued from preceding page. Pin No. Pin name 10 EN Function Equivalent circuit Logic enable pin. VCC (Built-in pull-up resistor) 200kΩ 14 OUT1 15 OUT1 21 OUT2 22 OUT2 18 PGND 19 PGND Driver output pin. VM OUT1 OUT2 PGND 12 TOUT Voltage raising output pin. 13 VM 23 VM Motor power supply. (both terminals to be connected) 7 VCC Logic power supply. 4 VG1 VG2 Voltage raising circuit 1. VG1 VCC × 2 Clamped to 5.4V 0.1μF C1H 0.01μF C1L 24 VG2 2 C2H 3 C2L · Voltage raising circuit 2. VM + VG1 VM VG2 · Voltage raising capacitor connection pin. 0.1μF VG2 is discharged in abnormal. C2H 0.01μF C2L 1 SGND Logic GND 18 PGND Driver GND 19 PGND (both terminals to be connected) No.A0907-5/6 LV8013T Application Circuit Example C2H VG2 CVG2 =0.1μF C2=0.01μF C2L TOUT CVG1=0.1μF VG1 VM 2.7V to 5.5V C2H *1 C1=0.01μF 2.7V to 5.5V C2L OUT2 VCC OUT2 IN1 PGND IN2 PGND EN OUT1 TIN OUT1 M CPU SGND VM *1 : Connect a kickback absorption capacitor directly near IC. Coil kick-back may cause rise of the voltage of VM line, and the voltage exceeding the maximum rating may be applied momentarily, resulting in deterioration or damage of IC. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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