LC898217XC D

LC898217XC
Auto Focus (AF) Controller & Driver
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1. Overview
LC898217XC is an AF control LSI. It consists of 1 system of
feedback circuit for AF control. Built-in equalizer circuit using
digital operation. Built-in A/D converter, D/A converter, Constant
Crrent Driver. This is suitable for small & thinner camera module.
2. Features
 Built-in equalizer circuit using digital operation
- AF control equalize circuit
- Any coefficient can be specified by 2-wire serial I/F (TWIF)
 2-wire serial interface
(The communication protocol is compatible with I2C.)
WLCSP10, 1.04x2.04
 Built-in A/D converter
- 11-bit
- Input 1 channel
 Built-in D/A converter
- 8-bit
- Output 2-channel (Hall offset, Constant current bias)
 Built-in VGA
- Hall Amp
- 1 channel
 Built-in EEPROM
- 128byte (16byte/page)
 Built-in OSC
- 24MHz
■ Built-in Constant Current Driver
- 10-bit, 110mA
- 1-channel
 Package
- WL-CSP 10-pin
- Pb-Free, Halogen Free
 Supply voltage
- VDD (2.6V to 3.3V)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
February 2016 - Rev. 0
1
Publication Order Number :
LC898217XC/D
LC898217XC
3. Pin Description
I
O
B
INPUT
OUTPUT
BIDIRECTION
P
TYPE
Power supply, GND
NC
 2-wire serial interface
SCL
I
SDA
B
2-wire serial interface clock pin
2-wire serial interface data pin
 Hall interface
BIASO
OPINP
OPINM
O
I
I
D/A output (to Hall element)
VGA input (from Hall element)
VGA input (from Hall element)
 Driver interface
OUT1
O
Driver output (to Actuator)
O
Driver output (to Actuator)
 Power supply pin
VDD
VSS
P
P
Power supply
GND
 Test pin
PORT
B
OUT2
NOT CONNECT
Analog test signal input/output
Convergence detection monitor output
VSYNC input
* Process when pins are not used
PIN TYPE “O” – Ensure that it is set to OPEN.
PIN TYPE “I” – OPEN is inhibited. Ensure that it is connected to the VDD or VSS even when it is unused.
(Please contact ON Semiconductor for more information about selection of VDD or VSS.)
PIN TYPE “B” – If you are unsure about processing method on the pin description of pin layout table, please contact us.
Note that incorrect processing of unused pins may result in defects.
* In case of connecting PORT pin with HOST CPU
When LC898217 is power off and HOST CPU is power on, a HOST CPU pin connected with PORT pin have to be fixed
"L" level.
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LC898217XC
4. Pin Layout
Circuit Name
Number of PINs
Circuit Name
Number of PINs
Analog
4
Driver
2
Logic
2
Power
2
“PORT” pin has analog function and digital function.
BOTTOM VIEW
A
B
1
OUT2
OUT1
2
VSS
VDD
3
PORT
SCL
4
BIASO
SDA
5
OPINM OPINP
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LC898217XC
5. Block Diagram
SDA
SCL
2-Wire Serial
I/F
EEPROM
Hall
Driver
+
BIASO
DA
Adjustment
& Measurement
Circuit
DA
+
-
Constant
Current
Driver
OUT1
OUT2
OPINP
OPINM
+
-
ch1
ch2
AD
Control
logic
EQ
OUT1
OUT2
VDD
Logic OUT
Logic IN
Hall
OSC
POR
2.2uF
LDO
VSS
PORT
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LC898217XC
6. Package Dimensions
unit : mm
WLCSP10, 1.04x2.04
CASE 567LF
ISSUE B
E
PIN A1
REFERENCE
NOTE 4
BACKSIDE
COATING
D
0.05 C
2X
0.05 C
2X
DETAIL A
0.08 C
C
SIDE VIEW
e
0.03 C
DIM
A
A1
A3
b
D
E
e
DETAIL A
A
A1
NOTE 3
MILLIMETERS
MIN
MAX
0.27
0.33
0.04 REF
0.025 REF
0.12
0.22
1.04 BSC
2.04 BSC
0.40 BSC
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
PACKAGE
OUTLINE
A1
e/2
b
0.05 C A B
A3
TOP VIEW
0.10 C
10X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
4. BACKSIDE COATING IS OPTIONAL.
A B
0.40
PITCH
e
B
10X
A
0.40
PITCH
1
2
3
4
0.17
DIMENSIONS: MILLIMETERS
5
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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LC898217XC
7. Electrical Characteristics
1) Absolute Maximum Rating at VSS=0V
Item
Supply voltage
Input/output voltage
Storage ambient
temperature
Operating ambient
temperature
Symbol
VDD33 max
VI33, VO33
Condition
Ta ≤ 25°C
Rating
0.3 to 4.6
0.3 to VDD33+0.3
Ta ≤ 25°C
Tstg
55 to 125
Topr
30 to 70
Unit
V
V
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
2) Allowable Operating Ratings at Ta=30 to 70C, VSS=0V
3V power supply (VDD)
Item
Supply voltage
Input voltage range
Symbol
VDD33
VIN
Min
2.6
0
Typ
2.8
Max
3.3
VDD33
Unit
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
3) DC Characteristics : Input/Output level at VSS= 0V, VDD=2.6 to 3.6V, Ta =30 to 70C
Item
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Pulldown resistor
Symbol
VIH
VIL
VOH
VOL
Rdn
Condition
CMOS
compliant
Schmidt
IOL=2mA
IOL= 2mA
Min
1.4
Typ
Max
0.4
Unit
V
V
SCL, SDA,
PORT
0.4
220
V
V
kΩ
PORT
SDA, PORT
PORT
VDD0.4
50
Applicable pins
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
4) Driver output (OUT1, OUT2) at VSS= 0V, VDD= 2.8V, Ta = 25°C
Item
Maximum current
Output ON resistance
Symbol
Condition
Min
Ifull
Ronu
Compliance voltage
Vcomp
Output leak current
Ioleak
Typ
Max
105
Io=110mA
Pch
115
Unit
mA
1.4
Ω
1
A
0.5
Applicable pins
OUT1, OUT2
V
5) Non-volatile Memory Characteristics
Item
Endurance
Data retention
Write time
Symbol
EN
RT
Condition
Min
Typ
Max
1000
10
tWT
20
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Unit
Cycles
Years
ms
Applicable circuit
EEPROM
LC898217XC
8. AC Characteristics
8.1 VDD supply timing
Figure 8.1 VDD supply timing
It is available to use 2-wire serial interface 5ms later for Power On Reset of VDD.
Item
VDD turn on time
2-wire serial interface start time
from VDD on
VDD off time
Bottom Voltage
Symbol
t1
Min
t2
5
t3
Vbot
100
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Typ
Max
3
Unit
ms
ms
0.1
ms
V
LC898217XC
8.2 AC specification
Figure 8.2 shows interface timing definition and Table 8.1 shows electric characteristics.
Figure 8.2 2-wire serial interface timing definition
Table 8.1 Electric characteritics for 2-wire serial interface (AC characteristics)
Item
SCL clock frequency
START condition
hold time
SCL clock
Low period
SCL clock
High period
Setup time for
START condition
repetition
FSCL
SCL
tHD,STA
SCL
SDA
0.6
0.26
s
tLOW
SCL
1.3
0.5
s
tHIGH
SCL
0.6
0.26
s
0.6
0.26
s
0 (*3)
s
50
ns
tSU,STA
tHD,DAT
Data setup time
tSU,DAT
STOP condition setup time
Bus free time between STOP
and START
Fast-mode Plus
Pin
name
Data hold time
SDA, SCL
rising time
SDA, SCL
falling time
Fast-mode
Symbol
tr
tf
tSU,STO
tBUF
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
Min
Typ
Max
Min
400
0 (*3)
0.9
100
Typ
Max
1000
Units
kHz
300
120
ns
300
120
ns
0.6
0.26
s
1.3
0.5
s
*3: LC898217XC is designed for a condition with typ. 20ns of hold time. If SDA signal is unstable around falling point of SCL
signal, please implement an appropriate treatment on board, such as inserting a resistor.
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LC898217XC
ORDERING INFORMATION
Device
LC898217XC-MH
Package
Shipping (Qty / Packing)
WLCSP10, 1.04x2.04
(Pb-Free / Halogen Free)
4000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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