ENA0604 D

Ordering number : ENA0604
LB11921T
Monolithic Digital IC
Three-Phase Brushless Motor Driver
http://onsemi.com
Overview
The LB11921T is a pre-driver IC designed for variable-speed control of 3-phase brushless motors. It can be used to
implement a motor drive circuit with the desired output capacity (voltage, current) by using discrete transistors for
the output stage. It implements direct PWM drive for minimal power loss. Since the LB11921T includes a built-in
VCO circuit, applications can control the motor speed arbitrarily by varying the external clock frequency.
Functions
• Direct PWM drive output
• Speed discriminator + PLL speed control circuit
• Speed lock detection output
• Built-in VCO circuit
• Forward/reverse switching circuit
• Braking circuit (short braking)
• Full complement of on-chip protection circuits, including lock protection, current limiter, and thermal shutdown
protection circuits.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Output current
Symbol
Conditions
VCC max
IO max
Ratings
Unit
8
V
UH, VH, WH, UL, VL, WL output
10
mA
W
Allowable power dissipation 1
Pd max1
Independent IC
0.4
Allowable power dissipation 2
Pd max2
Mounted on a circuit board*
0.9
W
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
* Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
11707 MS IM 20060327-S00010 No.A0604-1/18
LB11921T
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
FG Schmitt output applied voltage
VFGS
0 to 7
V
FG Schmitt output current
IFGS
0 to 5
mA
Lock detection applied voltage
VLD
0 to 7
V
Lock detection output current
ILD
0 to 20
mA
Supply voltage
VCC
4.4 to 7.0
V
Electrical Characteristics at Ta = 25°C, VCC = 5V
Parameter
Symbol
Ratings
Conditions
min
Supply current 1
ICC1
Supply current 2
ICC2
unit
typ
max
23
32
mA
In stop mode
2.1
2.9
mA
Output Block
Output saturation voltage 1-1
VOsat1-1
At low level: IO = 500μA
0.1
0.2
V
Output saturation voltage 1-2
VOsat1-2
At low level: IO = 5mA
0.3
0.5
V
Output saturation voltage 2-1
VOsat2-1
At high level: IO = -500μA
VCC-0.2
VCC-0.1
V
Output saturation voltage 2-2
VOsat2-2
At high level: IO = -5mA
VCC-0.4
VCC-0.2
V
-2
-0.1
μA
Hall Amplifier
Input bias current
IHB(HA)
Common-mode input voltage range 1
VICM1
When Hall-effect sensors are used
Common-mode input voltage range 2
VICM2
When one-side biased inputs are used
0.5
VCC-2.0
VCC
0
V
V
(Hall-effect IC applications)
Hall input sensitivity
Sine wave
50
mVp-p
ΔVIN(HA)
9
15
26
mV
Input voltage low → high
VSLH
4
7
13
mV
Input voltage high → low
VSHL
-13
-8
-4
mV
Hysteresis
PWM Oscillator
Output high-level voltage
VOH(PWM)
2.75
3.0
3.25
V
Output low-level voltage
VOL(PWM)
1.45
1.65
1.9
V
Oscillator frequency
f(PWM)
Amplitude
V(PWM)
C = 680pF
1.1
1.35
1.6
Vp-p
Output high-level voltage
VOH(CSD)
3.15
3.5
3.85
V
Output low-level voltage
VOL(CSD)
0.9
1.1
1.3
V
External capacitor charge current
ICHG1
-9.0
-6.5
-3.9
μA
External capacitor discharge current
ICHG2
2.4
4.0
6.0
μA
23
kHz
CSD Oscillator
Oscillator frequency
f(RK)
C = 0.047μF
Amplitude
V(RK)
2.1
2.4
2.65
Vp-p
Output high-level voltage
VOH(C)
2.00
2.30
2.55
V
Output low-level voltage
VOL(C)
1.55
1.80
2.05
V
1.2
MHz
0.7
Vp-p
20
Hz
VCO Oscillator C pin
Oscillator frequency
f(C)
Amplitude
V(C)
0.3
0.5
Continued on next page.
No.A0604-2/18
LB11921T
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
unit
max
Current Limiter Operation
Limiter
VRF
0.24
0.26
0.28
V
150
180
°C
30
°C
Thermal Shutdown Operation
Thermal shutdown operating
TSD
Design target value *
ΔTSD
Design target value *
temperature
Hysteresis
Low-voltage Protection Circuit
Operating voltage
VSDL
Release voltage
VSDH
3.55
3.93
4.23
V
Hysteresis
ΔVSD
0.12
0.19
0.26
V
VIO(FG)
-10
3.40
3.74
4.00
V
FG Amplifier
Input offset voltage
Input bias current
IB(FG)
-1
10
mV
1
μA
Output high-level voltage
VOH(FG)
IFGI = -0.1mA, No load
3.6
3.95
4.3
V
Output low-level voltage
VOL(FG)
IFGI = 0.1mA, No load
0.7
1.05
1.4
V
180
250
mV
2.34
kHz
FG input sensitivity
Gain: 100×
Schmitt amplitude for the next stage
3
100
mV
Operating frequency range
Open-loop gain
Reference voltage
f(FG) = 2kHz
VB(FG)
45
51
-5%
VCC/2
5%
dB
0.2
0.4
V
10
μA
1.1
V
V
FGS Output
Output saturation voltage
Output leakage current
VO(FGS)
IL(FGS)
IO(FGS) =2mA
VO = VCC
Speed Discriminator Output
Output high-level voltage
VOH(D)
Output low-level voltage
VOL(D)
VCC-1.0
VCC-0.7
0.8
Counts
V
512
Speed Control PLL Output
Output high-level voltage
VOH(P)
3.25
3.50
3.85
V
Output low-level voltage
VOL(P)
1.25
1.60
1.85
V
0.25
0.4
V
10
μA
+6.25
%
Lock Detection
Output saturation voltage
Output leakage current
VOL(LD)
IL(LD)
ILD = 10mA
VO = VCC
Lock range
-6.25
Integrator
Input offset voltage
Input bias current
VIO(INT)
-10
10
mV
IB(INT)
-0.4
0.4
μA
V
Output high-level voltage
VOH(INT)
IINTI = -0.1mA, No load
3.45
3.7
3.95
Output low-level voltage
VOL(INT)
IINT = 0.1mA, No load
1.1
1.3
1.5
45
51
-5%
VCC/2
Open-loop gain
Gain-bandwidth product
Reference voltage
Design target value *
VB(INT)
*: Design target value and no measurement was made.
V
dB
1.0
MHz
5%
V
Continued on next page.
No.A0604-3/18
LB11921T
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
unit
typ
max
FIL Output
Output source current
IOH(FIL)
-17
-13
-7
μA
Output sink current
IOL(FIL)
7
12
17
μA
Input high-level voltage
VIH(S/S)
2.0
VCC
V
Input low-level voltage
VIL(S/S)
0
1.0
V
Input open voltage
VIO(S/S)
VCC-0.5
VCC
V
Hysteresis
ΔVIN(S/S)
0.13
0.22
0.31
V
Input high-level current
IIH(S/S)
VS/S = VCC
10
Input low-level current
IIL(S/S)
VS/S = 0V
Pull-up resistance
S/S Pin
μA
-10
0
-135
-93
RU(S/S)
37
53.5
Input high-level voltage
VIH(F/R)
2.0
VCC
V
Input low-level voltage
VIL(F/R)
0
1.0
V
Input open voltage
VIO(F/R)
VCC-0.5
VCC
V
Hysteresis
ΔVIN(F/R)
Input high-level current
IIH(F/R)
VF/R = VCC
Input low-level current
IIL(F/R)
VF/R = 0V
Pull-up resistance
RU(F/R)
Input high-level voltage
VIH(BR)
2.0
Input low-level voltage
VIL(BR)
Input open voltage
VIO(BR)
Hysteresis
ΔVIN(BR)
0.13
μA
70
kΩ
F/R Pin
0.13
0.22
0.31
V
-10
0
10
μA
-135
-93
37
53.5
μA
70
kΩ
VCC
V
0
1.0
V
VCC-0.5
VCC
V
0.22
0.31
V
10
μA
70
kΩ
BR Pin
Input high-level
IIH(BR)
VBR = VCC
Input low-level current
IIL(BR)
VBR = 0V
Pull-up resistance
-10
0
-135
-93
RU(BR)
37
53.5
Input high-level voltage
VIH(CLK)
2.0
VCC
V
Input low-level voltage
VIL(CLK)
0
1.0
V
VCC-0.5
VCC
V
μA
CLK Pin
Input open voltage
VIO(CLK)
Hysteresis
ΔVIN(CLK)
Design target value *
Input high-level current
IIH(CLK)
VCLK = VCC
Input low-level current
IIL(CLK)
VCLK = 0V
Input frequency
Pull-up resistance
0.13
0.22
0.31
V
-10
0
10
μA
-135
-93
37
53.5
f(CLK)
RU(CLK)
μA
2.34
kHz
70
kΩ
*: Design target value and no measurement was made.
No.A0604-4/18
LB11921T
Package Dimensions
unit : mm (typ)
3253B
Allowable Power Dissipation, Pd max - W
0.5
5.6
7.6
19
36
1
18
0.15
0.18
Mounted on a specified board:
114.3mm×76.1mm×1.6mm, glass epoxy
1.0
0.9
0.8
0.6
0.504
Independent IC
0.4
0.224
0.2
0.08
(1.0)
(0.63)
1.2max
(0.5)
Pd max - Ta
1.2
9.75
0
-20
0
20
40
60
80
Ambient Temperature, Ta -°C
100
ILB01797
SANYO : TSSOP36(275mil)
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
VCC
WH
WL
VH
VL
UH
UL
GND
RF
RFGND
FGIN+
FGIN-
Pin Assignment
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
F/R
BR
FGS
LD
DOUT
POUT
INT.REF
INT.IN
INT.OUT
PWM
FIL
R
C
CSD
NC
18
FGOUT
1
S/S
LB11921T
Top view
Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN–.)
F/R=L
F/R=H
Output
IN1
IN2
IN3
IN1
IN2
IN3
PWM
-
1
H
L
H
L
H
L
VH
UL
2
H
L
L
L
H
H
WH
UL
3
H
H
L
L
L
H
WH
VL
4
L
H
L
H
L
H
UH
VL
5
L
H
H
H
L
L
UH
WL
6
L
L
H
H
H
L
VH
WL
No.A0604-5/18
LB11921T
IN3-
IN3+
IN1IN2+
IN2-
CSD
IN1+
Block Diagram
VCC
HALL
HYS
AMP
CSD
OSC
WH
VH
LOGIC
PRI
DRIVER
F/R
F/R
UH
WL
VL
UL
LOGIC
BR
BR
TSD
S/S
RES
RF
INT
OUT
COMP
+
RFGND
-
INT
IN
CURR
LIM
S/S
1.3VREF
VCC
LVSD
INT
REF
PWM
OSC
PWM
POUT
LD
LD
SPEED
DISCRI
DOUT
SPEED
PLL
1/512
FG
FILTER
FGS
R
VCO
PLL
VCO
C
-
+
FIL
FGOUT
CLK
FIL
+
-
VCC
CLK
FGIN+
FGIN-
GND
No.A0604-6/18
LB11921T
Pin Functions
Pin No.
Symbol
1
S/S
Pin Description
Start/stop control
Equivalent Circuit
VCC
Low: 0V to 1.0V
50kΩ
High: 2.0V to VCC
Goes high when left open.
Low for start.
3.5kΩ
The hysteresis is about 0.22V
1
2
CLK
External clock signal input
Low: 0V to 1.0V
VCC
50kΩ
High: 2.0V to VCC
Goes high when left open.
The hysteresis is about 0.22V.
f = 2.34kHz, maximum
3.5kΩ
2
3
F/R
Forward/reverse control
Low: 0V to 1.0V
VCC
High: 2.0V to VCC
50kΩ
Goes high when left open.
Low for forward.
The hysteresis is about 0.22V.
3.5kΩ
3
BR
Brake pin (short braking operation)
Low: 0V to 1.0V
VCC
High: 2.0V to VCC
Goes high when left open.
High or open for brake mode operation.
The hysteresis is about 0.22V.
50kΩ
4
3.5kΩ
4
Continued on next page.
No.A0604-7/18
LB11921T
Continued from preceding page.
Pin No.
Symbol
5
FGS
Pin Description
Equivalent Circuit
FG schmitt comparator circuit output
VCC
This is an open collector output.
5
6
LD
Speed lock detection output
VCC
Goes low when the motor speed is within the
speed lock range (±6.25%).
6
7
DOUT
Speed discriminator output
V CC
Acceleration → high, deceleration → low
7
8
POUT
Speed control system PLL output
VCC
Outputs the phase comparison result for CLK and
FG.
8
Integrating amplifier non-inverting input
(1/2 VCC potential)
10
INT IN
VCC
Integrating amplifier inverting input
30kΩ
INT REF
500Ω
9
500Ω
10
30kΩ
9
Continued on next page.
No.A0604-8/18
LB11921T
Continued from preceding page.
Pin No.
Symbol
11
INT OUT
Pin Description
Equivalent Circuit
Integrating amplifier output
VCC
40kΩ
11
12
PWM
PWM oscillator frequency setting.
Connect a capacitor between this pin and ground.
VCC
300Ω
7.5kΩ
12
13
FIL
VCO system PLL output filter connection
VCC
300Ω
13
14
R
Set the value of the charge/discharge current
from the VCO circuit C pin.
VCC
Insert a resistor between this pin and ground.
300Ω
14
Continued on next page.
No.A0604-9/18
LB11921T
Continued from preceding page.
Pin No.
Symbol
15
C
Pin Description
Equivalent Circuit
VCO oscillator connection
VCC
Insert a capacitor between this pin and ground.
The oscillation frequency of the C pin must not
exceed 1.2MHz.
300Ω
15
16
CSD
Set the operating time of the constrained-rotor
protection circuit.
Reset circuit
VCC
Insert a capacitor between this pin and ground.
This pin also functions as the logic circuit block
power-on reset pin.
300Ω
16
17
NC
There is unconnected pin, and can be used for
wiring.
18
FGOUT
FG amplifier output
VCC
This pin is connected to the FG Schmitt
comparator circuit internally in the IC.
40kΩ
18
FG Schmitt comparator
20
+
FGIN
FG amplifier inverting input
VCC
300Ω
FGOUT
FG amplifier noninverting input.
Insert a capacitor between this pin and ground.
20kΩ
FGIN-
The 1/2 VCC potential.
500Ω
500Ω
19
20
20kΩ
19
Continued on next page.
No.A0604-10/18
LB11921T
Continued from preceding page.
Pin No.
Symbol
21
RF GND
Pin Description
Equivalent Circuit
Output current detection reference
VCC
Connect to GND of the external resistor Rf.
21
22
RF
Output current detection
Connect a low resistance resistor Rf between this
VCC
pin and Rf GMD pin.
This resistor sets the maximum output current
IOUT to be 0.26/Rf.
22
23
GND
GND pin
24
UL
Outputs (that are used to drive external
25
UH
transistors).
26
VL
Duty cycle is controlled on the UH, VH, and WH
27
VH
side of these output.
28
WL
29
WH
VCC
50kΩ
24 26 28
30
VCC
25 27 29
Power supply
Connect a capacitor between this pin and ground
for stabilization.
31
IN3-
Hall-effect device inputs.
32
IN3+
The input is seen as a high-level input when IN+
33
IN2-
> IN-, and as a low-level input for the opposite
34
IN2+
state.
35
IN1-
If noise on the Hall-effect device signals is a
36
IN1+
problem, insert capacitors between the
corresponding IN+ and IN- inputs.
VCC
500Ω
32 34 36
500Ω
31 33 35
No.A0604-11/18
LB11921T
Sample Application Circuit 1 (P-channel + N-channel, Hall-effect sensor application)
24V
IN2-
IN3+
IN3-
VCC
WH
26
25
24
23
22
21
20
19
FGIN-
IN2+
27
FGIN+
IN1-
28
RFGND
29
RF
30
GND
31
UL
32
UH
33
VL
34
VH
35
WL
36
IN1+
5V
S/S
CLK
F/R
BR
FGS
LD
DOUT
POUT
INT.REF
INT.IN
INT.OUT
PWM
FIL
R
C
CSD
NC
FGOUT
LB11921T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
S/S CLK F/R
BR FGS LD
No.A0604-12/18
LB11921T
Sample Application Circuit 2 (PNP + NPN, Hall-IC application)
24V
23
22
21
20
19
FGIN-
24
FGIN+
25
RFGND
26
RF
27
GND
IN3+
28
UL
IN2-
29
UH
IN2+
30
VL
IN1-
31
VH
32
WL
33
WH
34
VCC
35
IN3-
36
IN1+
5V
S/S
CLK
F/R
BR
FGS
LD
DOUT
POUT
INT.REF
INT.IN
INT.OUT
PWM
FIL
R
C
CSD
NC
FGOUT
LB11921T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
S/S CLK F/R BR FGS LD
No.A0604-13/18
LB11921T
LB11921T Overview
1. Speed Control Circuit
This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The
speed discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The
PLL circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a
speed discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in
motor speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency
(fFG) is controlled to have the equal frequency with the clock signal (fCLK) which is input through the CLK pin.
fFG = fCLK
2. VCO Circuit
The LB11921T includes a built-in VCO circuit to generate the speed discriminator circuit reference signal. The
reference signal frequency is given by the following formula.
fVCO = fCLK × 512
fVCO: Reference signal frequency
fCLK: Externally input clock frequency
The range over which the reference signal frequency can be varied is determined by the resistor and capacitor
components connected to the R and C pins (pins 14 and 15) and by the VCO loop filter constant (the values of the
external components connected to pin 13).
Reference value at VCC = 5V
fFG in the high-speed
R(kΩ)
C(pF)
1.5kHz
5.6
330
2.0kHz
5.6
220
rotation mode
The components connected to the R, C, and FIL pins must be connected with lines to their ground pin (pin 23) that
are as short as possible.
3. Output Drive Circuit
To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are
external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with
which the output is on. The PWM switching is performed on the UH, VH, and WH pins. The PWM switching side in
the output can be selected to be either the high or low side depending on how the external transistors are connected.
4. Current Limiter Circuit
The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.26V (typical), Rf: current
detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.
High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current
detection resistor (Rf).
5. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open
collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to
the speed error to control the motor speed to be within the lock range.
6. Notes on the PWM Frequency
The PWM frequency is determined by the capacitor (F) connected to the PWM pin.
fPWM ≈ 1/(64000 × C)
A PWM frequency of between 15 and 25kHz is desirable. If the PWM frequency is too low, the motor may resonate
at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result
in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. To make the
circuit less susceptible to noise, the connected capacitors must be connected to the GND pin (pin 23) with
lines that are as short as possible.
No.A0604-14/18
LB11921T
7. Hall effect sensor input signals
An input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs. The closer the input waveform is
to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required the closer
the input waveform is to a triangular wave. Also note that the input DC voltage must be set to be within the
commonmode input voltage range.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins.
When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of
the Hall effect sensor signal inputs as 0 to VCC level signals if the other side is held fixed at a voltage within the
common-mode input voltage range that applies when a Hall effect sensors are used.
8. Forward/Reverse Switching
The motor rotation direction can be switched using the F/R pin. However, the following notes must be observed if the
motor direction is switched while the motor is turning.
• This IC is designed to avoid through currents when switching directions. However, increases in the motor supply
voltage (due to instantaneous return of motor current to the power supply) during direction switching may cause
problems. The values of the capacitors inserted between power and ground must be increased if this increase is
excessive.
• If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be
turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the
motor back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does
not exceed the ratings of the output transistors used. (The higher the motor speed at which the direction is
switched, the more severe this problem becomes.)
9. Brake Switching
The LB11921T provides a short-circuit brake implemented by turning the output transistors for the UH, VH, and WH
pins for all phases on. (The opposite side transistors are turned off for all phases.) Note that the current limiter does
not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed. The current that
flows in the output transistors during braking is determined by the motor back EMF voltage and the coil resistance.
Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The
higher the motor speed at which braking is applied, the more severe this problem becomes.)
The braking function can be applied and released with the IC in the start state. This means that motor startup and stop
control can be performed using the brake pin with the S/S pin held at the low level (the start state). If the startup time
becomes excessive, it can be reduced by controlling motor startup and stop with the brake pin rather than with the
S/S pin. (Since the IC goes to the power saving state when stopped, enough time for the VCO circuit to stabilize will
be required at the beginning of the motor start operation.)
10. Constraint Protection Circuit
The LB11921T includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint
mode. If the LD output remains high (indicating the unlocked state) for a fixed period in the start state, the PWM
output (external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CSD
pin.
The set time (in seconds) is 15.1 × C (μF)
To clear the motor constrained protection state, the application must either switch to the stop or brake state for a fixed
period (about 1ms or longer), or the power must be turned off and reapplied.
If the motor constrained protection circuit is not used, a 360kΩ resistor and a 3300pF capacitor must be connected in
parallel between the CSD pin and ground. However, in that case, the clock disconnect protection circuit described
below will no longer function. Since the CSD pin also functions as the power-on reset pin, if the CSD pin were
connected directly to ground, the IC would go to the power-on reset state and motor drive operation would remain
off. The power-on reset state is cleared when the CSD pin voltage rises above a level of about 0.25V.
11. Clock Disconnect Protection Circuit
If the clock input goes to the no input state when the IC is in the start state, this protection circuit will operate and
turn off the PWM output. If the clock is resupplied before the motor constraint protection circuit operates, the IC will
return to the drive state, but if the motor constraint protection circuit does operate, the IC must either be set
temporarily (approximately 1 ms or over) to the stop or brake state, or the power must be turned off and reapplied.
No.A0604-15/18
LB11921T
12. Low-Voltage Protection Circuit
The LB11921T includes a low-voltage protection circuit to protect against incorrect operation when VCC power is
applied or if the power supply voltage falls below its operating level. The (external) all output transistors are turned
off if VCC falls under about 3.74 volts, and the protection function is cleared at about 3.93 volts or higher.
13. Power Supply Stabilization
Since this IC is used in applications that draw large output currents, the power-supply line is subject to fluctuations.
Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between
the VCC pin and ground. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse
power supply connection, since this makes the power-supply voltage even more subject to fluctuations, even larger
capacitors will be required.
14. Ground Lines
The signal system ground and the output system ground must be separated and a single ground point must be taken at
the connector. Since the output system ground carries large currents, this ground line must be made as short as
possible.
Output system ground --- Ground for Rf, output diodes, and 24V line capacitors
Signal system ground --- Ground for the IC, external components, and 5V line capacitors
15. FG Amplifier
The FG amplifier is normally implemented as a filter amplifier such as that shown in the application circuits to reject
noise. Since a clamp circuit has been added at the FG amplifier output, the output amplitude is clamped at about
3Vp-p, even if the gain is increased.
Since a Schmitt comparator is inserted after the FG amplifier, applications must set the gain so that the amplifier
output amplitude is at least 250mVp-p. (It is desirable that the gain be set so that the amplitude is over 0.5Vp-p at
the lowest controlled speed to be used.)
The capacitor inserted between the FGIN+ pin (pin 20) and ground is required for bias voltage stabilization. To make
the connected capacitor as immune from noise as possible, connect this capacitor to the GND pin (pin 23) with a line
that is as short as possible.
16. Integrating Amplifier
The integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed
controlling voltage. At the same time it also sets the control loop gain and frequency characteristics.
External components necessary for the integrating amplifier must be placed as close to the IC as possible to reduce
influence of noise.
17. FIL Pin External Components
The capacitor inserted between the FIL pin and ground is used to suppress ripple on the FIL pin voltage. Therefore,
application designers must select a capacitance value that provides fully adequate smoothing of the FIL pin voltage
even at the lowest external clock input frequency used. Also, the FIL pin voltage convergence time (the time until the
reference signal stabilizes) when the input clock frequency is switched is shortened by connecting a resistor and a
capacitor in series between the FIL pin and ground. Therefore, designers must select values for the resistor and
capacitor that give the required convergence time.
No.A0604-16/18
LB11921T
18. R and C Pin External Components
The maximum range over which the reference signal frequency fVCO can be varied when 5V is used as the VCC
supply voltage is about a factor of three.
When it is desirable to make this range as wide as possible, since the values of the R pin external resistor (R) and the
C pin external capacitor (C) are determined by the maximum value of the reference signal frequency (fVCO1) and
the minimum value (VCCL) of the VCC power supply due to unit-to-unit variations, R and C can be determined
using the following procedure as a reference.
(1) Calculate R1 and C1 using the following formulas and determine values for R and C such that the conditions R ≤
R1 and C ≤ C1 will hold taking the sample-to-sample variations (including other issues such as temperature
characteristics) into account.
R1 = (VCCL-2.2 V)/370μA
C1 = (370μA /0.9V) × (1/fVCO1) × 0.7
(2) The minimum value (fVCO2) for the reference signal frequency that can be set for the R and C values determined
in step (1) can be calculated from the following formula if we let R2 and C2 be the smallest values for R and C
due to the sample-to-sample variations (including other issues such as temperature characteristics). Therefore, the
range over which the reference signal frequency can be set is fVCO1 to fVCO2.
fVCO2 = 0.38/(R2 × C2)
(3) The following are the conditions that must be met and the points that require care when determining the values of
the external components connected to the R and C pins.
1. The maximum value of the set reference signal frequency must not exceed 1.2MHz.
2. The R pin voltage and the FIL pin voltage must be in the range 0.3V to (VCCL-2.2V). (VCCL is the lowest
value of the VCC supply voltage given the unit-to-unit variations. VCCL is always greater than or equal to
4.4V.) However, the lower the R pin voltage, the more susceptible the system will be to ground line noise, and
the reference signal frequency may become unstable as a result. Therefore the lower end of the R pin voltage
range must not be used if there is much ground line noise in the system.
3. Set the value of the R pin external resistor to a value in the range 5.6kΩ to 10kΩ. Also, assure that the R pin
current remains under 370μA.
4. Set the value of the C pin external capacitor to a value in the range 220pF to 1000pF.
5. When it is desirable to make the range of the reference signal frequency as wide as possible, set the values of R
and C to the largest possible values. (However, those values must be lower than the calculated values R1 and
C1.) Use components with the smallest sample-to-sample variations possible. The VCC voltage must be made
as much higher than 5V as possible to acquire the widest possible range for the reference signal frequency.
19. NC pin
Since the NC pins are electrically open with respect to the IC itself, they can be used as intermediate connection
points for lines in the PCB pattern.
No.A0604-17/18
LB11921T
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PS No.A0604-18/18