LC75843UGA Application Note Design method of the LCD system using 1/2-duty LCD panel http://onsemi.com Overview This application note explains the design method of the LCD (Liquid Crystal Display) system using LCD driver IC (LC75843UGA). The LC75843UGA is the 1/1 to 1/4 duty general-purpose LCD driver that can be used in applications such as automotive display by control with the controller. In addition, this IC is able to drive up to 100 segments directly, and can also control up to four general-purpose output ports. Moreover, it has a built-in 3ch PWM (Pulse Width Modulation) function for brightness adjustment of LED (Light Emitting Diode). Furthermore, because of built-in the oscillator circuit, it is possible to reduce external resister and external capacitor for oscillation. CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. CCB is a registered trademark of Semiconductor Components Industries, LLC. © Semiconductor Components Industries, LLC, 2014 April, 2014 - Rev.0 1 LC75843UGA Application Note LCD System Configuration Example This application note explains various function explanations and setting method example of serial control data in the LCD system configuration using LCD driver IC (LC75843UGA) as shown below. VOUP (Pull-up power supply for LED) LCD Driver IC (LC75843UGA) +5.0 [V] S1/P1 (Button indicator A) S2/P2 (Button indicator B) S3/P3 (Button indicator C) VDD VSS OSCI S4/P4 (Backlight) 20 LCD Controller /INH 3 (CCB interface) CE CL DI S5 to S24 COM4/S25 (open) COM3/S26 (open) S28 (open) LCD Panel (2com x 20seg = 40 segments) S27/COM2 COM1 Figure 1. LCD system configuration using LCD driver IC (LC75843UGA) < Operation specifications of the LCD system > LCD driver IC (LC75843UGA) specifications Support for static (1/1-duty) or 1/2-duty or 1/3-duty or 1/4-duty drive. (Capable of driving the LCD up to 100 segments directly) Built-in LCD drive bias voltage stabilization circuit. Support for up to four general-purpose output ports Support for the PWM output function of a maximum of 3ch. Support for clock output function of 1ch. Incorporation of an oscillator circuit (Incorporation of resistor and capacitor for an oscillation), and setting of the “Internal oscillator operating mode” or “External clock input operating mode” is possible by serial control data. Serial control data input supports CCB* format communication with the system controller. (Support 3.3V and 5.0V operation) Adjustment of the frame frequency of the LCD drive waveform is possible by serial control data. Adjustment of the frame frequency of the PWM drive waveform is possible by serial control data. Setting of the power saving mode or the all segments turn off mode is possible by serial control data. The /INH pin allows the display to be forced off state. LCD system specifications of Figure 1 The LCD panel to use has 20-segments and 2-commons. Total display segments are 40-segments. Therefore, LCD drive duty ratio is 1/2-duty. 1/2-bias. The four general-purpose output ports are used. Control of the LED by PWM function. Unused. Internal oscillator operating mode is used. Used. (Controlled by LCD controller) Frame frequency is adjusted, but frequency value is undecided. PWM is controlled, but frequency value is undecided. Used. (Controlled by LCD controller) Used. (Controlled by LCD controller) http://onsemi.com 2 LC75843UGA Application Note Pin Assignment DI CL CE /INH OSCI VSS VDD S28 COM1 COM2/S27 COM3/S26 COM4/S25 S24 S23 S22 S21 S20 S19 The following figure shows the pin assignment of LCD driver IC (LC75843UGA). 36 19 LC75843UGA (TSSOP36) (Top view) 1 S1/P1 S2/P2 S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 18 Figure 2. Pin Assignment of LCD driver IC (LC75843UGA) Table 1. Pin function of LCD driver IC (LC75843UGA) Pin name S1/P1 S2/P2 S3/P3 S4/P4 S5 to S24 S28 COM1 COM2/S27 COM3/S26 COM4/S25 OSCI CE CL DI /INH VDD VSS Pin function General-purpose port output pin. The S1/P1 pin can be used as a segment drive pin by control data (P0 to P2). General-purpose port output pin. The S2/P2 pin can be used as a segment drive pin by control data (P0 to P2). General-purpose port output pin. The S3/P3 pin can be used as a segment drive pin by control data (P0 to P2). General-purpose port output pin. The S4/P4 pin can be used as a segment drive pin by control data (P0 to P2). Segment drive output pins. Segment drive output pin. When “S28 output off mode (DN=0)”, S28 is VSS level output. When “S28 output on mode (DN=1)”, S28 is segment output. Common drive output pin. Common drive or segment drive output pin. The COM2/S27 pin can be used as a segment drive pin by control data (DT0, DT1). Common drive or segment drive output pin. The COM3/S26 pin can be used as a segment drive pin by control data (DT0, DT1). Common drive or segment drive output pin. The COM4/S25 pin can be used as a segment drive pin by control data (DT0, DT1). External clock input pin. When “Internal oscillator operating mode (OC=0)”, make sure to connect OSCI to GND. When “External clock input mode (OC=1)”, OSCI is used to input the external clock. Serial data transfer chip enable input pin. Serial data transfer synchronization clock input pin. Serial data transfer data input pin. Display off control input pin. /INH=High (VDD) : Display ON /INH=Low (VSS) : Display forced off General-purpose output port pins (S1/P1 to S4/P4) are VSS level. Segment output pins (S5 to S24, and S28) are VSS level. Common output pins (COM1, COM2/S27, COM3/S26 and COM4/S25) are VSS level. The internal oscillator circuit is stopped. External clock input is inhibited. The reception of serial control data is possible. (Registers are updated) Logic power supply pin for LCD driver IC. A power supply voltage of +4.5 [V] to +6.3 [V]. Ground pin. Must be connected all each board to the ground. http://onsemi.com 3 LC75843UGA Application Note Serial Control Data Transfer Explanation (1) Basic Timing The LC75843UGA has several internal registers. These internal registers are written by CCB interface (Serial interface). Structure of transfer bits consists of CCB address and instruction data. First eight bits are CCB address (44h). The bit number of instruction data is different depending on an instruction. The serial control data is taken by the positive edge of the CL signal, which is latched by the negative edge of the CE signal. When the number of data in CE=VDD period is different from the defined number (64-bits and 48-bits), IC does not execute the instruction and holds the old state. Even when CL signal stops at high level, the CCB interface can be received. However, serial Control Data transfer timing (transfer form) is different. Therefore, when designing equipment, refer to the “Delivery specification for the LC75843UGA”. CE input CL input DI input Address Display data Control data 8 bits Direction data (=0,1) Instruction data (64 bits) CE input CL input DI input Address Control data Direction data (=1,0) 8 bits Instruction data (48 bits) Figure 3. Basic timing when CL signal is stopped at the Low Level Since the IC internal data is undefined when power supply is first applied, applications should set the /INH pin=Low (VSS) at the same time as power supply is applied to turn off the display (The S1/P1 to S4/P4, S5 to S24, COM4/S25, COM3/S26, COM2/S27, COM1 and S28 pins are outputted at the VSS level), and during this period send serial control data from the controller. The controller should then set the /INH pin=High (VDD) after the data transfer has completed. This procedure prevents meaningless display at power supply on. t1 > 1 [ms] t2 > 0 [ms] VDD /INH input tc > 10 [us] Display OFF Display ON Display OFF CE input CCB interface CL input DI input DD=0,1 DD=1,0 Internal data LCD display state (Segments, Commons) General-purpose output ports state (S1/P1 to S4/P4) Undefined Defined Undefined Display forced off (VSS level) Segment ON is possible Display forced off (VSS level) Forced off (VSS level) ON/OFF control is possible Forced off (VSS level) Figure 4. Basic timing of serial control data transfer http://onsemi.com 4 LC75843UGA Application Note (2) Allowable Operating Ranges of the Serial Control Data Transfer The following figure shows the specifications of the allowable operating ranges when CL signal is stopped at the low level. VIH1 50% VIL1 CE tclL tclH VIH1 50% VIL1 CL tf tcp tr tcs tch VIH1 50% VIL1 DI tds tdh Figure 5. Allowable operating ranges of serial control data transfer Table 2. Allowable operating ranges Parameter Symbol Conditions Min. Typ. Max. Unit 6.3 V 0.4 VDD 6.3 V 0 0.2 VDD V 3.125 MHz Power Supply Voltage VDD VDD Input High Level Voltage VIH1 CE, CL, DI, /INH Input Low Level Voltage VIL1 CE, CL, DI, /INH Serial Data Transfer Synchronization Clock Frequency fcl CL, 1/(tclL+tclH) Data Setup Time tds CL, DI 160 ns Data Hold Time tdh CL, DI 160 ns CE Wait Time tcp CE, CL 160 ns CE Setup Time tcs CE, CL 160 ns CE Hold Time tch CE, CL 160 ns High Level Clock Pulse Width tclH CL 160 ns Low Level Clock Pulse Width tclL CL 160 ns Rise Time tr CE, CL, DI Fall Time tf CE, CL, DI /INH Switching Time tc /INH, CE 4.5 10 160 ns 160 ns us These specifications show an example, and, we have a case to change these specifications without a notice for improvement. Therefore, it is not guaranteed for design as the mass production equipment. When designing equipment, refer to the “Delivery specification for the LC75843UGA”. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 5 LC75843UGA Application Note (3) Allotment of Serial Control Data The following figure shows the serial control data transfer form when the “1/2-duty drive mode” and CL signal is stopped at the low level. CE CL DI 0 0 1 0 0 0 1 0 D1 D2 D3 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 DT0 DT1 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Display data (54 bits) Control data (8 bits) Direction data (2 bits) CE CL DI 0 0 1 0 0 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Control data (18 bits) Fixed data (4 bits) PF0 PF1 PF2 PF3 PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 P0 P1 P2 FC0 FC1 FC2 FC3 DN EXF OC SC BU Control data (24 bits) B0 to B3, A0 to A3 : CCB address. (=44h) D1 to D54 DT0, DT1 W10 to W15 W20 to W25 W30 to W35 PF0 to PF3 PS10, PS11 PS20, PS21 PS30, PS31 PS40, PS41 P0 to P2 FC0 to FC3 DN EXF OC SC BU : Display data setting registers. : LCD drive type (Duty ratio, Bias ratio) setting registers. : PWM duty setting registers of the PWM output function (ch1). : PWM duty setting registers of the PWM output function (ch2). : PWM duty setting registers of the PWM output function (ch3). : PWM output waveform frame frequency setting registers. : General-purpose output port (S1/P1) function setting registers. : General-purpose output port (S2/P2) function setting registers. : General-purpose output port (S3/P3) function setting registers. : General-purpose output port (S4/P4) function setting registers. : S1/P1 to S4/P4 output pins function setting registers. : LCD drive waveform frame frequency setting registers. : S28 pin function setting register. : External clock operating frequency setting register. (When OC=1, EXF is valid.) : Fundamental clock operating mode setting register. : All segments turn off mode setting register. : Power saving mode setting register. http://onsemi.com 6 1 0 Direction data (2 bits) LC75843UGA Application Note Explanation of the LCD drive control LCD Driver IC (LC75843UGA) S1/P1 (LED is controlled by general-purpose output port) S2/P2 (LED is controlled by general-purpose output port) S3/P3 (LED is controlled by general-purpose output port) (LED is controlled by general-purpose output port) S4/P4 20 S5 to S24 COM4/S25 (open) COM3/S26 (open) S28 (open) LCD Panel (2com x 20seg = 40 segments) S27/COM2 COM1 Figure 6. Peripheral circuits configuration example of the LCD driver outputs (1) LCD Drive Waveform It is explanation about the drive type of the 1/2-duty and 1/2-bias. The common outputs (COM1, COM2/S27) repeat VDD level, VSS level and 1/2 VDD level in turn. On the other hand, the segment outputs (S5 to S26, and S28) repeat VSS level and VDD level by a state of display ON/OFF (Display data setting register is 1/0). When the LCD segment is ON (It interrupt light), the potential difference of segment output and common output becomes VDD level. When the LCD segment is OFF (It penetrate light), the potential difference of segment output and common output becomes lower than 1/2 VDD level. This drive method assigns a half of a frame to control of ON/OFF of one segment. In addition, this drive method uses the 1/2 VDD level divided in two between VDD and VSS. Thus, this drive method is called the “1/2-duty and 1/2-bias drive”. When set the “1/2-duty drive mode”, the following figure shows the LCD drive waveform. VDD /INH input Display forced off Display on VSS VDD COM1 output 1/2 VDD VSS VSS VDD S27/COM2 output 1/2 VDD VSS VSS LCD driver output when all LCD segments corresponding to COM1 and COM2 are off. (When display data were set to “0, 0”) VDD VSS VSS VDD LCD driver output when only LCD segments corresponding to COM1 are on. (When display data were set to “1, 0”) VSS LCD driver output when only LCD segments corresponding to COM2 are on. (When display data were set to “0, 1”) VSS LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. (When display data were set to “1, 1”) VSS VSS VDD VSS VDD VSS Frame frequency fo [Hz] Figure 7. LCD driver output waveform http://onsemi.com 7 LC75843UGA Application Note (2) LCD Drive Type Setting (DT0, DT1) The registers of the DT0 and DT1 can set the LCD drive type from 1/1-duty to 1/4-duty. The LCD system configuration example is LCD panel of the 1/2-duty drive used. Therefore, this system sets DT0=0 and DT1=1. DT0 DT1 LCD drive type 0 1 0 1 0 0 1 1 1/4-duty and 1/3-bias drive type 1/3-duty and 1/3-bias drive type 1/2-duty and 1/2-bias drive type Static (1/1-duty) drive type COM1 COM1 COM1 COM1 COM1 Output pins state COM2/S27 COM3/S26 COM4/S25 COM2 COM3 COM4 COM2 COM3 S25 COM2 S26 S25 S27 S26 S25 (3) S28 Pin Function Setting (DN) The DN register can set the “Segment output of the S28 output pin” or “VSS level output of the S28 output pin”. The LCD system configuration example does not use S28 output pin. Therefore, this system sets DN=0. DN S28 output pin state 0 1 VSS level output S28 segment output (4) Display Data Setting (D1 to D54) The registers from D1 to D54 set the LCD segment ON/OFF, or these registers set the general-purpose output port (P1 to P4) of high level output or low level output. The LCD system configuration example is the “1/2-duty drive mode”, and LCD segments from S5 to S24 used. Therefore, set the LCD display data from D9 to D48. In addition, the pins from S1/P1 to S4/P4 use general-purpose output port function. Therefore, set the general-purpose output ports (P1 to P4) of high level output or low level output by the LCD display data to D1, D3, D5 and D7. About the control method of “Display data setting registers (D1 to D8)”, refer to paragraph (3) of “Explanation of the LED Control by General-purpose Output Ports”. When set the “1/2-duty drive mode”, the following table shows the relation between the “Display data setting registers (D9 to D48)” and the segment outputs and the common outputs. Output pin COM1 COM2/S27 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 COM4/S25 COM3/S26 S28 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 D54 Notes Thes display data are unused, and D49 and D50 sets the all “0”. Thes display data are unused, and D51 and D52 sets the all “0”. Thes display data are unused, and D53 and D54 sets the all “0”. For example, the following table shows the relation between the “Display data setting register” and S5 output pin state. http://onsemi.com 8 LC75843UGA Application Note Display data D9 D10 0 0 1 0 0 1 1 1 S5 output pin state All LCD segments corresponding to COM1 and COM2 are off. LCD segments corresponding to COM1 is on and LCD segments corresponding to COM2 is off. LCD segments corresponding to COM1 is off and LCD segments corresponding to COM2 is on. All LCD segments corresponding to COM1 and COM2 are on. Explanation of the LED Control by General-purpose Output Ports VOUP (Pull-up power supply for LED) LCD Driver IC (LC75843UGA) S1/P1 (Button indicator A) S2/P2 (Button indicator B) S3/P3 (Button indicator C) S4/P4 (Backlight) Figure 8. Peripheral circuits configuration example of the general-purpose output ports (1) LED Control Waveform The LC75843UGA has up to four general-purpose output ports. In addition, the PWM output function has up to 3ch and can perform brightness adjustment of the LED individually for each channel. The brightness of the LED has a method to adjust a forward current of LED flowing at the time of ON, or there is pulse width modulation (PWM) control to adjust the apparent brightness by repeating ON and OFF at high speed. The LED looks bright if the ON time per unit time by PWM control is long. In addition, it looks dark if the ON time per unit time by PWM control is short. When LED is always turn on (Brightness is 100%), the consumption electric current is maximum. When LED is ON, the LED uses electricity, and when LED is OFF, the LED does not use electricity. Thus, it can set the low power consumption by PWM control. When used the general-purpose output port, the following figure shows the LED control waveform. http://onsemi.com 9 LC75843UGA Application Note /INH input S1/P1 to S4/P4 outputs when general-purpose output portwas set to low S1/P1 to S4/P4 outputs when general-purpose output port was set to high VDD LED off LED on VSS VDD LED off LED off (0% duty) LED off LED on (100% duty) VSS VDD VSS LED on S1/P1 to S4/P4 outputs when PWM duty was set to 1/64(1.56%) VDD LED off VSS LED on S1/P1 to S4/P4 outputs when PWM duty was set to 2/64(3.12%) VDD LED off VSS LED on S1/P1 to S4/P4 outputs when PWM duty was set to 3/64(4.69%) LED off VDD S1/P1 to S4/P4 outputs when PWM duty was set to 32/64(50.00%) LED off S1/P1 to S4/P4 outputs when PWM duty was set to 62/64(96.87%) LED off LED on S1/P1 to S4/P4 outputs when PWM duty was set to 63/64(98.44%) LED off LED on S1/P1 to S4/P4 outputs when PWM duty was set to 64/64(100.00%) LED off LED on VSS VDD LED on VSS VDD VSS VDD VSS VDD VSS Frame frequency fp [Hz] Figure 9. General-purpose port output waveform (2) S1/P1 to S4/P4 Output Pins Function Setting (P0 to P2) The registers from P0 to P2 can set the “Output pins from S1/P1 to S4/P4 of the segment output port” or “Output pins from S1/P1 to S4/P4 of the general-purpose output port”. The LCD system configuration example controls LED by general-purpose output port of the S1/P1 to S4/P4 output pins. Therefore, this system sets P0=1, P1=0 and P2=0. P0 P1 P2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 S1/P1 S1 P1 P1 P1 P1 S1 S1 S1 Output pin state S2/P2 S3/P3 S2 S3 S2 S3 P2 S3 P2 P3 P2 P3 S2 S3 S2 S3 S2 S3 http://onsemi.com 10 S4/P4 S4 S4 S4 S4 P4 S4 S4 S4 S1 to S4 : Segment output ports P1 to P4 : General-purpose output ports LC75843UGA Application Note (3) General-purpose Ports (P1 to P4) Function Setting (PS10,PS11,PS20,PS21,PS30,PS31,PS40 and PS41) The registers from PS10 and PS11 can set the “General-purpose output function”, “Clock output function”, or “PWM output function” of the general-purpose output port (P1). In addition, PS20, PS21, PS30, PS31, PS40 and PS41 registers can set the “General-purpose output function” or “PWM output function” of the general-purpose output ports (P2 to P4). The general-purpose output function outputs general-purpose output ports (P1 to P4) of high level or low level by “Display data setting registers (D1 to D8)”. The clock output function outputs internal oscillator clock (fosc) or external clock input (fck) of the 1/2 frequency division or 1/8 frequency division. This function can set only generalpurpose output port (P1). Therefore, when stop the clock, the “Display data setting register (D1)” by general-purpose output function sets the “0”, and general-purpose output port (P1) outputs low level. The PWM output function has up to 3ch and can perform brightness adjustment of the LED individually for each channel. However, PWM duty setting register (W10 to W15, W20 to W25, and W30 to W35) does not have a setting function of 0%-duty. Therefore when you want to turn off the LED, the “Display data setting registers (D1 to D8)” by general-purpose output function set the “0”, and general-purpose output ports (P1 to P4) output low level. PS10 0 1 0 1 PS11 0 0 1 1 General-purpose output port (P1) function General-purpose output function : High level or low level output Clock output function : Outputs a clock of the fosc/2 frequency Clock output function : Outputs a clock of fosc/8 frequency PWM output function (ch1) : Controlled by PWM duty setting register from W10 to W15 PS20 0 1 0 1 PS21 0 0 1 1 General-purpose output port (P2) function General-purpose output function : High level or low level output PWM output function (ch1) : Controlled by PWM duty setting register from W10 to W15 PWM output function (ch2) : Controlled by PWM duty setting register from W20 to W25 PWM output function (ch3) : Controlled by PWM duty setting register from W30 to W35 PS30 0 1 0 1 PS31 0 0 1 1 General-purpose output port (P3) function General-purpose output function : High level or low level output PWM output function (ch1) : Controlled by PWM duty setting register from W10 to W15 PWM output function (ch2) : Controlled by PWM duty setting register from W20 to W25 PWM output function (ch3) : Controlled by PWM duty setting register from W30 to W35 PS40 0 1 0 1 PS41 0 0 1 1 General-purpose output port (P4) function General-purpose output function : High level or low level output PWM output function (ch1) : Controlled by PWM duty setting register from W10 to W15 PWM output function (ch2) : Controlled by PWM duty setting register from W20 to W25 PWM output function (ch3) : Controlled by PWM duty setting register from W30 to W35 The LCD system configuration example uses general-purpose output port function from S1/P1 to S4/P4. The following table shows the relation between the “Display data setting registers (D1 to D8)” and general-purpose output ports (P1 to P4) of high level or low level. Display data Controlled output pin D1 S1/P1 D3 S2/P2 D5 S3/P3 D7 S4/P4 Notes When PS10=0, PS11=0 and D1=0, S1/P1 is outputted at the low level. When PS10=0, PS11=0 and D1=1, S1/P1 is outputted at the high level. When “PS10, PS11” are not “0, 0”, D1 is invalid. When PS20=0, PS21=0 and D3=0, S2/P2 is outputted at the low level. When PS20=0, PS21=0 and D3=1, S2/P2 is outputted at the high level. When “PS20, PS21” are not “0, 0”, D3 is invalid. When PS30=0, PS31=0 and D5=0, S3/P3 is outputted at the low level. When PS30=0, PS31=0 and D5=1, S3/P3 is outputted at the high level. When “PS30, PS31” are not “0, 0”, D5 is invalid. When PS40=0, PS41=0 and D7=0, S4/P4 is outputted at the low level. When PS40=0, PS41=0 and D7=1, S4/P4 is outputted at the high level. When “PS40, PS41” are not “0, 0”, D7 is invalid. http://onsemi.com 11 LC75843UGA Application Note When control the LED in the system configuration example of the Figure 8, a register setting example is shown below. (Case 1) When all LED were set to OFF. General-purpose output port (P1) control OFF PS10 PS11 D1 0 0 0 General-purpose output port (P2) control OFF PS20 PS21 D3 0 0 0 General-purpose output port (P3) control OFF PS30 PS31 D5 0 0 0 General-purpose output port (P4) control OFF PS40 PS41 D7 0 0 0 General-purpose output port (P3) control OFF PS30 PS31 D5 0 0 0 General-purpose output port (P4) control ON (W30 to W35=1,1,1,1,1,0) PS40 PS41 D7 1 1 0 (Case 2) When backlight-LED was set to ON (Brightness is 50%). General-purpose output port (P1) control OFF PS10 PS11 D1 0 0 0 General-purpose output port (P2) control OFF PS20 PS21 D3 0 0 0 (Case 3) When backlight-LED was set to ON (Brightness is 50%) and button indicator A-LED was set to ON (Brightness is 50%). General-purpose output port (P1) control ON (W10 to W15=1,1,1,1,1,0) PS10 PS11 D1 1 1 0 General-purpose output port (P2) control OFF PS20 PS21 D3 0 0 0 General-purpose output port (P3) control OFF PS30 PS31 D5 0 0 0 General-purpose output port (P4) control ON (W30 to W35=1,1,1,1,1,0) PS40 PS41 D7 1 1 0 (Case 4) When backlight-LED was set to ON (Brightness is 50%) and button indicator B-LED was set to ON (Brightness is 50%). General-purpose output port (P1) control OFF PS10 PS11 D1 0 0 0 General-purpose output port (P2) control ON (W10 to W15=1,1,1,1,1,0) PS20 PS21 D3 1 0 0 General-purpose output port (P3) control OFF PS30 PS31 D5 0 0 0 General-purpose output port (P4) control ON (W30 to W35=1,1,1,1,1,0) PS40 PS41 D7 1 1 0 (Case 5) When backlight-LED was set to ON (Brightness is 50%) and button indicator A/B/C-LED were set to ON (Brightness is 50%). General-purpose output port General-purpose output port General-purpose output port General-purpose output port (P1) control (P2) control (P3) control (P4) control ON (W10 to W15=1,1,1,1,1,0) ON (W10 to W15=1,1,1,1,1,0) ON (W20 to W25=1,1,1,1,1,0) ON (W30 to W35=1,1,1,1,1,0) PS10 PS11 D1 PS20 PS21 D3 PS30 PS31 D5 PS40 PS41 D7 1 1 0 1 0 0 0 1 0 1 1 0 (Case 6) When button indicator C-LED was changed from 50% to 79.69%. General-purpose output port General-purpose output port General-purpose output port General-purpose output port (P1) control (P2) control (P3) control (P4) control ON (W10 to W15=1,1,1,1,1,0) ON (W10 to W15=1,1,1,1,1,0) ON (W20 to W25=0,1,0,0,1,1) ON (W30 to W35=1,1,1,1,1,0) PS10 PS11 D1 PS20 PS21 D3 PS30 PS31 D5 PS40 PS41 D7 1 1 0 1 0 0 0 1 0 1 1 0 (Case 7) When backlight-LED was set to OFF. General-purpose output port General-purpose output port General-purpose output port (P1) control (P2) control (P3) control ON (W10 to W15=1,1,1,1,1,0) ON (W10 to W15=1,1,1,1,1,0) ON (W20 to W25=0,1,0,0,1,1) PS10 PS11 D1 PS20 PS21 D3 PS30 PS31 D5 1 1 0 1 0 0 0 1 0 General-purpose output port (P4) control OFF PS40 PS41 D7 0 0 0 (Case 8) When all LED were set to ON (Brightness is 100%). General-purpose output port General-purpose output port General-purpose output port General-purpose output port (P1) control (P2) control (P3) control (P4) control ON (W10 to W15=1,1,1,1,1,1) ON (W10 to W15=1,1,1,1,1,1) ON (W20 to W25=1,1,1,1,1,1) ON (W30 to W35=1,1,1,1,1,1) PS10 PS11 D1 PS20 PS21 D3 PS30 PS31 D5 PS40 PS41 D7 1 1 0 1 0 0 0 1 0 1 1 0 or General-purpose output port (P1) control ON PS10 PS11 D1 0 0 1 General-purpose output port (P2) control ON PS20 PS21 D3 0 0 1 General-purpose output port (P3) control ON PS30 PS31 D5 0 0 1 http://onsemi.com 12 General-purpose output port (P4) control ON PS40 PS41 D7 0 0 1 LC75843UGA Application Note (4) PWM Duty Setting (W10 to W15, W20 to W25, W30 to W35) The registers from W10 to W15, from W20 to W25, and from W30 to W35 can set the pulse width of the PWM output. The PWM duty setting has up to 3ch and can perform brightness adjustment of the LED individually for each channel. However, the PWM duty setting register (W10 to W15, W20 to W25, and W30 to W35) does not have a setting function of the 0%-duty. Therefore when you want to turn off the LED, the “Display data setting registers (D1 to D8)” by general-purpose output function set the “0”, and general-purpose output ports (P1 to P4) output low level. T p = 1 / fp S1/P1 to S4/P4 LED off Tpl Wx0 Wx1 Wx2 Wx3 Wx4 Wx5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Tph PWM output pulse width (PWM duty) 1/64 (1.56%) 2/64 (3.12%) 3/64 (4.69%) 4/64 (6.25%) 5/64 (7.81%) 6/64 (9.38%) 7/64 (10.94%) 8/64 (12.50%) 9/64 (14.06%) 10/64 (15.62%) 11/64 (17.19%) 12/64 (18.75%) 13/64 (20.31%) 14/64 (21.87%) 15/64 (23.44%) 16/64 (25.00%) 17/64 (26.56%) 18/64 (28.12%) 19/64 (29.69%) 20/64 (31.25%) 21/64 (32.81%) 22/64 (34.37%) 23/64 (35.94%) 24/64 (37.50%) 25/64 (39.06%) 26/64 (40.62%) 27/64 (42.19%) 28/64 (43.75%) 29/64 (45.31%) 30/64 (46.87%) 31/64 (48.44%) 32/64 (50.00%) LED on PWM duty = (Tph / (Tpl+Tph)) Wx0 Wx1 Wx2 Wx3 Wx4 Wx5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWM output pulse width (PWM duty) 33/64 (51.56%) 34/64 (53.12%) 35/64 (54.69%) 36/64 (56.25%) 37/64 (57.81%) 38/64 (59.37%) 39/64 (60.94%) 40/64 (62.50%) 41/64 (64.06%) 42/64 (65.62%) 43/64 (67.19%) 44/64 (68.75%) 45/64 (70.31%) 46/64 (71.87%) 47/64 (73.44%) 48/64 (75.00%) 49/64 (76.56%) 50/64 (78.12%) 51/64 (79.69%) 52/64 (81.25%) 53/64 (82.81%) 54/64 (84.37%) 55/64 (85.94%) 56/64 (87.50%) 57/64 (89.06%) 58/64 (90.62%) 59/64 (92.19%) 60/64 (93.75%) 61/64 (95.31%) 62/64 (96.87%) 63/64 (98.44%) 64/64 (100.00%) x : 1 to 3 Explanation of the Instruction Data (1) Fundamental Clock Operating Mode Setting (OC, EXF) LCD Driver IC (LC75843UGA) Internal oscillator clock frequency fosc [kHz] OSCI Internal oscillator circuit clock Figure 10. Peripheral circuits configuration example of the external clock input pin http://onsemi.com 13 LC75843UGA Application Note The OC register can set the “Internal oscillator operating mode” or “External clock input operating mode”. Furthermore, when OC register sets the “External clock input operating mode (OC=1)”, the EXF register can set the division ratio. The EXF register can set the division ratio a clock to input from OSCI pin becomes 300 [kHz](Typ.) and 38 [kHz](Typ.). However, when set the “External clock 38kHz input mode (OC=1 and EXF=1)”, please be careful because PWM output function is invalidity. The LCD system configuration example sets OC=0 and EXF=0 to use the “Internal oscillator operating mode”. OC EXF Fundamental clock operating mode OSCI input pin state 0 1 1 0/1 0 1 Internal oscillator operating mode External clock 300kHz input mode External clock 38kHz input mode Connect to GND Inputs a clock of 300 [kHz](Typ.) Inputs a clock of 38 [kHz](Typ.) The explanation mentioned above is used only to explain internal operation and how to IC, and the characteristic of the products is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. (2) LCD Drive Waveform Frame Frequency Setting (FC0 to FC3) The registers from FC0 to FC3 can set the frame frequency (fo) of the common and segment output waveform. The frame frequency (frame ratio) setting of the LCD drive waveform is different by “Fundamental clock operating mode setting register (OC)” and “External clock operating frequency setting register (EXF)”. Frame frequency fo [Hz] Internal oscillator clock frequency fosc [kHz] LCD drive waveform Internal oscillator circuit clock The LCD system configuration example sets OC=0 to use the “Internal oscillator operating mode”. When sets OC=0, the following table shows the frame frequency of the LCD drive waveform. FC0 FC1 FC2 FC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Internal oscillator operating mode (OC=0) LCD drive waveform frame frequency fo [Hz] LCD drive waveform frame ratio (Internal oscillator clock frequency is fosc=300 [kHz](typ.)) fosc / 6144 48.83 fosc / 5376 55.80 fosc / 4608 65.10 fosc / 3840 78.12 fosc / 3456 86.80 fosc / 3072 97.66 fosc / 2688 111.61 fosc / 2304 130.21 fosc / 2112 142.04 fosc / 1920 156.25 fosc / 1728 173.61 fosc / 1536 195.31 fosc / 1344 223.21 fosc / 1152 260.42 fosc / 960 312.50 fosc / 768 390.62 The explanation mentioned above is used only to explain internal operation and how to IC, and the characteristic of the products is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. http://onsemi.com 14 LC75843UGA Application Note (3) PWM Output Waveform Frame Frequency Setting (PF0 to PF3) The registers from PF0 to PF3 can set the PWM output frame frequency (fp) of the general-purpose output port. When set the “External clock input operating mode setting (OC = 1)” and “External clock 38kHz input mode setting (EXF=1)”, these registers are invalid. Internal oscillator clock frequency fosc [kHz] Internal oscillator circuit clock Frame frequency fp [Hz] PWM output waveform The LCD system configuration example is “Internal oscillator operating mode” operated. Therefore, this system sets OC=0. When sets OC=0, the following table shows the frame frequency (fp) of the PWM output waveform. PF0 PF1 PF2 PF3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Internal oscillator operating mode (OC=0) PWM output waveform frame frequency fp [Hz] PWM output waveform frame ratio (Internal oscillator clock frequency is fosc=300 [kHz](typ.)) fosc / 1536 195.31 fosc / 1408 213.07 fosc / 1280 234.37 fosc / 1152 260.42 fosc / 1024 292.97 fosc / 896 334.82 fosc / 768 390.62 fosc / 640 468.75 fosc / 512 585.94 fosc / 384 781.25 fosc / 256 1171.87 fosc / 896 334.82 fosc / 896 334.82 fosc / 896 334.82 fosc / 896 334.82 fosc / 896 334.82 The explanation mentioned above is used only to explain internal operation and how to IC, and the characteristic of the products is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. (4) All Segments Turn Off Mode Setting (SC) The SC register can set the “Normal mode” or “All segments turn off mode”. The LC75843UGA can display forced turn off by the /INH pin. When sets /INH pin=Low (VSS), segment outputs (S5 to S26, and S28), common outputs (COM1 and COM2/S27) and general-purpose port outputs (S1/P1 to S4/P4) are outputted at the all VSS level. In addition, it can display OFF (turn off the segments) by controllable SC register from the software of the LCD controller. When sets SC=1, segment outputs (S5 to S26, and S28) are outputted at the all off waveform. /INH pin SC register Low (VSS) 0/1 High (VDD) 0 1 Segment outputs (S5 to S26, and S28) All segment outputs are VSS level Segments can output ON waveform All segment outputs are OFF waveform Output pin state Common output (COM1 and COM2/S27) All common outputs are VSS level Common outputs are scan drive waveform Common outputs are scan drive waveform http://onsemi.com 15 General-purpose port outputs (S1/P1 to S4/P4) All general-purpose port outputs are VSS level General-purpose outputs or PWM waveform General-purpose outputs or PWM waveform LC75843UGA Application Note The LCD system configuration example is LCD panel of the 1/2-duty drive used. Therefore, when set “1/2-duty drive mode (DT0=0 and DT1=1)”, the following figure shows the LCD drive waveform. VDD /INH input Display forced off Display on VSS VDD COM1 output 1/2 VDD VSS VSS VDD S27/COM2 output 1/2 VDD VSS VSS LCD driver output when all LCD segments corresponding to COM1 and COM2 are off. (When display data were set to “0, 0”) VDD VSS VSS VDD LCD driver output when only LCD segments corresponding to COM1 are on. (When display data were set to “1, 0”) VSS LCD driver output when only LCD segments corresponding to COM2 are on. (When display data were set to “0, 1”) VSS LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. (When display data were set to “1, 1”) VSS VSS VDD VSS VDD VSS All segments turn off mode SC=0 SC=1 Normal mode SC=0 Figure 11. LCD driver output waveform when SC is set (5) Power Saving Mode Setting (BU) The BU register can set the “Normal mode” or “Power saving mode”. The LC75843UGA built-in the “Power saving mode” as a low power consumption mode. When set the “Power saving mode”, the internal oscillator circuit is stopped, and external clock input is inhibited and common / segment output pins are outputted at the VSS level. However, the output pins from S1/P1 to S4/P4 can output of high level or low level as a general-purpose output function by “Display data setting registers (D1 to D8)”. (PWM output function is invalid) BU Low power consumption mode 0 Normal mode 1 Power saving mode Internal operating conditions Normal mode • When output pins from S1/P1 to S4/P4 set the general-purpose output port, the output pins from S1/P1 to S4/P4 can use only a general-purpose output function of high level or low level. • Segment output pins (S5 to S26, and S28) are VSS level. • Common output pins (COM1 and COM2/S27) are VSS level. • The internal oscillator circuit is stopped. • External clock input is inhibited. • The reception of serial control data is possible. (Registers are updated) http://onsemi.com 16 LC75843UGA Application Note Software Control Example of the LCD Controller (1) Timing Chart From Power-on State to LCD Display ON First, the following figure shows the timing waveform from power-on state to initial setting and LCD display ON in the LCD system configuration example. +5.0 [V] VDD t1 > 1 [ms] /INH tc > 10 [us] High Low CE CL DI Note 1 fo = 97.66 [Hz] Scan drive waveform output COM1 Display forced off (VSS level) Scan drive waveform output S27/COM2 Display forced off (VSS level) Turn off waveform output S5 Display forced off (VSS level) Turn off waveform output S6 Display forced off (VSS level) Turn off waveform output S7 Display forced off (VSS level) Turn off waveform output S24 Display forced off (VSS level) Turn off waveform output COM4/S25 Display forced off (VSS level) Turn off waveform output COM3/S26 S28 Display forced off (VSS level) Display forced off (VSS level) S1/P1 S2/P2 S3/P3 S4/P4 S28 pin unused (VSS level) Forced off (VSS level) Turn off waveform output (LED OFF) Forced off (VSS level) Turn off waveform output (LED OFF) Forced off (VSS level) Turn off waveform output (LED OFF) Forced off (VSS level) Turn off waveform output (LED OFF) (1) (2) (3) < Operation sequence > (1) Power-on. (2) The initial setting command is transferred after passage of “Serial data input wait time (t1 > 1 [ms])”. (3) The display forced off is cancelled by setting the /INH pin to High(VDD) after passage of “Command execute wait time (tc > 10 [us])”. < Transfer instruction data > Note 1 : CCB address = (44)h, D1 to D8= all “0” data, D9 to D54= all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=1,1,1,1,1,0 (Brightness is 50%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=0 and PS11=0 (S1/P1=Low level general-purpose output), PS20=0 and PS21=0 (S2/P2=Low level general-purpose output), PS30=0 and PS31=0 (S3/P3=Low level general-purpose output), PS40=0 and PS41=0 (S4/P4=Low level general-purpose output), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 17 LC75843UGA Application Note (2) Timing Chart of the LCD Display Contents Change Next, the following figure shows the timing waveform of the LCD display contents change. For example, when S5 segment corresponding to COM1 is ON and S6 segment corresponding to COM2 is ON, the following figures shows the segment to change. VDD +5.0 [V] /INH High CE CL DI Note 2 fo = 97.66 [Hz] Scan drive waveform output OFF ON OFF Scan drive waveform output ON OFF ON Turn off waveform output OFF ON OFF Turn off waveform output ON OFF ON Turn off waveform output OFF OFF OFF OFF OFF OFF Turn off waveform output OFF OFF OFF Turn off waveform output OFF OFF OFF COM1 S27/COM2 S5 S6 S7 Turn off waveform output S24 COM4/S25 COM3/S26 S28 S1/P1 S2/P2 S3/P3 S4/P4 S28 pin unused (VSS level) Turn off waveform output (LED OFF) Turn off waveform output (LED OFF) Turn off waveform output (LED OFF) Turn off waveform output (LED OFF) (4) < Operation sequence > (4) The command of the LCD display change is transferred. < Transfer instruction data > Note 2 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=1,1,1,1,1,0 (Brightness is 50%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=0 and PS11=0 (S1/P1=Low level general-purpose output), PS20=0 and PS21=0 (S2/P2=Low level general-purpose output), PS30=0 and PS31=0 (S3/P3=Low level general-purpose output), PS40=0 and PS41=0 (S4/P4=Low level general-purpose output), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 18 LC75843UGA Application Note (3) Timing Chart of the Setting to Turn on the LED of Backlight Next, the following figure shows the timing waveform of turn on the LED of backlight (Brightness is 100%) connecting to S4/P4 output pin. VDD +5.0 [V] /INH High CE CL DI Note 3 fo = 97.66 [Hz] Scan drive waveform output COM1 Scan drive waveform output S27/COM2 S5 S6 S7 S24 COM4/S25 COM3/S26 S28 S1/P1 S2/P2 S3/P3 S4/P4 S28 pin unused (VSS level) Low level general-purpose output (LED OFF) Low level general-purpose output (LED OFF) Low level general-purpose output (LED OFF) PWM output (PWM duty=64/64=100%) VDD Low level general-purpose output (LED OFF) (5) < Operation sequence > (5) The command of the LED control is transferred. < Transfer instruction data > Note 3 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=1,1,1,1,1,0 (Brightness is 50%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=0 and PS11=0 (S1/P1=Low level general-purpose output), PS20=0 and PS21=0 (S2/P2=Low level general-purpose output), PS30=0 and PS31=0 (S3/P3=Low level general-purpose output), PS40=1 and PS41=1 (S4/P4=PWM output function (ch3) setting), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 19 LC75843UGA Application Note (4) Timing Chart of the Setting to Turn on the LED of Button Indicator A Next, the following figure shows the timing waveform of turn on the LED of button indicator A (Brightness is 50%) connecting to S1/P1 output pin. VDD +5.0 [V] /INH High CE CL DI Note 4 fo = 97.66 [Hz] Scan drive waveform output COM1 Scan drive waveform output S27/COM2 S5 S6 S7 S24 COM4/S25 COM3/S26 S28 S28 pin unused (VSS level) fp = 234.37 [Hz] PWM output (PWM duty=32/64=50%) S1/P1 S2/P2 S3/P3 S4/P4 Low level general-purpose output (LED OFF) Low level general-purpose output (LED OFF) Low level general-purpose output (LED OFF) PWM output (PWM duty=64/64=100%) VDD (6) < Operation sequence > (6) The command of the LED control is transferred. < Transfer instruction data > Note 4 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=1,1,1,1,1,0 (Brightness is 50%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=1 and PS11=1 (S1/P1=PWM output function (ch1) setting), PS20=0 and PS21=0 (S2/P2=Low level general-purpose output), PS30=0 and PS31=0 (S3/P3=Low level general-purpose output), PS40=1 and PS41=1 (S4/P4=PWM output function (ch3) setting), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 20 LC75843UGA Application Note (5) Timing Chart of the Setting to Turn on the LED of Button Indicator B Next, the following figure shows the timing waveform of turn off the LED of button indicator A connecting to S1/P1 output pin, and turn on the LED of button indicator B (Brightness is 50%) connecting to S2/P2 output pin. VDD +5.0 [V] /INH High CE CL DI Note 5 fo = 97.66 [Hz] Scan drive waveform output COM1 Scan drive waveform output S27/COM2 S5 S24 COM4/S25 COM3/S26 S28 S28 pin unused (VSS level) fp = 234.37 [Hz] PWM output (PWM duty=32/64=50%) Low level general-purpose output (LED OFF) S1/P1 PWM output (PWM duty=32/64=50%) S2/P2 S3/P3 S4/P4 Low level general-purpose output (LED OFF) Low level general-purpose output (LED OFF) PWM output (PWM duty=64/64=100%) VDD (7) < Operation sequence > (7) The command of the LED control is transferred. < Transfer instruction data > Note 5 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=1,1,1,1,1,0 (Brightness is 50%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=0 and PS11=0 (S1/P1=Low level general-purpose output), PS20=1 and PS21=0 (S2/P2=PWM output function (ch1) setting), PS30=0 and PS31=0 (S3/P3=Low level general-purpose output), PS40=1 and PS41=1 (S4/P4=PWM output function (ch3) setting), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 21 LC75843UGA Application Note (6) Timing Chart of the Setting to Turn on the LED of Button Indicator A to C Next, the following figure shows the timing waveform of turn on the LED of button indicator A to C connecting to S1/P1 to S3/P3 output pin. VDD +5.0 [V] /INH High CE CL DI Note 6 fo = 97.66 [Hz] Scan drive waveform output COM1 Scan drive waveform output S27/COM2 S5 S24 COM4/S25 COM3/S26 S28 S28 pin unused (VSS level) fp = 234.37 [Hz] PWM output (PWM duty=32/64=50%) S1/P1 Low level general-purpose output (LED OFF) PWM output (PWM duty=32/64=50%) S2/P2 PWM output (PWM duty=32/64=50%) S3/P3 S4/P4 Low level general-purpose output (LED OFF) PWM output (PWM duty=64/64=100%) VDD (8) < Operation sequence > (8) The command of the LED control is transferred. < Transfer instruction data > Note 6 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=1,1,1,1,1,0 (Brightness is 50%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=1 and PS11=1 (S1/P1=PWM output function (ch1) setting), PS20=1 and PS21=0 (S2/P2=PWM output function (ch1) setting), PS30=0 and PS31=1 (S3/P3=PWM output function (ch2) setting), PS40=1 and PS41=1 (S4/P4=PWM output function (ch3) setting), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 22 LC75843UGA Application Note (7) Timing Chart of the Setting to Change the Brightness of the LED Next, the following figure shows the timing waveform of the LED brightness change (Brightness is 79.69%) of button indicator C connecting to S3/P3 output pin. VDD +5.0 [V] /INH High CE CL DI Note 7 fo = 97.66 [Hz] Scan drive waveform output COM1 Scan drive waveform output S27/COM2 S5 S24 COM4/S25 COM3/S26 S28 S28 pin unused (VSS level) fp = 234.37 [Hz] PWM output (PWM duty=32/64=50%) S1/P1 PWM output (PWM duty=32/64=50%) S2/P2 PWM output (PWM duty=51/64=79.69%) PWM output (PWM duty=32/64=50%) S3/P3 S4/P4 PWM output (PWM duty=64/64=100%) VDD (9) < Operation sequence > (9) The command of the LED control is transferred. < Transfer instruction data > Note 7 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=0,1,0,0,1,1 (Brightness is 79.69%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=1 and PS11=1 (S1/P1=PWM output function (ch1) setting), PS20=1 and PS21=0 (S2/P2=PWM output function (ch1) setting), PS30=0 and PS31=1 (S3/P3=PWM output function (ch2) setting), PS40=1 and PS41=1 (S4/P4=PWM output function (ch3) setting), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=0 (“All segment turn off mode” was cancelled), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 23 LC75843UGA Application Note (8) Timing Chart of the Setting to Turn off the Segments and Turn off the LED of Backlight Next, the following figure shows the timing waveform of the display OFF (turn off the all segments) and turn off the LED of backlight. VDD +5.0 [V] /INH High CE CL DI Note 8 fo = 97.66 [Hz] Scan drive waveform output COM1 Scan drive waveform output S27/COM2 Turn off waveform output S5 Turn off waveform output S6 Turn off waveform output S7 Turn off waveform output S24 Turn off waveform output COM4/S25 Turn off waveform output COM3/S26 S28 S28 pin unused (VSS level) fp = 234.37 [Hz] PWM output (PWM duty=32/64=50%) S1/P1 PWM output (PWM duty=32/64=50%) S2/P2 PWM output (PWM duty=51/64=79.69%) S3/P3 S4/P4 PWM output (PWM duty=64/64=100%) VDD Low level general-purpose output (LED OFF) (10) < Operation sequence > (10) The command of the turn off the segments and turn off the LED of backlight setting is transferred. < Transfer instruction data > Note 8 : CCB address = (44)h, D1 to D8=all “0” data, D9=1, D10=0, D11=0, D12=1, D13 to D54=all “0” data, DT0=0 and DT1=1 (1/2-duty), W10 to W15=1,1,1,1,1,0 (Brightness is 50%), W20 to W25=0,1,0,0,1,1 (Brightness is 79.69%), W30 to W35=1,1,1,1,1,1 (Brightness is 100%), PF0=0, PF1=1, PF2=0 and PF3=0 (fp=234.37 [Hz]), PS10=1 and PS11=1 (S1/P1=PWM output function (ch1) setting), PS20=1 and PS21=0 (S2/P2=PWM output function (ch1) setting), PS30=0 and PS31=1 (S3/P3=PWM output function (ch2) setting), PS40=0 and PS41=0 (S4/P4=Low level general-purpose output), P0=1, P1=0 and P2=0 (S1/P1 to S4/P4 are set by general-purpose output port (P1 to P4)), FC0=0, FC1=1, FC2=0 and FC3=1 (fo=97.66 [Hz]), DN=0 (S28 pin unused), EXF=0 and OC=0 (Internal oscillator operating mode), SC=1 (Set the “All segment turn off mode”), BU=0 (“Power saving mode” was cancelled). http://onsemi.com 24 LC75843UGA Application Note (9) Timing Chart from LCD Display OFF to Power-off State Finally, the following figure shows the timing waveform to set by power-off state from LCD display OFF. VDD +5.0 [V] t2 > 0 [ms] /INH High CE Low CL Low DI Low Low fo = 97.66 [Hz] Scan drive waveform output Display forced off (VSS level) COM1 Scan drive waveform output Display forced off (VSS level) S27/COM2 Turn off waveform output Display forced off (VSS level) S5 Turn off waveform output Display forced off (VSS level) S6 Turn off waveform output Display forced off (VSS level) S7 Turn off waveform output Display forced off (VSS level) S24 Turn off waveform output Display forced off (VSS level) COM4/S25 Turn off waveform output Display forced off (VSS level) COM3/S26 S28 S28 pin unused (VSS level) Display forced off (VSS level) fp = 234.37 [Hz] PWM output (PWM duty=32/64=50%) Forced off (VSS level) S1/P1 PWM output (PWM duty=32/64=50%) Forced off (VSS level) S2/P2 PWM output (PWM duty=51/64=79.69%) Forced off (VSS level) S3/P3 S4/P4 Low level general-purpose output Forced off (VSS level) (11) < Operation sequence > (11) The display forced off is set by setting the /INH pin to Low (VSS). (12) Power-off. http://onsemi.com 25 (12) LC75843UGA Application Note Application Circuit (1) In the Case of the LCD System Configuration Using the LCD Panel of 46 Segments VOUP (Pull-up power supply for LED) LCD Driver IC (LC75843UGA) +5.0 [V] S1/P1 (Button indicator A) S2/P2 (Button indicator B) S3/P3 (Button indicator C) VDD VSS S4/P4 OSCI (Backlight) 23 LCD Controller /INH CE CL DI 3 (CCB interface) S5 to S24 COM4/S25 COM3/S26 S28 LCD Panel (2com x 23seg = 46 segments) S27/COM2 COM1 Figure 12. LCD system configuration using the LCD panel of 46 segments The LC75843UGA is able to drive up to 46 segments the LCD panel of the 1/2-duty when the output pins from S1/P1 to S4/P4 used general-purpose output ports (P1 to P4). The following explains a setting method example of serial control data in this case. This system sets DT0=0 and DT1=1 to use an LCD panel of the 1/2-duty drive. DT0 DT1 LCD drive type 0 1 0 1 0 0 1 1 1/4-duty and 1/3-bias drive type 1/3-duty and 1/3-bias drive type 1/2-duty and 1/2-bias drive type Static (1/1-duty) drive type COM1 COM1 COM1 COM1 COM1 Output pins state COM2/S27 COM3/S26 COM4/S25 COM2 COM3 COM4 COM2 COM3 S25 COM2 S26 S25 S27 S26 S25 This system sets DN=1 to use S28 output terminal as the segment output. DN 0 1 S28 output pin state VSS level output S28 segment output This system sets LCD display data from D9 to D54 to use LCD segments from S5 to S26, and S28. In addition, the pins from S1/P1 to S4/P4 use general-purpose output port function. Therefore, sets the general-purpose output ports (P1 to P4) of high level output or low level output by D1 to D8. When sets the “1/2-duty drive mode”, the following table shows the relation between the Display data setting registers (D9 to D54) and the segment outputs and the common outputs. Output pin COM1 COM2/S27 Output pin COM1 COM2/S27 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 S17 S18 S19 S20 S21 S22 S23 S24 COM4/S25 COM3/S26 S28 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 D54 http://onsemi.com 26 LC75843UGA Application Note This system sets output pins from S1/P1 to S4/P4 to a general-purpose output port and controls LED. Therefore, this system sets P0=1, P1=0 and P2=0. P0 P1 P2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output pin state S2/P2 S3/P3 S2 S3 S2 S3 P2 S3 P2 P3 P2 P3 S2 S3 S2 S3 S2 S3 S1/P1 S1 P1 P1 P1 P1 S1 S1 S1 S4/P4 S4 S4 S4 S4 P4 S4 S4 S4 S1 to S4 : Segment output ports P1 to P4 : General-purpose output ports The registers of the PS10 and PS11 can set the “General-purpose output function”, “Clock output function”, or “PWM output function” of the general-purpose output port (P1). In addition, the registers of the PS20, PS21, PS30, PS31, PS40 and PS41 can set the “General-purpose output function” or “PWM output function” of the generalpurpose output ports (P2, P3 and P4). The general-purpose output function outputs general-purpose output ports (P1 to P4) of high level or low level by “Display data setting registers (D1, D3, D5 and D7)”. The PWM output function can set the pulse width of the PWM output by “PWM duty setting register (W10 to W15, W20 to W25 and W30 to W35)”. The PWM duty setting has up to 3ch and can perform brightness adjustment of the LED individually for each channel. The setting method about the registers except the above is the same as “Explanation of the LCD drive control”, “Explanation of the LED Control by General-purpose Output Ports” and “Explanation of the Instruction Data”. (2) In the Case of the LCD System Configuration Using the LCD Panel of 48 Segments VOUP (Pull-up power supply for LED) LCD Driver IC (LC75843UGA) +5.0 [V] S1/P1 (Button indicator A) S2/P2 (Button indicator C) VDD VSS S3/P3 (Backlight) OSCI 24 P4/S4 LCD Controller /INH 3 (CCB interface) CE CL DI S5 to S24 COM4/S25 COM3/S26 S28 S27/COM2 COM1 LCD Panel (2com x 24seg = 48 segments) Figure 13. LCD system configuration using the LCD panel of 48 segments The output pins from S1/P1 to S4/P4 of the LC75843UGA can set the “Segment output port” or “General-purpose output port”. This IC is able to drive up to 48 segments the LCD panel of the 1/2-duty when the output pins from S1/P1 to S3/P3 used general-purpose output ports (P1 to P3) and the S4/P4 output pin used segment output port (S4). The following explains a setting method example of serial control data in this case. http://onsemi.com 27 LC75843UGA Application Note This system sets DT0=0 and DT1=1 to use an LCD panel of the 1/2-duty drive. DT0 DT1 LCD drive type 0 1 0 1 0 0 1 1 1/4-duty and 1/3-bias drive type 1/3-duty and 1/3-bias drive type 1/2-duty and 1/2-bias drive type Static (1/1-duty) drive type COM1 COM1 COM1 COM1 COM1 Output pins state COM2/S27 COM3/S26 COM4/S25 COM2 COM3 COM4 COM2 COM3 S25 COM2 S26 S25 S27 S26 S25 This system sets DN=1 to use S28 output terminal as the segment output. DN 0 1 S28 output pin state VSS level output S28 segment output This system sets LCD display data from D7 to D54 to use LCD segments from S4 to S26, and S28. In addition, the pins from S1/P1 to S3/P3 use general-purpose output port function. Therefore, sets the general-purpose output ports (P1 to P3) of high level output or low level output by D1 to D6. When sets the “1/2-duty drive mode”, the following table shows the relation between the Display data setting registers (D7 to D54) and the segment outputs and the common outputs. Output pin COM1 COM2/S27 Output pin COM1 COM2/S27 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 S16 S17 S18 S19 S20 S21 S22 S23 S24 COM4/S25 COM3/S26 S28 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 D32 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 D54 When the S1/P1 to S3/P3 output pins used general-purpose output ports (P1 to P3) and when the S4/P4 output pin used segment output port (S4), this system sets P0=0, P1=1 and P2=1. P0 P1 P2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 S1/P1 S1 P1 P1 P1 P1 S1 S1 S1 Output pin state S2/P2 S3/P3 S2 S3 S2 S3 P2 S3 P2 P3 P2 P3 S2 S3 S2 S3 S2 S3 S4/P4 S4 S4 S4 S4 P4 S4 S4 S4 S1 to S4 : Segment output ports P1 to P4 : General-purpose output ports The registers of the PS10 and PS11 can set the “General-purpose output function”, “Clock output function”, or “PWM output function” of the general-purpose output port (P1). In addition, the registers of the PS20, PS21, PS30 and PS31 can set the “General-purpose output function” or “PWM output function” of the general-purpose output ports (P2 and P3). The general-purpose output function outputs general-purpose output ports (P1 to P3) of high level or low level by “Display data setting registers (D1, D3 and D5)”. This system does not use the registers of the PS40 and PS41. Therefore, those set all “0”. The setting method about the registers except the above is the same as “Explanation of the LCD drive control”, “Explanation of the LED Control by General-purpose Output Ports” and “Explanation of the Instruction Data”. http://onsemi.com 28 LC75843UGA Application Note (3) In the Case of the LCD System Configuration Using the LCD Panel of 54 Segments LCD Driver IC (LC75843UGA) +5.0 [V] VDD VSS 27 P1/S1 P2/S2 P3/S3 P4/S4 OSCI S5 to S24 S25/COM4 S26/COM3 S28 LCD Controller /INH CE CL DI 3 (CCB interface) LCD Panel (2com x 27seg = 54 segments) S27/COM2 COM1 Figure 14. LCD system configuration using the LCD panel of 54 segments The LC75843UGA is able to drive up to 54 segments the LCD panel of the 1/2-duty when the output pins from S1/P1 to S4/P4 used segment output ports (S1 to S4). The following explains a setting method example of serial control data in this case. This system sets DT0=0 and DT1=1 to use an LCD panel of the 1/2-duty drive. DT0 DT1 LCD drive type 0 1 0 1 0 0 1 1 1/4-duty and 1/3-bias drive type 1/3-duty and 1/3-bias drive type 1/2-duty and 1/2-bias drive type Static (1/1-duty) drive type COM1 COM1 COM1 COM1 COM1 Output pins state COM2/S27 COM3/S26 COM4/S25 COM2 COM3 COM4 COM2 COM3 S25 COM2 S26 S25 S27 S26 S25 This system sets DN=1 to use S28 output terminal as the segment output. DN 0 1 S28 output pin state VSS level output S28 segment output This system sets LCD display data from D1 to D54 to use LCD segments from S1 to S26, and S28. When sets the “1/2-duty drive mode”, the following table shows the relation between the Display data setting registers (D1 to D54) and the segment outputs and the common outputs. Output pin COM1 COM2/S27 Output pin COM1 COM2/S27 S1/P1 S2/P2 S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 COM4/S25 COM3/S26 S28 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 D30 D32 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 D54 http://onsemi.com 29 LC75843UGA Application Note This system sets output pins from S1/P1 to S4/P4 to a segment output port and drives LCD segment. Therefore this system sets P0=0, P1=0 and P2=0. P0 P1 P2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output pin state S2/P2 S3/P3 S1/P1 S1 P1 P1 P1 P1 S1 S1 S1 S2 S2 P2 P2 P2 S2 S2 S2 S4/P4 S3 S3 S3 P3 P3 S3 S3 S3 S4 S4 S4 S4 P4 S4 S4 S4 S1 to S4 : Segment output ports P1 to P4 : General-purpose output ports This system does not use the registers of the PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, W10 to W15, W20 to W25, W30 to W35, and PF0 to PF3. Therefore, those set all “0”. The setting method about the registers except the above is the same as “Explanation of the LCD drive control”, “Explanation of the LED Control by General-purpose Output Ports” and “Explanation of the Instruction Data”. (4) In the Case of the LCD System Configuration to Input an External Clock (300kHz) VOUP (Pull-up power supply for LED) LCD Driver IC (LC75843UGA) +5.0 [V] S1/P1 (Button indicator A) S2/P2 (Button indicator B) S3/P3 (Button indicator C) VDD VSS S4/P4 (Backlight) 18 OSCI LCD Controller /INH 3 (CCB interface) CE CL DI S5 to S22 S23 S24 COM4/S25 COM3/S26 S28 (open) (open) (open) (open) (open) S27/COM2 COM1 LCD Panel (2com x 18seg = 36 segments) Figure 15. LCD system configuration to input an external clock (300kHz) The LC75843UGA is able to set the “Internal oscillator operating mode” or “External clock input operating mode”. Furthermore, this IC can set the division ratio a clock to input from OSCI pin becomes 300 [kHz](Typ.) or 38 [kHz](Typ.). However, when set the “External clock 38kHz input mode (OC=1 and EXF=1)”, please be careful because PWM output function is invalidity. The reason why a customer selects the LCD system configuration using the “External clock input operating mode” is because the characteristic of the internal oscillator clock frequency (fosc) is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore the customer may worry about the flicker of the liquid crystal display occurring by interference with other frequency. Furthermore, there may be a customer hoping to lower clock frequency more because of the low power consumption and EMI (Electro Magnetic Interference) measures, etc. http://onsemi.com 30 LC75843UGA Application Note First of all, the following table shows the pin explanation of the external clock input pin (OSCI) and the specifications of the allowable operating ranges. Pin name Pin function External clock input pin. When “Internal oscillator operating mode (OC=0)”, make sure to connect OSCI to GND. When “External clock input mode (OC=1)”, OSCI is used to input the external clock. OSCI Allowable operating ranges at Ta= -40°C to +105°C, VSS=0V Parameter Symbol Conditions Min. Typ. Max. Unit 6.3 V Power Supply Voltage VDD VDD 4.5 Input High Level Voltage VIH2 OSCI 0.4 VDD 6.3 V Input Low Level Voltage VIL2 OSCI 0 0.2 VDD V External Clock input Frequency fck OSCI, External clock input operating mode 10 300 600 kHz External Clock Duty Ratio Dck OSCI, External clock input operating mode 30 50 70 % These specifications show an example, and, we have a case to change these specifications without a notice for improvement. Therefore, it is not guaranteed for design as the mass production equipment. When designing equipment, refer to the “Delivery specification for the LC75843UGA”. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. The following explains a setting method example of serial control data in this case. This system sets OC=1 and EXF=0 to use the “External clock 300kHz input mode” OC 0 1 1 EXF 0/1 0 1 Fundamental clock operating mode Internal oscillator operating mode External clock 300kHz input mode External clock 38kHz input mode OSCI input pin state Connect to GND Inputs a clock of 300 [kHz](Typ.) Inputs a clock of 38 [kHz](Typ.) The registers from FC0 to FC3 can set the frame frequency (fo) of the common and segment output waveform. When sets OC=1 and EXF=0, the following table shows the frame frequency of the LCD drive waveform. FC0 FC1 FC2 FC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 External clock 300kHz input operating mode (OC=1, EXF=0) LCD drive waveform frame frequency fo [Hz] LCD drive waveform frame ratio (External clock input frequency is fck=300 [kHz](typ.)) fck / 6144 48.83 fck / 5376 55.80 fck / 4608 65.10 fck / 3840 78.12 fck / 3456 86.80 fck / 3072 97.66 fck / 2688 111.61 fck / 2304 130.21 fck / 2112 142.04 fck / 1920 156.25 fck / 1728 173.61 fck / 1536 195.31 fck / 1344 223.21 fck / 1152 260.42 fck / 960 312.50 fck / 768 390.62 The explanation mentioned above is used only to explain internal operation and how to IC, and the characteristic of the products is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. http://onsemi.com 31 LC75843UGA Application Note The registers from PF0 to PF3 can set the PWM output frame frequency (fp) of the general-purpose output port. When sets OC=1 and EXF=0, the following table shows the frame frequency of the PWM output waveform. PF0 PF1 PF2 PF3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 External clock 300kHz input operating mode (OC=1, EXF=0) PWM output waveform frame frequency fp [Hz] PWM output waveform frame ratio (External clock input frequency is fck=300 [kHz](typ.)) fck / 1536 195.31 fck / 1408 213.07 fck / 1280 234.37 fck / 1152 260.42 fck / 1024 292.97 fck / 896 334.82 fck / 768 390.62 fck / 640 468.75 fck / 512 585.94 fck / 384 781.25 fck / 256 1171.87 fck / 896 334.82 fck / 896 334.82 fck / 896 334.82 fck / 896 334.82 fck / 896 334.82 The explanation mentioned above is used only to explain internal operation and how to IC, and the characteristic of the products is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. The setting method about the registers except the above is the same as “Explanation of the LCD drive control”, “Explanation of the LED Control by General-purpose Output Ports” and “Explanation of the Instruction Data”. (5) In the Case of the LCD System Configuration to Input an External Clock (38kHz) LCD Driver IC (LC75843UGA) +5.0 [V] VDD VSS P1/S1 (open) P2/S2 (open) P3/S3 (open) P4/S4 (open) 18 OSCI LCD Controller /INH 3 (CCB interface) CE CL DI S5 to S22 S23 S24 COM4/S25 COM3/S26 S28 (open) (open) (open) (open) (open) S27/COM2 COM1 LCD Panel (2com x 18seg = 36 segments) Figure 16. LCD system configuration to input an external clock (38kHz) The LC75843UGA is able to set the “Internal oscillator operating mode” or “External clock input operating mode”. Furthermore, this IC can set the division ratio a clock to input from OSCI pin becomes 300 [kHz](Typ.) or 38 [kHz](Typ.). However, when set the “External clock 38kHz input mode (OC=1 and EXF=1)”, please be careful because PWM output function is invalidity. http://onsemi.com 32 LC75843UGA Application Note The following explains a setting method example of serial control data in this case. This system sets OC=1 and EXF=1 to use the “External clock 38kHz input mode” OC 0 1 1 EXF 0/1 0 1 Fundamental clock operating mode Internal oscillator operating mode External clock 300kHz input mode External clock 38kHz input mode OSCI input pin state Connect to GND Inputs a clock of 300 [kHz](Typ.) Inputs a clock of 38 [kHz](Typ.) The registers from FC0 to FC3 can set the frame frequency (fo) of the common and segment output waveform. When sets OC=1 and EXF=1, the following table shows the frame frequency of the LCD drive waveform. FC0 FC1 FC2 FC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 External clock 38kHz input operating mode (OC=1, EXF=1) LCD drive waveform frame frequency fo [Hz] LCD drive waveform frame ratio (External clock input frequency is fck=38 [kHz](typ.)) fck / 768 49.48 fck / 672 56.55 fck / 576 65.97 fck / 480 79.16 fck / 432 87.96 fck / 384 98.96 fck / 336 113.09 fck / 288 131.94 fck / 264 143.94 fck / 240 158.33 fck / 216 175.92 fck / 192 197.92 fck / 168 226.19 fck / 144 263.89 fck / 120 316.67 fck / 96 395.83 The explanation mentioned above is used only to explain internal operation and how to IC, and the characteristic of the products is uneven by a production variation and the terms of use of the IC (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. This system sets output pins from S1/P1 to S4/P4 to a segment output port and drives LCD segment. Therefore this system sets P0=0, P1=0 and P2=0. P0 P1 P2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 S1/P1 S1 P1 P1 P1 P1 S1 S1 S1 Output pin state S2/P2 S3/P3 S2 S2 P2 P2 P2 S2 S2 S2 S3 S3 S3 P3 P3 S3 S3 S3 S4/P4 S4 S4 S4 S4 P4 S4 S4 S4 S1 to S4 : Segment output ports P1 to P4 : General-purpose output ports This system does not use the registers of the PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, W10 to W15, W20 to W25, W30 to W35, and PF0 to PF3. Therefore, those set all “0”. The setting method about the registers except the above is the same as “Explanation of the LCD drive control”, “Explanation of the LED Control by General-purpose Output Ports” and “Explanation of the Instruction Data”. When LED control is necessary for the LCD system configuration example of the “External clock 38kHz input mode”, the output pins from S1/P1 to S4/P4 are set the general-purpose output ports (P1 to P4), and if it is only setting of ON (Brightness is 100%) or OFF of the LED, it can be set. Then, this system controls LED by generalpurpose output port of the output pins from S1/P1 to S4/P4, therefore, this system sets P0=1, P1=0 and P2=0. In addition, the general-purpose output port (P4) uses the general-purpose output function, therefore, this system sets PS40=0 and PS41=0. Finally, the general-purpose output port (P4) outputs high level (LED turns on with 100% of brightness) or low level (turn off the LED) by the “Display data setting register (D7)”. http://onsemi.com 33 LC75843UGA Application Note LCD Driver IC (LC75843UGA) VOUP +5.0 [V] VDD S1/P1 (open) S2/P2 (open) VSS S3/P3 (open) (Pull-up power supply for LED) S4/P4 (Backlight) S5 to S22 S23 S24 COM4/S25 COM3/S26 S28 OSCI LCD Controller /INH 3 (CCB interface) CE CL DI 18 (open) (open) (open) (open) (open) LCD Panel (2com x 18seg = 36 segments) S27/COM2 COM1 Figure 17. LED control by the LCD system configuration to input an external clock (38kHz) (6) In the Case of the LCD System Configuration Using two LCD Panels. LCD Driver IC (A) (LC75843UGA) +5.0 [V] P1/S1 P2/S2 P3/S3 P4/S4 VDD VSS LCD Controller OSCI /INH CEA CEB CL DI 20 S5 to S24 COM4/S25 COM3/S26 S28 OSCI /INH CE CL DI (CCB interface) LCD Panel (A) (2com x 27seg = 54 segments) S27/COM2 COM1 LCD Driver IC (B) (LC75843UGA) P1/S1 P2/S2 P3/S3 P4/S4 VDD VSS OSCI /INH CE CL DI 20 S5 to S24 COM4/S25 COM3/S26 S28 (CCB interface) S27/COM2 COM1 LCD Panel (B) (2com x 27seg = 54 segments) Figure 18. LCD system configuration using two LCD panels In the case of the system configuration using two LCD panels, the CL and DI signal of the CCB interface are input from an LCD controller into both LC75843UGA and are controlled at the same time, and the CE signal of the CCB interface is input from an LCD controller into LC75843UGA separately and is controlled separately. http://onsemi.com 34 LC75843UGA Application Note /INH Display forced off Display on CEA CEB CL DI Initialization of IC(A) Internal data of the IC(A) Undefined Internal data of the IC(B) Undefined The display data of IC(B) is changed Initialization of IC(B) The display data of IC(A) is changed Defined Changed Defined Changed Figure 19. Control example of the LCD system configuration using two LCD panels When serial control data is transferred for LCD driver IC(A), the “Chip enable A (CEA)” signal is set to control signal, and the “chip enable B (CEB)” signal is held to low level. When serial control data is transferred for LCD driver IC(B), the “Chip enable A (CEA)” signal is held to low level, and the “Chip enable B (CEB)” signal is set to control signal. Even if a control signal is input into CL and DI, the internal data of the LCD driver IC are not changed if CE signal is heldd to low level. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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