NCN49599 D

NCN49599
Product Preview
Power Line Communication
Modem
The NCN49599 is a powerful spread frequency shift keying
(S−FSK) communication system−on−chip (SoC) designed for
communication in hostile environments.
It combines a low power ARM Cortex M0 processor with a high
precision analogue front end and a robust line driver. Based on 4800
baud S−FSK dual−channel technology, it offers an ideal compromise
between speed and robustness.
It is functionally compatible with the NCN49597 and NCS5651
chip set, offering frequencies to cover all CENELEC bands for use in
applications such as e−metering, home automation and street lighting.
The NCN49599 benefits for more than 10 years of field experience in
e−metering and delivers innovative features such as a smart
synchronization and in−band statistics.
Fully reprogrammable, the modem firmware can be updated in the
field. Multiple royalty−free firmware options are available from
ON Semiconductor; refer to the separate datasheets for details. The
configurable GPIOs allow connecting peripherals such as LCDs or
metering ICs.
Features
• Power Line Communication (PLC) Modem for 50 Hz, 60 Hz and DC
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1 56
QFN56 8x8, 0.5P
CASE 485CN
MARKING DIAGRAMS
56
1
ON
ARM
NCN49599
0C599−001
AWLYYWWG
e3
Mains
A
= Assembly Location
• Embedded Highly Linear 2−stage Power Amplifier with Current
WL
= Wafer Lot Traceability
YYWW = Date Code
Limitation, Thermal Protection, Enable/Shutdown Control,
G
= Green Designator
Rail−to−rail Drop of only ±1 V at Iout = 1.5 A
• Embedded ARM Cortex M0 Processor
• 8 General−purpose IOs Controllable by Software
ORDERING INFORMATION
See detailed ordering and shipping information in the package
• Embedded 32 kB RAM; Embedded 2 kB ROM
dimensions section on page 33 of this data sheet.
• Hardware Compliant with CENELEC EN 50065−1 and EN 50065−7
• Half Duplex S−FSK Channel, Data Rate Selectable:
300 – 600 – 1200 – 2400 – 4800 baud (@ 50 Hz);
360 – 720 – 1440 – 2880 – 5760 baud (@ 60 Hz)
• Programmable Carrier Frequencies in CENELEC A, B,
• Complete Handling of Protocol Layers (physical,
C and D Band
MAC, LLC)
• UART for Interfacing with an Application
• Repetition Boosting Robustness and Range of the
Microcontroller
Communication (IEC firmware)
• Power Supply 3.3 V and 12 V
Typical Applications
• Wide Junction Temperature Range: −40°C to +125°C
• AMR: Remote Automated Meter Reading
• Building Automation
Available Firmware Options
• IEC − Fully IEC61334−5−1, IEC 61334−4−32 and
• Solar Power Control and Monitoring
Linky Compliant
• Street Light Control and Monitoring
• ON PL110 − Mesh Networking with Collision
• Transmission of Alerts (fire, gas leak, water leak)
Avoidance and Error Correction
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. P4
1
Publication Order Number:
NCN49599/D
NCN49599
APPLICATION
Application Example
JTAG
Interface
3V3_D
Meter
Interface
+12
D7
3V3_A
R19
3V3_D
C19
C18
C3
R3
R1
TX_OUT
A−
D1
+12
A_OUT
R4
R6
B−
R12
C4
R14
C10
C11
B_OUT
R7
+12
D2
41 39
49
VDD
43
6
VDD
VDDA
53
A+
C6
R8
B+
R10
RX_OUT
1:2
C7
D3
12, 13, 14, 20
15, 16
26
52
35
1
34
54, 55
37
2
38
NCN49599
30
45
C8
MAINS
REF_OUT
RXD
BR0
BR1
Application
mController
RESB
TEST
SDO
SDI
SCK
46
28
31
CSB
47
33
SEN
R11
D4
R18
TXD
50
29
RX_IN
3V3_D
U1
25
51
R9
Tr1
C16
27
R5
R13
VCC
C1
C5
+12
ENB
C2
C17
TXD/PRES
TX_ENB
R2
Optional
External
Flash
C9
8, 9, 10, 11,
17, 18, 36
R16
R17
22
21
XIN
56
VEE
3
VEE
VSS
24
VSS
7
Y1
C13
C14
GPIO bus
19
EXT_CLK_EN
C12
3V3_D
44
VSSA
R15
23
VDD1V8
ZC_IN
D5
5
4
RLIM
48
XOUT
42
ILIM
ALC_IN
3V3_A
C15
D6
Figure 1. Typical Application for the NCN49599 S−FSK Modem
Figure 1 shows an S−FSK PLC modem built around the
NCN49599. The design is a good starting point for a
CENELEC. EN 50065−1−compliant system; for further
information refer to the design manual in [1].
This design is not galvanically isolated; safety must be
considered when interfacing to a microcontroller or a PC.
For synchronization the mains is coupled in via a 1 MW
resistor; the Schottky diode pair D5 clamps the voltage
within the input range of the zero crossing detector.
In the receive path a 2nd order high pass filter blocks the
mains frequency. The corner point − defined by C7, C8, R10
and R11 − is designed at 10 kHz. In the transmit path a 3rd
order low pass filter built around the internal power
operational amplifier suppresses the 2nd and 3rd harmonics
to be in line with the CENELEC EN50065−1 specification.
The filter components are tuned for a space and mark
frequency of 63.3 and 74 kHz respectively, typically for
e−metering in the CENELEC A−band. The output of the
amplifier is coupled via a DC blocking capacitor C10 to a 2:1
transformer Tr1. The high voltage capacitor C11 couples the
secondary of this transformer to the mains. High−energetic
transients from the mains are clamped by the protection
diode combination D3, D4, together with D1, D2.
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NCN49599
Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component
Function and Remarks
Value
Tolerance
Unit
C1
TX_OUT signal coupling
470
±20%
nF
C2
Low pass transmit filter
470
±10%
pF
C3
Low pass transmit filter
68
±10%
pF
C4
Low pass transmit filter
3
±10%
pF
C5
Low pass transmit filter
2.7
±10%
nF
Supply decoupling
100
−20 +80%
nF
C6, C16, C17, C18, C19
C7, C8
High pass receive filter
1
±10%
nF
C9, C13
Internal 1.8 V supply decoupling; ceramic
10
−20 +80%
mF
C10
Transmission signal coupling; 1 A rms ripple @ 70 kHz
10
±20%
mF
C11
High Voltage coupling; 630 VDC
220
±20%
nF
C12
Zero Cross noise suppression
100
±20%
pF
C14, C15
Crystal load capacitor
36
±20%
pF
R1
Low pass receive filter
3.3
±1%
kW
R2
Low pass receive filter
8.2
±1%
kW
R3, R9,
Low pass transmit and high pass receive filter;
10
±1%
kW
R7, R8
Amplifier bias
10
±1%
kW
R12, R13
Receive mode input bias
10
±1%
kW
R18, R19
Pull up
10
±1%
kW
R4
Low pass transmit filter
3
±1%
kW
R5
Low pass transmit filter
1
±1%
kW
R6
Low pass transmit filter
1.6
±1%
kW
R10
High pass receive filter
15
±1%
kW
R11
High pass receive filter
30
±1%
kW
R14
Line transients protection; 0.5 W
0.47
±1%
W
R15
Zero crossing coupling
1
±5%
MW
R16
Current protection
5
±1%
kW
R17
ILIM LED bias
3.3
±5%
kW
D1, D2
High−current Schottky clamp diodes
D3, D4
Unidirectional TVS
MBRA340
P6SMB6.8AT3G
D5
Dual low−current Schottky clamp diode
D6
ILIM LED indication (optional)
D7
TVS
Y1
Crystall
Tr1
2:1 signal transformer
U1
PLC modem
BAS70−04
LED
1SMA12CA
48 MHz
NCN49599
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3
50 ppm
NCN49599
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Absolute maximum power amplifier supply
VCC_ABSM
VEE − 0.3
13.2
V
Absolute maximum digital amplifier power supply
VDD_ABSM
VSS − 0.3
3.9
V
POWER SUPPLY PINS VCC, VDD, VDD2, VDDA, VSS, VSSA
Absolute maximum digital modem power supply
VDD_ABSM
VSS − 0.3
3.9
V
Absolute maximum analog power supply
VDDA_ABSM
VSSA − 0.3
3.9
V
Absolute maximum difference between digital and analog power supply
VDD − VDDA_ABSM
−0.1
0.1
V
Absolute maximum difference between digital and analog ground
VSS − VSSA_ABSM
−0.1
0.1
V
Absolute maximum difference between digital and power ground
VSS − VEE_ABSM
−0.5
0.5
V
VXIN_ABSM18
VSS − 0.2
VDD18 + 0.2
V
VXOUT_ABSM18
VSS − 0.2
VDD18 + 0.2
V
VN5VSIN_ABSM
VSS − 0.3
VDD + 0.3
V
VN5VSOUT_ABSM
VSS − 0.3
VDD + 0.3
V
ImpZC_IN
−20
20
mA
ImavgZC_IN
−2
2
mA
V5VSIN_ABSM
VSS − 0.3
5.5
V
V5VSOUT_ABSM
VSS − 0.3
VDD + 0.3
V
Absolute maximum voltage at the analog amplifier pins
VAMPA_ABSM
VSS − 0.3
VDD18 + 0.3
V
Absolute maximum voltage at the amplifier control pins
VAMPC_ABSM
VSS − 0.3
VCC + 0.3
V
CLOCK PINS XIN, XOUT
Absolute maximum input for the clock input pin (Note 1)
Absolute maximum voltage at the clock output pin (Note 1)
NON 5 V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, TDO, SCK, SDO, SCB
Absolute maximum input for normal digital inputs and analog inputs
Absolute maximum voltage at any output pin
Maximum peak input current at the zerocrossing input pin
Maximum average input current at the zerocrossing input pin (1 ms)
5 V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0..IO9, RESB, TDI, TCK, TMS, TRSTB, TEST, SDI
Absolute maximum input for digital 5 V safe pins configured as input (Note 2)
Absolute maximum voltage at 5V safe pin configured as output (Note 2)
AMPLIFIER PINS A+, A−, B+, B−, BOUT1, BOUT2, VWARN, XOUT
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The upper maximum voltage rating on the clock pins XIN and XOUT is specified with respect to the output voltage of the internal core voltage
regulator. The tolerance of this voltage regulator must be taken into account. In case an external clock is used, care must be taken not to
damage the XIN pin.
2. The direction (input or output) of configurable pins (IO0...IO9) depends on the firmware.
Normal Operating Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device as
described in the Electrical Characteristics section and for the
reliability specifications.
Total cumulative dwell time outside the normal power
supply voltage range or the ambient temperature under bias,
must be less than 0.1 percent of the useful life.
Table 3. OPERATING RANGES
Rating
Power supply voltage range (VDDA and VDD pins)
Power supply voltage range (VCC pin)
Symbol
Min
Max
Unit
VDD, VDDA
3.0
3.6
V
Vcc
6.0
12.0
V
Junction Temperature Range
TJ
−40
125
°C
Ambient Temperature Range
TA
−40
85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCN49599
Pin Description − QFN Package
VDDA
VSSA
RX_OUT
RX_IN
REF_OUT
ZC_IN
EN
A+
A−
A_OUT
VCC
B_OUT1
B_OUT2
VEE
43
44
45
46
47
48
49
50
51
52
53
54
55
56
B−
B+
VEE
RLIM
ILIM
VDD
VSS
IO3
IO4
IO5
IO0
TDO
TDI
TCK
1
42
2
41
3
40
4
39
5
38
6
37
NCN49599
7
8
36
35
9
34
10
33
11
32
12
31
13
30
14
29
ALC_IN
TX_OUT
NC
TX_EN
TEST
RES
IO1
BR0
BR1
SEN
IO2
CSB
SDO
SDI
28
27
26
25
24
23
22
21
20
19
17
18
16
15
SCK
RXD
TXD
VDD
VSS
VDD1V8
XOUT
XIN
TXD/PRES
EXT_CLK_EN
IO7
IO6
TRST
TMS
Figure 2. QFN Pin−out of NCN49599 (top view)
Table 4. NCN49599 QFN PIN FUNCTION DESCRIPTION
Pin Number
Pin Name
I/O
Type
1
B−
In
A
Inverting input of operational amplifier B
Description
2
B+
In
A
Non−inverting input of operational amplifier B
3, 56
VEE
P
Negative power supply amplifiers
4
RLIM
In
A
Amplifier B current limit set resistor pin
5
ILIM
In
A
Current limit flag
6, 25
VDD
P
3.3 V digital supply
7, 24
VSS
In
P
Digital ground
8..10, 17, 18
IO3...IO7
In/Out
D, 5VS, ST
General−purpose I/O’s (Note 3)
11, 36
IO0, IO1
In/Out
D, 5VS, ST
General−purpose I/O’s (Notes 3 and 4)
12
TDO
Out
D
13
TDI
In
D, 5VS, PD, ST
14
TCK
In
D, 5VS, PD
JTAG test clock (Note 7)
15
TMS
In
D, 5VS, PD
JTAG test mode select (Note 7)
16
TRSTB
In
D, 5VS, PD, ST
JTAG test reset (active low) (Note 8)
19
EXT_CLK_EN
In
D, 5VS, PD, ST
External clock enable input
20
TXD/PRES
Out
D, 5VS
Output of transmitted data (TXD) or PRE_SLOT signal (PRES)
21
XIN
In
A, 1.8V
Crystal oscillator input
22
XOUT
Out
A, 1.8V
Crystal oscillator output (output must be left floating when XIN is
driven by external clock)
JTAG test data output
JTAG test data input (Note 7)
3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general− purpose
IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation for details.
4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has
been loaded, the pin is available as a GPIO.
5. During normal operation, this pin must be tied to ground (recommended) or left open.
6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.
7. During normal operation, it is recommended that this pin is tied to ground.
8. During normal operation, this pin must be tied to Vdd.
9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.
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NCN49599
Table 4. NCN49599 QFN PIN FUNCTION DESCRIPTION
Pin Number
Pin Name
I/O
Type
Description
23
VDD1V8
26
TXD
Out
D, 5VS, OD
27
RXD
In
D, 5VS
UART receive input
28
SCK
Out
D, 5VS
SPI interface to external Flash: clock
29
SDI
In
D, 5VS, ST
30
SDO
Out
D, 5VS
SPI interface to external Flash: serial data output
31
CSB
In
D, 5VS
SPI interface to external Flash: chip select
32
IO2
In/Out
D, 5VS, ST
33
SEN
In
D, 5VS, PD, ST
34
BR1
In
D, 5VS
UART baud rate selection
35
BR0
In
D, 5VS
UART baud rate selection
37
RESB
In
D, 5VS, ST
38
TEST
In
D, 5VS, ST, PD
39
TX_ENB
Out
D, 5VS, OD
1.8 V regulator output. A decoupling capacitor of at least 1 mF is
required for stability
P
UART transmit output
SPI interface to external Flash: serial data input (Note 6)
Must be kept low while firmware is loaded over the serial interface; available as a normal GPIO afterwards (Note 3)
Boot mode selection (refer to Boot Loader section)
Reset (active low)
Production hardware test enable (Note 5)
Transmit enable (active low)
40
NC
41
TX_OUT
Out
This pin is not connected and must be connected to ground (recommended) or left open
A
Transmitter output
42
ALC_IN
In
A
Automatic level control input
43
VDDA
P
3.3 V analog supply
44
VSSA
P
Analog ground
45
RX_OUT
Out
A
Output of receiver operational amplifier
46
RX_IN
In
A
Non−inverting input of receiver operational amplifier
47
REF_OUT
Out
A
Internal voltage reference. A decoupling capacitor of at least 1 mF
is required for stability
48
ZC_IN
In
A
50/60 Hz input for mains zero crossing detection
49
ENB
In
D
Enable / shutdown power amplifier (active low)
50
A+
In
A
Non−inverting input of operational amplifier A
51
A−
In
A
Inverting input of operational amplifier A
52
A_OUT
Out
A
Output of operational amplifier A
53
VCC
P
Positive supply for power amplifiers A and B
54
B_OUT1
Out
A
Output of operational amplifier B
55
B_OUT2
Out
A
Output of operational amplifier B
3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general− purpose
IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation for details.
4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has
been loaded, the pin is available as a GPIO.
5. During normal operation, this pin must be tied to ground (recommended) or left open.
6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.
7. During normal operation, it is recommended that this pin is tied to ground.
8. During normal operation, this pin must be tied to Vdd.
9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.
P:
A:
D:
PD:
OD:
Power pin
Analogue pin
Digital pin
Internal Pull Down resistor (Note 9)
Open Drain Output
5VS:
Out:
In:
5 V safe; pin that supports the presence of 5 V if used as input or as open−drain output
Output signal
Input signal
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NCN49599
ELECTRICAL CHARACTERISTICS
All parameters are valid for TJ = −40°C to 125°C, VDD = 3.3 V, VCC = 12 V, VEE = 0 V, fCLK = 48 MHz ± 50 ppm unless otherwise specified.
Internal voltage regulator: pin VDD1V8
Table 5. POWER SUPPLY AND VOLTAGE REFERENCE
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VDD18
1.62
1.80
1.98
V
Internal voltage regulator output
VDD and VDDA current consumption
During reception (Note 10)
IRX
40
60
mA
During transmission (Note 10)
ITX
40
60
mA
4
mA
RESB = 0
VCC quiescent current consumption
IRESET
ENB = 0; no load
IQ_EN
20
40
mA
ENB = 1
IQ_HiZ
120
150
mA
10. With typical firmware. The exact value depends on the firmware variant loaded and the firmware configuration.
Oscillator: pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on
the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 6. OSCILLATOR
Parameter
Test Conditions
Symbol
Max
Unit
65
%
Tstartup
15
ms
Load capacitance external crystal
CL
18
pF
Series resistance external crystal
RS
60
W
15
pF
Duty cycle with quartz connected
Min
Typ
35
Start−up time
1
6
Maximum Capacitive load on XOUT
XIN used as clock input
CLXOUT
Low input threshold voltage
XIN used as clock input
VILXOUT
High input threshold voltage
XIN used as clock input
VIHXOUT
0.7 VDD18
V
Low output voltage
XIN used as clock input,
XOUT = 2 mA
VOLXOUT
0.3
V
High input voltage
XIN used as clock input
VOHXOUT
VDD18 −
0.3
V
Rise and fall time on XIN
XIN used as clock input
trXIN_EXT
1.5
ns
Max
Unit
550
VPK
1.9
V
0.3 VDD18
V
Zero Crossing detector and 50/60 Hz PLL: pin ZC_IN
Table 7. ZERO CROSSING DETECTOR AND 50/60 HZ PLL
Parameter
Mains voltage input range
Test Conditions
Symbol
Min
VMAINS
90
With protection resistor at
ZC_IN (Note 11)
Typ
Rising threshold level
VIRZC_IN
Falling threshold level
VIFZC_IN
0.85
V
Hysteresis
VHYZC_IN
0.4
V
R_CONF[0] = 0 (50 Hz)
Flock50Hz
45
55
Hz
R_CONF[0] = 1 (60 Hz)
Flock60Hz
54
66
Hz
R_CONF[0] = 0 (50 Hz)
Tlock50Hz
15
s
R_CONF[0] = 1 (60 Hz)
Tlock60Hz
20
s
Lock range (Note 12)
Lock time (Note 12)
11. This parameter is not tested in production.
12. These parameters will not be measured in production as the performance is determined by a digital circuit. Correct operation of this circuit
will be guaranteed by the digital test patterns.
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NCN49599
Table 7. ZERO CROSSING DETECTOR AND 50/60 HZ PLL
Parameter
Test Conditions
Symbol
Frequency variation without going out of
lock (Note 12)
R_CONF[0] = 0 (50 Hz)
Frequency variation without going out of
lock (Note 12)
R_CONF[0] = 1 (60 Hz)
Jitter of CHIP_CLK (Note 12)
Min
Typ
Max
Unit
DF60Hz
0.1
Hz/s
DF50Hz
0.1
Hz/s
JitterCHIP_CLK
25
ms
11. This parameter is not tested in production.
12. These parameters will not be measured in production as the performance is determined by a digital circuit. Correct operation of this circuit
will be guaranteed by the digital test patterns.
Transmitter External Parameters: pin TX_OUT, ALC_IN, TX_ENB
Table 8. TRANSMITTER EXTERNAL PARAMETERS
Parameter
AC output level
Test Conditions
Symbol
Min
fTX_OUT = 23 – 75 kHz (Note 13)
fTX_OUT = 148.5 kHz (Note 13)
VTX_OUT
0.85
0.76
DC output level
VTX_OUT
Typ
Max
Unit
1.15
1.22
VPK
VPK
1.65
V
Second order harmonic distortion
fTX_OUT = 148.5 kHz (Note 13)
HD2
−55
dB
Third order harmonic distortion
fTX_OUT = 148.5 kHz (Note 13)
HD3
−57
dB
11.44
Hz
30
Hz
Transmitted carrier frequency resolution
RfTX_OUT
Transmitted carrier frequency accuracy
(Note 14)
DfTX_OUT
Capacitive output load at pin TX_OUT
(Note 14)
CLTX_OUT
11.44
20
pF
Resistive output load at pin TX_OUT
RLTX_OUT
5
5
kW
Turn off delay of TX_ENB output
TdTX_ENB
0.25
0.5
ms
Automatic level control attenuation step
ALCstep
2.9
3.1
dB
Maximum attenuation
ALCrange
20.3
21.7
dB
Low threshold level on ALC_IN
With DC bias equal to VREF_OUT
VTLALC_IN
0.34
0.46
VPK
High threshold level on ALC_IN
With DC bias equal to VREF_OUT
VTHALC_IN
0.54
0.72
VPK
RALC_IN
111
189
kW
PSRRTX_OUT
32
10
VTX_PF_10kHz
VTX_LPF_148kHz5
VTX_LPF_195kHz
VTX_LPF_245kHz
VTX_LPF_500kHz
VTX_LPF_1000kHz
VTX_LPF_2000kHz
−0.5
−1.3
−4.5
Input impedance of ALC_IN pin
Power supply rejection ratio of the
transmitter section
f = 50 Hz (Note 15)
f = 10 kHz (Note 15)
Transmit cascade gain
(Note 16)
f = 10 kHz
f = 148.5 kHz
f = 195 kHz
f = 245 kHz
f = 500 kHz
f = 1 MHz
f = 2 MHz
dB
0.5
0.5
−1.5
−3
−18
dB
−36
−50
13. With the level control register set for maximal output amplitude. Tested with low pass filter tuned for CENELEC D−band.
14. This parameter will not be tested in production.
15. A sinusoidal signal of 100 mVpp is injected between VDDA and VSSA while the digital AD converter generates an idle pattern. The signal
level at TX_OUT is measured to determine the parameter.
16. The cascade of the digital−to−analog converter (DAC), low−pass filter (LPF), and transmission amplifier is production tested and must have
a frequency characteristic between the limits listed. The level is specified relative to the level at DC; the absolute output level will depend
on the operating condition.
This test is done with the low−pass filter (LPF) tuned to include the CENELEC D−band. In production the measurement will be done for relative
to DC with a signal amplitude of 100 mV.
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8
NCN49599
Power amplifier parameters: Pin A+, A−, A_OUT, B+, B−, BOUT1&2, VSS, VEE, ENB, ILIM, RLIM
Table 9. POWER AMPLIFIER GENERAL PARAMETERS
Parameter
Test Conditions
Symbol
Min
Typ
Output shutdown time
ENB 0 → 1
60
Output enable time
ENB 1 → 0
5
Junction temperature shutdown threshold
(Note 17)
Junction temperature shutdown recovery
threshold
(Note 17)
+150
ENB input level high
VIH,EN
ENB input level low
VIL,EN
ENB input current
Max
ns
10
°C
+135
°C
V
0.8
VENB = 0 V
mA
0.1
VIH,EN
ILIM flag output low level
VIL,EN
V
mA
10
ILIM flag output high level
ms
+160
2
VENB = 3.3 V
Unit
2
0.8
V
V
17. Characterization data only. Not tested in production.
Table 10. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP A
Parameter
Test Conditions
Symbol
Input offset voltage
Typ
Max
Unit
VOS,A
±3
±10
mV
PSRRA
25
150
mV/V
1
nA
Offset vs power supply
VCC = +6 V, VEE = −6 V
Input bias current
(Note 18)
IB,A
Input voltage noise density
f = 1 kHz, VIN = GND,
BW = 131 kHz (Note 18)
en,A
Common−mode voltage range
Common−mode rejection ratio
VEE − 0.1 v VCM v VCC − 3
Min
250
VCM,A
VEE −0.1
CMRRA
70
nV/√Hz
VCC − 3
V
85
dB
Differential input impedance
ZIDM,A
0.2 | 1.5
GW | pF
Common−mode input impedance
ZICM,A
0.2 | 3
GW | pF
100
dB
80
MHz
1.5
MHz
SRA
60
V/ ms
G = +1, RL = 500 W, VO = 8 VPP, f =
1 kHz, CIN = 220 mF, COUT= 330 mF
THD+NA
0.015
%
G = +1, RL = 50 W, VO = 8 VPP, f =
100 kHz, CIN = 220 mF, COUT = 330 mF
THD+NA
0.023
%
Open−loop gain
RL = 500 W (Note 18)
AOL,A
Gain bandwidth product
Full power bandwidth
GBWA
G = +5, Vout = 11 VPP (Note 18)
Slew rate
Total harmonic distortion and noise
80
0.2
Voltage output swing from rail
VCC = +12 V, VEE = 0 V
From positive rail
IL = -12 mA
VOH,A
0.3
1
V
From negative rail
IL = +12 mA
VOL,A
0.3
1
V
Short−circuit current
Output impedance
Closed Loop G = +4, f = 100 kHz
Capacitive load drive
18. Characterization data only. Not tested in production.
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9
ISC,A
280
mA
ZO,A
0.25
W
CLOAD,A
100
pF
NCN49599
Table 11. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP B
Parameter
Test Conditions
Symbol
Input offset voltage
Offset vs power supply
Typ
Max
Unit
VOS,B
±3
±10
mV
PSRRB
25
150
mV/V
1
nA
Input bias current
(Note 19)
IB,B
Input voltage noise density
f = 1 kHz, VIN = GND,
BW = 131 kHz
en,B
Common−mode voltage range
Common−mode rejection ratio
VEE − 0.1 v VCM v VCC − 3
Min
125
VCM,B
VEE −0.1
CMRRB
70
nV/√Hz
VCC − 3
V
85
dB
Differential input impedance
ZIDM,B
0.2 | 11
GW | pF
Common−mode input impedance
ZICM,B
0.2 | 22
GW | pF
100
dB
60
MHz
400
kHz
Open−loop gain
RL = 5 W (Note 19)
AOL,B
Gain bandwidth product
Full power bandwidth
80
GBWB
G = +2, Vout = 11 VPP (Note 19)
200
SRB
70
V/ ms
G = +1, RL = 50 W, VO = 8 VPP,
f = 1 kHz
THD+NB
0.015
%
G = +1, RL = 50 W, VO = 8 VPP,
f = 100 kHz
THD+NB
0.067
%
IOUT = −1.5 A @ TJ = 25°C
VOH,B
0.7
1
V
IOUT = −1.0 A @ TJ = 125°C
VOH,B
0.7
1
V
IOUT = +1.5 A @ TJ = 25°C
VOH,B
0.4
1
V
IOUT = +1.0 A @ TJ = 125°C
VOH,B
0.4
1
V
Short−circuit current
RLIM = 5 kW
ISC,B
Output impedance
Closed Loop G = +1,
f = 100 kHz
Slew rate
Total harmonic distortion and noise
Voltage output swing from positive rail
Voltage output swing from negative rail
1.2
A
ENB = 0 (enabled)
ZO,B
0.065
W
ENB = 1 (shutdown)
ZO,B
12
MW
CLOAD,B
500
nF
Capacitive load drive
19. Characterization data only. Not tested in production.
Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT
Table 12. RECEIVER EXTERNAL PARAMETERS
Parameter
Input offset voltage
Test Conditions
Symbol
Min
Typ
Max
Unit
AGC gain = 42 dB
VOFFS_RX_IN
5
mV
AGC gain = 0 dB
VOFFS_RX_IN
50
mV
Max. peak input voltage (corresponding
to 62.5% of the ADC full scale)
AGC gain = 0 dB (Note 20)
VMAX_RX_IN
1.15
VPK
Input referred noise of the analog receiver path
AGC gain = 42 dB
(Notes 20 and 21)
150
nV/√Hz
1
mA
0.85
NFRX_IN
Input leakage current of receiver input
ILE_RX_IN
−1
20. Input at RX_IN, no other external components.
21. Characterization data only. Not tested in production.
22. A sinusoidal signal of 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and REF_OUT output
is measured to determine the parameter. The AGC gain is fixed at 42 dB.
23. These parameters will be tested in production with an input signal of 95 kHz and 1 VPK by reading out the digital samples at the output
of the ADC. The AGC gain is switched to 0 dB.
24. The cascade of the receive low−pass filter (LPF), AGC and low noise amplifier is production tested and must have a frequency characteristic between the limits listed. The level is specified relative to the level at DC; the absolute output level will depend on the operating condition.
This test is done with the low−pass filter (LPF) tuned to include the CENELEC D−band.
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10
NCN49599
Table 12. RECEIVER EXTERNAL PARAMETERS
Parameter
Test Conditions
Symbol
Min
IMax_REF_OUT
−300
PSRRLPF_OUT
35
dB
10
dB
Max. current delivered by REF_OUT
Power supply rejection ratio of the
receiver input section
f = 50 Hz (Note 22)
f = 10 kHz (Note 22)
Typ
Max
Unit
300
mA
AGC gain step
AGCstep
5.3
6.7
dB
AGC range
AGCrange
39.9
44.1
dB
1.78
V
Analog ground reference output voltage
Load current ±300 mA
VREF_OUT
1.52
Signal to noise ratio
Signal amplitude of 62.5% of the
full scale of the ADC
(Notes 20 and 23)
SNAD_OUT
54
VCLIP_AGC_IN
1.05
VRX_LPF_10kHz
VRX_LPF_148.5kHz
VRX_LPF_195kHz
VRX_LPF_245kHz
VRX_LPF_500kHz
VRX_LPF_1000kHz
VRX_LPF_2000kHz
−0.5
−1.3
−4.5
Clipping level at the output of the gain
stage (RX_OUT)
Receive cascade gain
(Note 24)
f = 10 kHz, A = 250 mVpk
f = 148.5 kHz, A = 250 mVpk
f = 195 kHz, A = 250 mVpk
f = 245 kHz, A = 250 mVpk
f = 500 kHz, A = 250 mVpk
f = 1 MHz
f = 2 MHz
1.65
dB
0
1.65
VPK
0.5
0.5
−1
−3
−18
dB
−36
−50
20. Input at RX_IN, no other external components.
21. Characterization data only. Not tested in production.
22. A sinusoidal signal of 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and REF_OUT output
is measured to determine the parameter. The AGC gain is fixed at 42 dB.
23. These parameters will be tested in production with an input signal of 95 kHz and 1 VPK by reading out the digital samples at the output
of the ADC. The AGC gain is switched to 0 dB.
24. The cascade of the receive low−pass filter (LPF), AGC and low noise amplifier is production tested and must have a frequency characteristic between the limits listed. The level is specified relative to the level at DC; the absolute output level will depend on the operating condition.
This test is done with the low−pass filter (LPF) tuned to include the CENELEC D−band.
Power−on−Reset (POR)
Table 13. POWER−ON−RESET
Parameter
POR threshold (Note 25)
Power supply rise time
Test Conditions
Symbol
Min
VDD and VDDA rising
VPORH
VDD and VDDA falling
VPORL
2.1
0 to 3 V on both VDD and VDDA
TRPOR
1
Typ
Max
Unit
2.7
V
ms
25. The nominal voltage on the pins VDD and VDDA (the digital and analog power supply) must be equal; both supply rails must be switched
together.
Digital Outputs: TDO, SCK, SDO, CSB, IO0..IO7
Table 14. DIGITAL OUTPUTS: TDO, SCK, SDO, CSB, IO0..IO7
Parameter
Test Conditions
Symbol
Low output voltage (Note 26)
IXOUT = 4 mA
VOL
High output voltage (Note 26)
IXOUT = −4 mA
VOH
Min
0.85 VDD
26. For IO0..IO7, this parameter only applies if the pin is configured as output pin by the firmware.
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11
Typ
Max
Unit
0.4
V
V
NCN49599
Digital Outputs with Open Drain: TX_ENB, TXD, DATA/PRES
Table 15. DIGITAL OUTPUTS WITH OPEN DRAIN: TX_ENB, TXD, DATA/PRES
Parameter
Low output voltage
Test Conditions
Symbol
IXOUT = 4 mA
Min
Typ
VOL
Max
Unit
0.4
V
Max
Unit
0.2 VDD
V
Digital Inputs: BR0, BR1
Table 16. DIGITAL INPUTS: BR0, BR1
Parameter
Test Conditions
Symbol
Low input level
Min
Typ
VIL
High input level
0 to 3 V
Input leakage current
VIH
0.8 VDD
ILEAK
−2
V
2
mA
Max
Unit
0.2 VDD
V
Digital Inputs with Pull−down: TDI, TMS, TCK, TRSTB, TEST, SEN
Table 17. DIGITAL INPUTS WITH PULL−DOWN: TDI, TMS, TCK, TRSTB, TEST, SEN
Parameter
Test Conditions
Symbol
Min
Typ
Low input level
VIL
High input level
VIH
0.8 VDD
RPU
35
100
170
kW
Min
Typ
Max
Unit
0.80 VDD
V
Pull−down resistor
Measured at VPin = VDD / 2
V
Digital Schmitt Trigger Inputs: RXD, RESB, IO0..IO7, SDI
Table 18. DIGITAL SCHMITT TRIGGER INPUTS: RXD, RESB, IO0..IO7, SDI
Parameter
Test Conditions
Symbol
Rising threshold level (Note 27)
VT+
Falling threshold level (Note 27)
VT−
0.2 VDD
Input leakage current (Note 27)
ILEAK
−2
V
2
mA
27. For IO0...IO7, this parameter only applies if the pin is configured as input pin by the firmware.
Boat Loader Timing
NOTE:
The timing constraints shown in Table 19 governing the boot loader when uploading firmware over the serial interface are
illustrated in Figure 3.
Parameters are valid for a baud rate of 115’200.
Table 19. BOOT LOADER TIMING
Parameter
IO2 setup time to falling edge of RESB
Boot loader startup time
Test Conditions
Symbol
Min
(Note 28)
t2s
5
(Notes 28 and 29)
tstx
Inter−byte timeout sent to modem
(Note 28)
tIB
Boot loader acknowledgement after last
byte correctly received
(Note 28)
tACK
IO2 hold time after start of acknowledgement byte transmission
(Note 28)
t2h
Typ
12
Unit
ms
135
3.6
36
28. These parameters will not be measured in production as the performance is determined by a digital circuit.
29. This parameter is specified with the oscillator stable. Refer to Tstartup for oscillator startup information.
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Max
200
ms
20
ms
12
ms
ms
NCN49599
Figure 3. Timing constraints for uploading the firmware over the serial communication interface (SCI)
TYPICAL CHARACTERISTICS
2.2
2.0
Voltage [V]
Voltage [V]
1.68
1.66
1.64
1.8
1.6
1.4
1.62
1.60
1.2
0
0.2
0.4
0.6
Time [μs]
0.8
1.0
1.2
1.0
0
0.2
0.4
0.6
0.8
1.0
Figure 5. Receiver opamp − Large signal
transient response for (top to centre) no load,
10 kW load, 3.6 kW load
Figure 4. Receiver opamp − Small signal
transient response for (top to centre) no load,
10 kW load, 3.6 kW load
3.5
No load
3.0
10 kW
3.6 kW
Voltage [V]
2.5
RX_IN
2.0
1.5
49.9 W
RX_OUT
1.0
RL
0.5
1 μF
0
0
5
10
1.2
Time [μs]
15
20
Time [μs]
Figure 6. Receiver opamp − Output overdrive
recovery behaviour. The input signal is shown
in grey.
Figure 7. Test Circuit for Figures 4–6
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13
NCN49599
TYPICAL CHARACTERISTICS
8
20
Current sunk/sourced from pin [mA]
Current sunk/sourced from pin [mA]
25
Output low
Output high
15
10
5
0
0
0.5
1.0
1.5
2.0
Voltage at pin [V]
2.5
Output low,
VUC = 5 V
7
6
Output low,
VUC = 3.3 V
5
4
3
2
1
0
3.0
35
35
40
40
Third harmonic [dBc]
Second harmonic [dBc]
30
45
55
RL = 8.3 W
60
RL = 50.0 W
65
45
50
RL = 1.4 W
RL = 8.3 W
55
60
65
70
75
RL = 50.0 W
70
0
0.5
1.0
1.5
2.0
2.5
3.0
Output voltage [V RMS]
3.5
4.0
75
0
0.5
1.0
1.5
2.0
2.5
3.0
Output voltage [V RMS]
12 V
3 kW
100 nF
3.5
4.0
Figure 11. Third harmonic distortion of the
output opamp vs. output amplitude, for f = 100
kHz and RL (top to bottom) = 1.4 W, 8.3 W, 50 W
Figure 10. Second harmonic distortion of the
output opamp vs. output amplitude, for f = 100
kHz and RL (top to bottom) = 1.4 W, 8.3 W, 50 W
A+
5
Figure 9. Overcurrent flag pin (ILIM) current
sourcing and sinking capability
30
RL = 1.4 W
4
Voltage at pin [V]
Figure 8. GPIO current sourcing and sinking
capability
50
Output high,
VUC = 3.3 V
2
3
1
0
Output high,
VUC = 5 V
22 μF
3 pF
3 kW
VEE
AOUT
50 μF
B*
A*
BOUT
B+
NCN49599
(A opamp)
6V
NCN49599
(B opamp)
Figure 12. Test Circuit for Figures 10 and 11
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14
RL
NCN49599
GENERAL DESCRIPTION
development of applications: the user just needs to send the
raw data to the NCN49599 and no longer has to take care of
the details of the transmission over the specific medium. The
latter part easily represents half of the software development
cost.
The NCN49599 is a single−chip half duplex S−FSK
modem with an integrated line driver. It is designed for
hostile communication environments with very low
signal−to−noise ratio (SNR) and high interference. It is
particularly suited for power line carrier (PLC) data
transmission on low−or medium−voltage power lines.
Together with firmware, the device handles of the lower
layers of communication protocols. Firmware solutions are
provided by ON Semiconductor royalty−free for the two
most popular standards: the IEC 61334−5−1 standard
primarily intended for automatic meter reading (AMR) and
the ON PL110 protocol primarily intended for building and
process automation. Both variants handle the physical,
Media Access Control (MAC) and Logical Link Control
(LLC) layers on−chip. For more information, refer to the
dedicated software datasheets.
Because the lower layers are handled on−chip, the
NCN49599 provides an innovative architectural split. The
user benefits from a higher level abstraction. Compared to
a low−level interface, the NCN49599 allows faster
VCC
B− B+ RLIM ILIM A_OUT
CLIENT
Application
SERVER
Application
SERVER
Application
NCN49599 with
IEC firmware in
MASTER mode
NCN49599 with
IEC firmware in
SLAVE mode
NCN49597 with
IEC firmware in
SLAVE mode
Mains
Figure 13. Application example: a network topology
for a three−node IEC 61334−5−1 network
A typical system−level application is show in Figure 13.
Here, two NCN49599 modems and an NCN49597 modem
in combination with the IEC 61334−5−1 firmware connect
equipment using power line communication.
Figure 14 shows the building blocks of the NCN49599.
Refer to the sections below for a detailed description.
A− A+
VDD1V8 VDDA
VDDD
B_OUT1
NCN49599
B_OUT2
Current
Protect
B
A
TSD
Communication Controller
Power Amplifier
EN
TX_ENB
LP
Filter
TX_OUT
Receiver (S−FSK Demodulator)
RX_IN
Test
Control
AGC
S−FSK
Demodulator
A/D
IO[9:3]
RX_DATA
CRC
TXD/PRES
5
JTAG I /F
TEST
RESB
POR
Watchdog
Timer 1 & 2
REF
REF_OUT
5
Local Port
ARM
Risc
Core
RX_OUT
AAF
4
Flash SPI
Zero
crossing
PLL
VEE
SPI I/F
SEN
Clock and Control
ZC_IN
VSSA
Clock Generator
& Timer
VSSD
TO Application
Micro Controller
BR1
Transmit Data
& Sine Synthesizer
D/A
ALC_IN
FROM
Line Coupler
TxD
RxD
T_REQ
BR0
Serial
Comm.
Interface
Transmitter (S−FSK Modulator)
OSC
Program/Data
RAM
Program
ROM
TO
External Flash
Interrupt
Control
XIN XOUT EXT_CLK_E
Figure 14. Block Diagram of the NCN49599 S−FSK Modem
S−FSK is a modulation and demodulation technique that
combines some of the advantages of a classical spread
spectrum system (e.g. immunity against narrow band
interferers) with the advantages of the classical FSK system
(low complexity). The transmitter assigns the space
frequency fS to “data 0” and the mark frequency fM to “data
1”. In contrast to classical FSK, the modulation carriers fS
and fM used in S−FSK are placed well apart. As interference
and signal attenuation seen at the carrier frequencies are now
less correlated, this results in making their transmission
NCN49599 complies with the CENELEC EN 50065−1,
EN 50065−7 and the IEC 61334−5−1 standards. It operates
from a single 3.3 V power supply and is interfaced to the
power line by an external line driver and transformer. An
internal PLL is locked to the mains frequency and is used to
synchronize the data transmission at data rates of 300, 600,
1200, 2400 and 4800 baud for a 50 Hz mains frequency, or
360, 720, 1440, 2880 and 5760 baud for a 60 Hz mains
frequency. In both cases this corresponds to 3, 6, 12 or 24
data bits per half cycle of the mains period.
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15
NCN49599
random−access memory (RAM) stores the firmware and the
working data.
After the modem has been reset, the user must upload the
firmware into the modem memory. This may be done over
the asynchronous serial interface (discussed below);
alternatively, the modem can autonomously retrieve the
firmware from an attached SPI memory. For details, refer to
Boot Loader section.
The modem communicates to the application
microcontroller over a Serial Communication Interface
(SCI), a standard asynchronous serial link, which allows
interfacing with any microcontroller with a free UART. The
SCI works on two wires: TXD and RXD. The baud rate is
programmed by setting two pins (BR0, BR1).The
NCN49599 is functionally equivalent to the combination of
an NCN49597 modem and an NCS5651 line driver. Thus,
the same user software works equally well with the
NCN49597 as with the NCN49599.
quality independent from each other. Thus, more robust
communication is possible in interference−prone
environments. The frequency pairs supported by the
NCN49599 are in the range of 9–150 kHz with a typical
separation of 10 kHz.
The NCN49599 incorporates a line driver for
transmission, enabling communication over low−
impedance lines. The line driver is described in detail in the
Power Amplifier section.
The conditioning and conversion of the signal is
performed at the analogue front−end of the circuit. All
further processing of the signal and the handling of the
protocol is fully digital. The digital processing of the signal
is partitioned between hardwired blocks and a
microprocessor block. Where timing is most critical, the
functions are implemented with dedicated hardware. For the
functions where the timing is less critical − typically the
higher level functions − the circuit makes use of an
integrated ARM microprocessor core. An internal
DETAILED HARDWARE DESCRIPTION
Clock and Control
ZC_IN
Zero
crossing
PLL
CHIP_CLK
PRE_SLOT
PRE_FRAME_CLK
FRAME_CLK
BYTE_CLK
BIT_CLK
Clock and Control
PRE_BYTE_CLK
The clock and control block (Figure 15) provides the modem with the clock and synchronization signals required for correct
data transmission and reception. It is composed of the zero−crossing detector section, phase locked loop (PLL) section,
oscillator section and clock generator section.
Clock Generator
& Timer
OSC
EXT_CLK_E
XIN
XOUT
Figure 15. Clock and Control Block
Oscillator
If a crystal is to be used, the pin EXT_CLK_E should be
strapped to VSSA and the circuit illustrated in Figure 16
should be employed.
The NCN49599 may be clocked from a crystal with the
built−in oscillator or from an external clock. XIN is the input
to the oscillator inverter gain stage; XOUT the output.
XOUT cannot be used directly as a clock output as no
additional loading is allowed on the pin due to the limited
voltage swing. This applies both to operation with a crystal
and an external oscillator.
If an external clock of 48 MHz is to be used, the pin
EXT_CLK_E must be pulled to VDD and the clock signal
connected to XIN. Note that the high level on XIN must not
exceed the voltage of the internal voltage regulator (VDD18,
or about 1.8 V). The output must be floating.
XIN
XOUT
EXT_CLK_E
48 MHz
CX
CX
VSSA
Figure 16. Clocking the NCN49599 with a Crystal
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16
NCN49599
Correct operation is only possible with a parallel
resonance crystal of 48 MHz. A crystal with a load
capacitance CL of 18 pF is recommended.
The load capacitance is the circuit capacitance appearing
between the crystal terminals; it must be within the range
specified by the crystal manufacturer for correct operation
at the desired frequency. CL is determined by the external
capacitors CX and stray capacitance (CSTRAY):
CL +
directly from fCLK. The clock for the transmitter, fTX_CLK,
is equal to fCLK / 4 or 12 MHz; the master receiver clock,
fRX_CLK, equals fCLK / 8 or 6 MHz. All the internal clock
signals of the transmitter and the receiver will be derived
from fTX_CLK resp. fRX_CLK..
Zero Crossing Detector
Depending on the standard and the application,
synchronization with the mains zero crossing may be
required. Of particular note is IEC 61334−5−1 where data
frames start at a zero crossing of the mains voltage.
In order to recover this timing information, a zero cross
detection of the mains is performed.
Recommended circuits for the detection of the mains zero
crossing appear in the Application note “Mains
synchronization for PLC modems”. In case the modem is not
isolated from the mains a series resistor of 1 MW in
combination with two external Schottky clamp diodes is
recommended (Figure 17). This will limit the current
flowing through the internal protection diodes.
CX
) C STRAY
2
Stray capacitance typically ranges from 2 to 5 pF. This
results in a typical CX value of 33pF.
The printed circuit board should be designed to minimise
stray capacitance and capacitive coupling to other parts by
keeping traces as short as possible. The quality of the ground
plane below the oscillator components is critical.
To guarantee startup, the series loss resistance of the
crystal must be smaller than 60 W.
The oscillator output fCLK (48 MHz) is the base clock for
the entire modem. The microcontroller clock, fARM, is taken
Clock & Control
3V3_A
FROM
MAINS
BAS70−04
1 MW
ZC_IN
Debounce
Filter
100 pF
ZeroCross
PLL
CHIP_CLK
Figure 17. Zero Crossing Detector with Falling−edge De−bounce Filter
Because the detector threshold is not 0 V but slightly
positive, the rising edge of the output is delayed compared
to the actual rising mains zero crossing (Figure 18).
ZC_IN is the mains frequency sense pin. A comparator
with Schmitt trigger ensures a signal with edges, even in the
presence of noise. In addition, the falling edges of the
detector output are de−bounced with a delay of 0.5–1 ms.
Rising edges are not de−bounced.
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17
NCN49599
Figure 18. Zero Crossing Detector Signals and Timing (example for 50 Hz)
Phase Locked Loop (PLL)
using the register R_CONF. The bit R_CONF[0] specifies
the mains frequency, with a cleared bit (0) corresponding to
50 Hz; a set bit (1) to 60 Hz. The bits R_CONF[2:1] control
the number of data bits per mains period. The values 00b,
01b, 10b and 11b correspond to 6, 12, 24 and 48 bits per
mains period of 20 ms (50 Hz) or 16.7 ms (60 Hz).
Together this results in the baud rates and chip clock
frequencies shown in Table 20.
A phase−locked loop (PLL) structure converts the signal
at the ZC_IN comparator output to the chip clock
(CHIP_CLK). This clock is used for modulation and
demodulation and runs 8 times faster than the bit rate; as a
result, the chip clock frequency depends on the mains
frequency and the baud rate.
The filters of the PLL are dependent on the baud rate and
the mains frequency. They must be correctly configured
Table 20. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY
R_CONF[0]
Mains Frequency
R_CONF[2:1]
Baudrate
CHIP_CLK
0
50 Hz
00b
300 bps
2400 Hz
01b
600 bps
4800 Hz
10b
1200 bps
9600 Hz
11b
2400 bps
19200 Hz
00b
360 bps
2880 Hz
01b
720 bps
5760 Hz
10b
1440 bps
11520 Hz
11b
2880 bps
23040 Hz
1
60 Hz
The PLL significantly reduces the clock jitter. This makes
the modem less sensitive to timing variations; as a result, a
cheaper zero crossing detector circuit may be used.
The PLL input is only sensitive to rising edges.
If no zero crossings are detected, the PLL freezes its
internal timers in order to maintain the CHIP_CLK timing.
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18
NCN49599
Figure 19. Using the ZC_ADJUST register to compensate for zero crossing delay (example for 50 Hz)
The PLL ensures the generated chip clock is in phase with
the rising edge of comparator output. However, these edges
are not precisely in phase with the mains.
Inevitably, the external zero crossing detector circuit
suffers from a delay tDETD (e.g. caused by an optocoupler).
In addition, the comparator threshold is not zero (VIRZC_IN
= 1.9 V); this results in a further delay, tCOMP0 between the
rising edge of the signal on pin ZC_IN and the rising edge
on the comparator output (as noted before, the PLL takes
only the rising edge into account).
The combination of these delays would cause the modem
to emit and receive data frames too late.
Therefore, the PLL allows tuning the phase difference
between its input and the chip clock. The CHIP_CLK may
be brought forward by setting the register R_ZC_ADJUST.
The adjustment period or granularity is 13 ms, with a
maximum adjustment of 255 • 13 ms = 3,3 ms,
corresponding with a sixth of the 50 Hz mains sine period.
This is illustrated in Figure 9. The “physical frame” (i.e.,
the modulated signal appearing on the mains) starts earlier
with R_ZC_ADJUST[7:0] • 13 ms to compensate for the
zero cross delay.
The delay corresponding with the value of
R_ZC_ADJUST is also listed in Table 21.
Table 21. ZERO CROSSING DELAY COMPENSATION
R_ZC_ADJUST[7:0]
Compensation
0000 0000
0 ms (reset value)
0000 0001
13 ms
0000 0010
26 ms
0000 0011
39 ms
...
...
1111 1111
3315 ms
Clock Generator and Timer
The timing generator (Figure 15, centre) is responsible for
all synchronization signals and interrupts related to S−FSK
communication.
The timing is derived from the chip clock (CHIP_CLK,
generated by the PLL) and the main oscillator clock fCLK.
The timing has a fixed repetition rate, corresponding to the
length of a physical subframe (see reference [1]).
When the NCN49599 switches between receive and
transmit mode, the chip clock counter value is maintained.
As a result, the same timing is maintained for reception and
transmission. Seven timing signals are defined:
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19
NCN49599
• CHIP_CLK is the output of the PLL and the input of
•
•
•
•
the timing generator. It runs 8 times faster than the bit
rate on the physical interface.
BIT_CLK is only active at chip clock counter values
that are multiples of 8 (0, 8, .., 2872). It indicates the
start of the transmission of a new bit.
BYTE_CLK is only active at chip clock counter values
that are multiples of 64 (0, 64, .., 2816). It indicates the
start of the transmission of a new byte.
FRAME_CLK is only active at counter value 0; it
indicates the transmission or reception of a new frame.
PRE_BYTE_CLK follows the same pattern as
BYTE_CLK, but precedes it by 8 chip clocks. It can be
used as an interrupt for the internal microcontroller and
•
•
indicates that a new byte for transmission must be
generated.
PRE_FRAME_CLK follows the same pattern at
FRAME_CLK, but precedes it by 8 chip clocks. It can
be used as an interrupt for the internal microcontroller
and indicates that a new frame will start at the next
FRAME_CLK.
PRE_SLOT is active between the rising edge of
PRE_FRAME_CLK and the rising edge of
FRAME_CLK. This signal can be provided at the
digital output pin DATA/PRES when R_CONF[7] = 0.
Thus, the external host controller may synchronize its
software with the internal FRAME_CLK of the
NCN49599. Refer to the SCI section and Table 26 for
details.
Start of the physical subframe
R_CHIP _CNT
2871 2872
2879
0
1
2
3
4
5
6
7
8
9
63
64
65
CHIP_CLK
BIT_CLK
BYTE_CLK
FRAME _CLK
PRE_BYTE_CLK
PRE_FRAME _CLK
PRE_SLOT
Figure 20. Timing Signals
Transmitter Path Description (S−FSK Modulator)
The transmitter block is controlled by the microcontroller
core, which provided the bit sequence to be transmitted.
Direct digital synthesis (DDS) is employed to synthesize the
modulated signal (the Sine Wave Generator section); after a
conditioning step, this signal is converted to an analogue
voltage (the DA Converter section). Finally, an amplifier
with variable gain buffers the signal (the Amplifier with
ALC section) and outputs it on pin TX_OUT.
The NCN49599 transmitter block (Figure 21) generates
the signal to be sent on the transmission channel. Most
commonly, the output is connected to a power amplifier
which injects the output signal on the mains through a
line−coupler.
As the NCN49599 is a half−duplex modem, this block is
not active when the modem is receiving.
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20
NCN49599
Transmitter(S−FSK Modulator)
TX_EN
ALC_IN
ALC
control
TX_OUT
LP
Filter
ARM
Interface
&
Control
Transmit Data
& Sine Synthesizer
D/A
fMI
f MQ
fSI
fSQ
TO RECEIVER
Figure 21. Transmitter Block Diagram
A 3rd order continuous time low pass filter in the transmit
path filters the quantization noise and noise generated by the
ΣΔ DA converter.
The −3 dB frequency of this filter can be set to 130 kHz for
applications using the CENELEC A band. In this
configuration, the response of the filter is virtually flat up to
95 kHz. Alternatively a −3 dB frequency of 195 kHz can be
selected yielding a flat response for the entire CENELEC A
to D band (i.e., up to 148.5 kHz). Refer to the documentation
of the firmware for more information.
The low pass filter is tuned automatically to compensate
for process variation.
Microcontroller Interface & Control
The interface with the internal ARM microcontroller
consists of an 8−bit data register R_TX_DATA, 2 control
registers R_TX_CTRL and R_ALC_CTRL, a flag
TX_RXB defining the operating mode (a high level
corresponding to transmit mode; low to receive) and the
frequency control registers. All these registers are memory
mapped; most can be accessed through the firmware: refer
to the specific firmware documentation for details.
Sine Wave Generator
The direct digital synthesizer (DDS) generates a
sinusoidal signal alternating between the space frequency
(fS, data 0) and the mark frequency (fM, data 1) as required
to modulate the desired bit pattern. Two 16−bit wide
frequency step registers, R_FM and R_FS, control the steps
used by the DDS and thus the frequencies.
The space and mark frequency can be calculated using
fS = R_FS[15:0]_dec • fDDS/218
fM = R_FM[15:0]_dec • fDDS/218
Equivalently, values for R_FS[15:0] and R_FM[15:0]
may be calculated from the desired carrier frequencies
R_FS[15:0]_dec = [218 • fS/fDDS]
R_FM[15:0]_dec = [218 • fM/fDDS]
With fDDS = 3 MHz the direct digital synthesizer clock
frequency and [x] equal to x rounded to the nearest integer.
At the start of the transmission the DDS phase
accumulator starts at 0, resulting in a 0 V output level.
Switching between fM and fS is phase−continuous. Upon
switching to receive mode the DDS completes the active
sine period. These precautions minimize spurious emissions.
Amplifier with Automatic Level Control (ALC)
The analogue output of the low−pass filter is buffered by
a variable gain amplifier; 8 attenuation steps from 0 to
−21 dB (typical) with steps of 3 dB are provided.
The attenuation can be fixed by setting the bit
R_ALC_CTRL[3]. The embedded microcontroller can then
set the attenuation using register ALC_CTRL[2:0]. This
register is usually made available by the firmware to the
application microcontroller. The attenuations corresponding
to R_ALC_CTRL[2:0] values are given in Table 34.
Table 22. FIXED TRANSMITTER OUTPUT ATTENUATION
ALC_CTRL[2:0]
DA Converter and Anti−aliasing Filter
A digital to analogue ΣΔ converter converts the sine wave
digital word to a pulse density modulated (PDM) signal. The
PDM stream is converted to an analogue signal with a first
order switched capacitor filter.
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21
Attenuation
000
0 dB
001
−3 dB
010
−6 dB
011
−9 dB
100
−12 dB
101
−15 dB
110
−18 dB
111
−21 dB
NCN49599
the last level is kept in memory. As a result the next transmit
frame starts with the old level.
Note that the DC level on the ALC_IN pin is fixed
internally to 1.65 V. As a result, a coupling capacitor is
usually required.
If the automatic level control feature is not used, the pin
ALC_IN may be left floating (not recommended) or tied to
ground.
Alternatively, automatic level control (ALC) may be used
by clearing the bit R_ALC_CTRL[3].
In this mode, the signal on the analogue input pin ALC_IN
controls the transmitter output level. First, peak detection is
performed. The peak value is then compared to two
threshold levels VTLALC_IN and VTHALC_IN. Depending
on the value of the measured peak level on ALC_IN the
attenuation is updated using
VpALC_IN < VTLALC:
increase the level with one 3 dB step
VTLALC ≤ VpALC_IN ≤ VTHALC:
do not change the attenuation
VpALC_IN > VTHALC:
decrease the level with one 3 dB step
The gain changes in the next chip clock. Therefore, an
evaluation phase and a level adjustment phase take two
CHIP_CLK periods. ALC operation is enabled only during
the first 16 CHIP_CLK cycles after switching to transmit
mode.
Following reset, the level is set at minimum level
(maximum attenuation). When switching to reception mode
Transmitter Output TX_OUT
The transmitter output is DC coupled to the TX_OUT pin.
Because the entire analogue part of the NCN49599 is
referenced to the analogue reference voltage REF_OUT
(about 1.65 V), a decoupling capacitor (C1 in Figure 22) is
usually required.
To suppress the second and third order harmonic of the
generated S−FSK signal it is recommended to use a low pass
filter. Figure 22 illustrates an MFB topology of a 2nd order
filter.
Transmitter (S−FSK Modulator )
C4
FROM LINE
DRIVER
ALC
control
ALC _IN
R3
C3
R2
R1
C2
TO TX POWER
OUTPUT STAGE
C1
LP
Filter
TX_OUT
ARM
Interface
&
Control
TX_EN
VSSA
R4
Figure 22. TX_OUT Filter
The modem indicates whether it is transmitting or
receiving on the digital output pin TX_ENB. This is driven
low when the transmitter is activated. The signal can be used
to turn on an external line driver.
TX_ENB is a 5 V safe with open drain output; an external
pull−up resistor must be added (Figure 22, R4).
When the modem switches from transmit to receive mode,
TX_ENB is kept active (i.e., low) for a short period
tdTX_ENB (Figure 13).
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22
NCN49599
BIT_CLK
TX_DATA
TX_RXB
TX_ENB
TX_OUT
Figure 23. TX_ENB Timing
Power Amplifier
tdTX_ENB
Optimal stability and noise rejection, sufficient supply
decoupling is required. Refer to the Supplies and
Decoupling section for more information.
The NCN49599 integrates a high efficiency, Class A/B,
low distortion power line driver. It is optimized to accept a
signal from the modem part of the chip. The driver consists
of two operational amplifiers (opamps).
The output opamp is designed to drive up to 1.2 A peak
into an isolation transformer or simple coil coupling to the
mains. At an output current of 1.5 A, the output voltage is
guaranteed to swing within 1 V or less of either rail giving
the user improved SNR.
In addition to the output amplifier, a small−signal opamp
is provided which can be configured as a unity gain follower
buffer or can provide the first stage of a 4−pole low pass
filter.
The line driver offers a current limit, programmable with
a single resistor, R−Limit, together with a current limit flag.
The device has a thermal shutdown with hysteresis,
triggered when the internal junction temperature exceeds
150_C.
The line driver has a power supply voltage range of
6−12 V. It can be shut down, leaving the outputs highly
impedant.
Coupling and Filtering
A typical coupling and filtering circuit is shown in
Figure 24.
The power amplifier is enabled when ENB is low. In most
applications TX_ENB is looped to ENB; an external pull up
resistor is required.
Because the DC level on the TX_OUT pin equals the
voltage on REF_OUT (nominally 1.65 V), a decoupling
capacitor C1 is needed when connecting it to the power
amplifier.
To suppress the second and third order harmonic of the
generated S−FSK signal it is recommended to use a 2nd or
3th order low pass filter. Figure 24 shows an MFB topology
of a 3th order filter, designed for compliance with the
European CENELEC EN 50056−1 standard for signaling on
low−voltage electrical installations in the frequency range
3 kHz to 148.5 kHz.
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23
NCN49599
R3
R4
R5
R6
R2
C3
R1
C1
C4
VCC
C2
C5
R8
B−
B+
A_OUT
A−
A+
R7
C6
B_OUT1
TO COUPLER
B_OUT2
A
Power Amplifier
EN
Transmitter (S−FSK Modulator)
R22
TX_EN
A
TX_OUT
ARM
Interface
&
Control
LP
Filter
Figure 24. Power Amplifier Coupling and Filtering Current Protection
The maximal output current of the line driver in the
NCN49599 can be programmed by the simple addition of a
resistor (RLIM) from RLIM (pin 4) to VEE (Figure 25).
Figure 26 shows the limiting value for given resistance, with
a tolerance of ±50 mA. Unlike traditional power amplifiers,
the line driver in the NCN49599 current limit functions both
while sourcing and sinking current. To calculate the
resistance required to program a desired current limit the
following equation can be used:
For correct operation in typical applications it is strongly
recommended to set RLIM to 5 kW. This ensures the current
will not exceed 1.2 A causing damage. Refer also to the
paragraph Safe operating area.
If the load current reaches the set current limit, the ILIM
flag will go logic high. As an example, the user may act on
this by reducing the signal amplitude.
When the current output recovers, the ILIM flag will return
low.
54
BOUT
55
1.215 V
3
4
RLIMIT
56
VEE
RLIM
Figure 25. Programming the Current Limit
Figure 26 illustrates the required resistance to program the
current limit.
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24
NCN49599
Figure 26. RLIM in Function of the ILIM
Figure 27. Example SOA in VL–IL space (bottom
left corner is safe) with Rthj−a = 50 K/W
Thermal Protection
Although voltage−versus−current is the normal
representation of safe operating area, a PLC line driver can
only control one of these variables: voltage and current are
linked through the mains impedance. Figure 28 displays
exactly the same information as Figure 27 but might be
easier to work with. Constant current values are now
represented as canted lines.
Excessive dissipation inside the amplifier, for instance
during overload conditions, can result in damaging junction
temperatures. A thermal shutdown protection monitors the
junction temperature to protect against this.
When the internal junction temperature reaches
approximately 160_C, the amplifier is disabled and placed in
a high−impedance state. The amplifier will be re−enabled −
assuming the Enable input is still active − when the junction
temperature cools back down to approximately 135_C.
Safe Operating Area
The safe operating area (SOA) of an amplifier is the
collection of output currents IL and the output voltages VL
that will result in normal operation with risk of destruction
due to overcurrent or overheating.
In a normal application only the output amplifier of the
line driver must be considered; the load on the small−signal
amplifier is usually negligible.
The output amplifier SOA depends on the thermal
resistance from junction to ambient Rthj−a, which in turn
strongly depends on board design. Rthj−a = 50 K/W in free
air is a typical value, which may be used even if the host
printed circuit board (PCB) is mounted in a small closed
box, provided the transmission of frames are infrequent and
widely spread in time.
This typical value is also used in the generation of the
curves plotted in Figures 27 and 28.
Figure 27 shows the SOA in function of output current IL
and output voltage VL with the ambient temperature as
independent parameter. The maximum allowed current is
800 mA RMS. For that reason it is recommended to limit the
output current by using RLIM = 5 kW. This current limitation
is plotted as a horizontal line. The maximal output voltage is
limited by VCC,max, VOH and VOL. This results in the straight
line on the right hand side of the VL–IL plot. The area below
and left from these limitations is considered as safe. The
relation between output voltage and current is the impedance
as seen at the output of the power operational amplifier.
Constant impedance lines are represented by canted lines.
Figure 28. Example SOA in ZL–VL space (bottom
right corner is safe)
Again, the safe operating area depends on PCB layout.
Thus, the designer must verify the performance of her
particular design [1].
Receiver Path Description
The receiver demodulates the signal on the
communication channel. Typically, an external line
coupling circuit is required to filter out the frequencies of
interest on the communication channel.
The receiver block (Figure 29 and Figure 32) filters,
digitalizes and partially demodulates the output signal of the
coupling
circuit.
Subsequently,
the
embedded
microcontroller core will demodulate the resulting digital
stream. The demodulation is described in the fact sheets of
the various firmware solutions.
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25
NCN49599
RX_OUT
Receiver(Analog Path)
FROM
DIGITAL
LOW NOISE
OPAMP
RX_IN
4th
order
SD AD
LPF
Gain
TO
DIGITAL
REF_OUT
REF
1,65 V
Figure 29. Analogue Path of the Receiver Block
FROM TRANSMITTER
Receiver (Digital Path)
fMI
f MQ f SI
Quadrature Demodulator
fSQ
nd
FROM
ANALOG
2
IM
Decimator
1st
Noise
Shaper
fMQ
Compen−
sator
Decimator
Sliding
Filter
nd
2
QM
Sliding
Filter
IS
Sliding
Filter
Decimator
fM
fSI
nd
2
TO
GAIN
Abs
value
accu
AGC
Control
Decimator
f SQ
nd
2
QS
Decimator
fS
Sliding
Filter
Figure 30. Digital Path of the Receiver Block
50/60 Hz Suppression Filter
To improve communication performance, the NCN49599
provides a low−noise operational amplifier in a unity−gain
configuration which can be used to make a 50/60 Hz
suppression filter with only four external passive
components. Pin RX_IN is the non−inverting input and
RX_OUT is the output of the amplifier.
The internal reference voltage (described below) of
1.65 V is provided on REF_OUT and can be used for this
purpose. The current drawn from this pin should be limited
to 300 mA; in addition, adding a ceramic decoupling
capacitor of at least 1 mF is recommended.
The line coupler − external to the modem and not
described in this document − couples the communication
channel to the low−voltage signal input of the modem.
Ideally the signal produced by the line coupler would only
contain the frequency band used by the S−FSK modulation.
For the common case of communication over an AC power
line, a substantial 50 or 60 Hz residue is still present after the
line coupler. This residue − typically much larger than the
received signal − can easily overload the modem.
R2
Received
Signal
VIN
C2
C1
RX_OUT
Receiver (S−FSK Demodulator)
LOW NOISE
OPAMP
RX_IN
TO AGC
R1
REF_OUT
1,65 V
REF
CDREF
VSSA
Figure 31. External Component Connection for 50/60 Hz Suppression Filter
The recommended topology is shown in Figure 20 and
realizes a second order filter. The filter characteristics are
determined by external capacitors and resistors. Typical
values are given in Table 24 for carrier frequencies of 63.3
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26
NCN49599
and 74.5 kHz; the resulting frequency response is shown in
Figure 32. With a good layout, suppressing the residual
T
mains voltage (50 or 60 Hz) with 60 dB is feasible. To design
a filter for other frequencies, consult the design manual.
20
Vin/Vrx_out (dB)
−20
−60
−100
−140
10
100
1k
Frequency (Hz)
10k
100k
Figure 32. Transfer function of the 50 Hz suppression circuit shown in Figure 17
the transmit path which can be shared because NCN49599
works in half duplex mode. As described in the Low Noise
Anti−aliasing Filter section, the same choice of −3 dB
frequency can be selected between 130 kHz (virtually flat up
to 95 kHz) or 195 kHz (flat up to 148.5 kHz).
The output of the low pass filter is input for an analog 4th
order sigma−delta converter. The DAC reference levels are
supplied from the reference block. The digital output of the
converter is fed into a noise shaping circuit blocking the
quantization noise from the band of interest, followed by
decimation and a compensation step.
Table 23. VALUE OF THE RESISTORS AND
CAPACITORS
Component
Value
Unit
C1
1,5
nF
C2
1,5
nF
CDREF
1
mF
R1
22
kW
R2
11
kW
It is important to note that the analog part of NCN49599
is referenced to the internal analogue reference voltage
REF_OUT, with a nominal value of 1.65 V. As a result, the
DC voltage on pin RX_IN must be 1.65 V for optimal
dynamic range. If the external signal has a substantially
different reference level capacitive coupling must be used.
Quadrature Demodulator
The quadrature demodulation block mixes the digital
output of the ADC with the local oscillators. Mixing is done
with the in−phase and quadrature phase of both the fS and fM
carrier frequencies. Thus, four down−mixed (baseband)
signals are obtained.
After low−pass filtering, the in−phase and quadrature
components of each carrier are combined. The resulting two
signals are a measure of the energy at each carrier frequency.
These energy levels are further processed in the firmware.
The firmware will demodulate the value of the bit (i.e.,
decide between a 0 or 1 bit) by weighing the energy over a
period of 8 chip clocks. Refer to the firmware data sheets for
details.
Automatic Gain Control (AGC)
In order to extend the range of the analogue−to−digital
convertor, the receiver path contains a variable gain
amplifier. The gain can be changed in 8 steps from 0 to
−42 dB.
This amplifier can be used in an automatic gain control
(AGC) loop. The loop is implemented in digital hardware.
It measures the signal level after analogue−to−digital
conversion. The amplifier gain is changed until the average
digital signal is contained in a window around a percentage
of the full scale. An AGC cycle takes two chip clocks: a
measurement cycle at the rising edge of the CHIP_CLK and
an update cycle starting at the next chip clock.
Communication Controller
The Communication Controller block includes the
micro−processor and its peripherals (refer to Figure 33 for
an overview).
Low Noise Anti−aliasing Filter and ADC
The receiver has a 3rd order continuous time low pass filter
in the signal path. This filter is in fact the same block as in
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NCN49599
Communication Controller
Data / Program
RAM
Serial
Comm.
Interface
Program
ROM
TxD
RxD
BR0
BR1
ARM
Risc
Core
Timer 1 & 2
IO[9:0]
Local Port
DATA /PRES
TO
TRANSMIT
FROM
RECEIVER
POR
Interrupt
Control
RESB
Watchdog
Test
Control
Flash SPI
TEST
PC20 12053 0.4
SCK
SDI
SDO
CSB
SEN
Figure 33. The communication controller is based on a standard ARM Cortex M0 core
DATA/PRES pin. The function of this pin depends on the
register bit R_CONF[7].
If the bit is cleared (0), the preslot synchronization signal
(PRE_SLOT) appears on the pin.
If the bit is set (1), the modem outputs the baseband,
unmodulated, data. Thus, DATA/PRES is driven high when
a space symbol is being transmitted (i.e., the space
frequency fS appears on pin TX_OUT); it is driven low when
a mask symbol is transmitted (fM on TX_OUT).
The processor is an ARM Cortex M0 32−bit core with a
reduced instruction set computer (RISC) architecture,
optimized for IO handling. Most instructions complete in a
single clock cycle, including byte multiplication. The
peripherals include a watchdog, test and debug control,
RAM, ROM containing the boot loader, UART, two timers,
an SPI interface to optional external memory, I/O ports and
the power−on reset. The microcontroller implements
interrupts.
The 32 kB RAM contains the necessary space to store the
firmware and the working data. A full−duplex serial
communication block (the SCI section) allows interfacing to
the application microcontroller.
Testing
A JTAG debug interface is provided for development,
debugging and production test. An internal pull−down
resistor is provided on the input pins (TDI, TCK, TMS, and
TRSTB).
In practice, the end user of the modem will not need this
interface; this input pins may be tied to ground
(recommended) or left floating; TDO should be left floating.
The pin TEST enables the internal hardware test mode
when driven high. During normal operation, it should be tied
to ground (recommended) or left floating.
Local Port
Ten bidirectional general purpose input/output (GPIO)
pins (IO0..IO9) are provided. All general purpose IO pins
can be configured as an input or an output. In addition, the
firmware can emulate open−drain or open−source pins. All
pins are 5 V tolerant.
When the modem is booting, IO2 is configured as an input
and must be pulled low to enable uploading firmware over
the serial interface. At the same time, IO0 and IO1 are
configured as outputs and show the status of the boot loader.
A LED may be connected to IO0 to help with debugging.
After the firmware has been loaded successfully, IO0..IO2
become available as normal IOs.
Typically, the firmware provides status indication on
some IO pins; other IO pins remain available to the
application microcontroller as IO extensions.
The application microcontroller has also low−level access
to internal timing of the modem through the digital output
Serial Communication Interface (SCI)
The
Serial
Communication
Interface
allows
asynchronous communication with any device
incorporating a standard Universal Asynchronous Receiver
Transmitter (UART).
The serial interface is full−duplex and uses the standard
NRZ format with a single start bit, eight data bits and one
stop bit (Figure 34). The baud rate is programmable from
9600 to 115200 baud through the BR0 and BR1 pins.
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28
NCN49599
IDLE (mark)
LSB
Start
D0
MSB
D1
D2
tBIT
D3
D4
D5
D6
D7
IDLE (mark)
Stop
tBIT
8 data bits
1 character
PC20080523.3
Figure 34. Data Format of the Serial Interface
3V3_D
Serial data is sent from the NCN49599 to the application
microcontroller on pin TxD; data is received on pin RxD.
Both pins are 5 V tolerant, allowing communication with
both 3.3 V−and 5 V−powered devices.
On the open−drain output pin TxD an external pull−up
resistor must be provided to define the logic high level
(Figure 35). A value of 10 kW is recommended. Depending
on the application, an external pull−up resistor on RxD may
be required to avoid a floating input.
NCN49599
ARM
Risc
Core
TxD
RxD
Serial
Comm.
Interface
Application
Micro
Controller
BR0
BR1
8
IO[7:0]
Local Port
TXD/PRES
Communication Controller
+5V
Figure 36. Connection to the Application
Microcontroller
R
The baud rate of the serial communication is controlled by
the pins BR0 and BR1. After reset, the logic level on these
pins is read and latched; as a result, modification of the baud
rate during operation is not possible. The baud rate derived
from BR0 and BR1 is shown in Table 24.
Output
VSSD
Table 24. BR1, BR0 BAUD RATES
Figure 35. Interfacing to 5 V logic using a 5 V safe
output and a pull−up resistor
BR1
BR0
SCI Baud rate
0
0
115200
0
1
9600
1
0
19200
1
1
38400
BR0 and BR1 are 5 V safe, allowing direct connection to
5 V−powered logic.
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29
NCN49599
IDLE (mark)
LSB
Start
D0
tBIT
MSB
D1
D2
D3
D4
D5
D6
D7
IDLE (mark)
Stop
tBIT
8 data bits
1 character
Figure 37.
Watchdog
Configuration Registers
A watchdog supervises the ARM microcontroller. In case
the firmware does not periodically signal the watchdog it is
alive, it is assumed an error has occurred and a hard reset is
generated.
The behavior of the modem is controlled by configuration
registers. Some registers can be accessed by the user through
the firmware. Table 25 gives an overview of some
commonly exposed registers.
Table 25. NCN49599 CONFIGURATION REGISTERS
Register
Reset Value
R_CONF[7]
0
Function
R_CONF[2:1]
00b
R_CONF[0]
0
R_FS[15:0]
0000h
Step register for the space frequency fS
R_FM[15:0]
0000h
Step register for the mark frequency fM
R_ZC_ADJUST[7:0]
02h
R_ALC_CTRL[3]
0
R_ALC_CTRL[2:0]
000b
Pin DATA/PRES mode selection
Baud rate selection
Mains frequency
Fine tuning of phase difference between CHIP_CLK and rising edge of mains zero crossing
Automatic level control (ALC) enable
Automatic level control attenuation
Reset and Low Power
The concept of NCN49599 has a number of provisions to
have low power consumption. When working in transmit
mode the analogue receiver path and most of the digital
receive parts are disabled. When working in receive mode
the analog transmitter and most if the digital transmit parts,
except for the sine generation, are disabled.
When the pin RESB = 0 the power consumption is
minimal. Only a limited power is necessary to maintain the
bias of a minimum number of analog functions and the
oscillator cell.
NCN49599 has two reset modes: hard reset and soft reset.
The hard reset reinitializes the complete IC (hardware and
ARM) excluding the data RAM for the ARM. This
guarantees correct start−up of the hardware and the RAM.
A hard reset is active when pin RESB = 0 or when the power
supply VDD < VPOR (See Table 13). When switching on the
power supply the output of the crystal oscillator is disabled
until a few 1000 clock pulses have been detected, this to
enable the oscillator to start up.
BOOT LOADER
Booting from External Memory
During operation, the modem firmware is stored in the
internal random access memory (RAM). As this memory is
volatile, the firmware must be uploaded after reset.
The NCN49599 provides two mechanisms to achieve
this: the firmware may be stored in an external SPI memory
(Booting from External Memory section) or it may be
uploaded over the serial communication interface (the
Firmware Upload section).
During reset, the boot loader module in the modem can
retrieve the firmware from an attached memory.
To enable this mode, the boot control pin SEN must be
driven high and IO2 must be driven low; subsequently the
modem must be reset.
www.onsemi.com
30
NCN49599
NCN49599
EEPROM
LE25U20AQGTXG
SDO
SDI
Bootloader
SDI
SD0
SCK
SCK
CSB
CSB
Figure 38. Connecting an External SPI Memory to the Modem
The memory must be connected to the pins of the
dedicated serial peripheral interface (SPI), as shown in
Figure 38. Connecting an external SPI memory to the
modem. Figure 38. Any non−volatile memory with the
standard command set and three bytes addressing is
supported; is recommended.
The user must program the firmware into the external
memory starting from address 0. Four bytes must be added
at the end of the lowest 256−byte sector that can fit them, i.e.
either the sector containing the last byte of the firmware or
the next sector. These four bytes contain the checksum, the
number of sectors used, and the magical numbers A5H and
5AH. The checksum must be computed over the entire binary.
Between the four metadata bytes and the firmware,
zero−padding must be written.
This is illustrated in Table 26.
The tool PlcEepromGenerator.exe, provided by
ON Semiconductor, may be used to convert a binary
firmware file into a file that follows these requirements. The
latter can be written directly in the external memory.
As an example, if the firmware binary size is 618 bytes,
the first two 256−byte sector will be filled completely. The
last 106 bytes of the firmware binary will be written to the
third sector, followed by zero padding (256 − 106 − 4 = 146
bytes), followed by four bytes: checksum, 03H, A5H and
5AH.
Once the boot loader has finished copying the firmware to
the internal memory, the checksum is calculated and
compared to the stored checksum. If both match, the
processor is released from reset and the firmware starts
executing. IO2 subsequently becomes available as a normal
GPIO.
Table 26. Required contents of an external bootable SPI
memory for a binary firmware file of length N bytes
Firmware Upload Over the Serial Communication
Interface
Address
0
During reset, the boot loader module in the modem can
receive the firmware over the serial interface.
To enable this mode, the IO2 and the boot control pin SEN
must be driven low; subsequently the modem must be reset.
IO2 must remain low during the entire boot process; if
driven high during boot the boot loader terminates
immediately. To restart the boot loader, reset the modem.
As soon as the reset of the modem is released, the boot
loader process starts. When it is ready to receive the
firmware from the external microcontroller, the boot loader
will send a 02H (STX) byte.
Upon receiving this byte the user must send the byte
sequence specified in Table 27. The sequence contains a
checksum to verify correctness of the received binary image.
The CRC must be calculated over the firmware binary only
(excluding the magical number and the size). The program
crc.exe, provided by ON Semiconductor, can be used for this
calculation.
Content
Firmware binary
...
N
N+1
Zero padding, if required
...
100H • S + FBH
100H • S + FCH
Checksum
100H • S + FDH
S, the number of sectors used
100H • S + FEH
Magical number: A5H
100H • S + FFH
Magical number: 5AH
Where S is the number of sectors used:
www.onsemi.com
31
NCN49599
If these timing constraints are not satisfied the boot loader
will send a 15H (NAK) character and will reject any data
received until the application microprocessor stops sending
bytes for at least 100ms. The pause will restart the boot
loader, and a new STX character will be sent to the
application microcontroller to indicate this.
Once transmission has started, the maximal delay
between consecutive bytes is 20 ms. If this timing
constraints is not met, or if the checksum is incorrect, the
boot loader will send a 15H (NAK) character. This error also
occurs when the user attempts to upload a binary exceeding
the maximal size of 7F00H (32512) bytes. When the
application microcontroller receives this NAK, it should
transmit a CEH (mnemonic for ”clear error”) byte. This
informs the boot loader that the application microcontroller
understood the problem. Following the CEH byte, the
microcontroller may restart.
The timing constraints are illustrated in Figure 3.
Table 27. Byte sequence to be transmitted by the
application microcontroller during firmware upload
Value
Description
[ CEH ]
Should only be sent to restart the boot
loader process, in response to a NAK
character received from the modem
AAH
Magical number
Size (LSB)
Size (MSB)
Binary, first byte
The size of the entire firmware binary,
including the four bytes for the CRC at
the end
Contents of the firmware binary
...
Binary, last byte
CRC (LSB)
CRC, as calculated on the binary only
CRC (MSB)
Data transmission must start only after receiving the STX
byte. In addition, the first byte must be sent within 350 ms.
APPLICATION INFORMATION
For a system−level overview of power line
communication, refer to [7]. For more information on how
to design with the NCN49599 modem, refer to the design
manual available from your sales representative [1]. This
section gives a few hints.
The analogue and digital blocks of the modem itself are
powered through independent power supply pins (VDDA
resp. VDD); the nominal supply voltage is 3.3 V. On both
pins, decoupling must be provided with at least a ceramic
capacitor of 100 nF between the pin and the corresponding
ground (VSSA resp. VSS). The connection path of these
capacitors on the printed circuit board (PCB) should be kept
as short as possible in order to minimize the parasitic
inductance.
It is recommended to tie both analogue and digital ground
pins to a single, uninterrupted ground plane.
Supplies and Decoupling
For optimal stability and noise rejection, all power
supplies must be decoupled as physically close to the device
as possible.
The line driver is primarily powered through the pin VCC.
Large currents are drawn from this supply rail if the
amplifiers are loaded. Two ceramic capacitors of 10 mF and
100 nF to ground are recommended at this point (Figure 39).
Of course, the 100 nF capacitor must be nearest to the
device.
12 V
FB
3.3 V
10 mF
100 nF
VCC
6
NCN49599
VCC
B−
1
53
54
2
3
55
56
B+
VEE
Figure 39. Decoupling Capacitors − Line Driver
www.onsemi.com
32
NCN49599
POWER
GROUND
ÌÌÌÌÌÌ
ÌÌ’’
ÌÌ
ÌÌÌÌÌÌ
ÌÌ
ÌÌ
’’
##
%%
$$
ÌÌÌÌÌ
ÌÌ
##
&&
ÌÌ
ÌÌ
ÌÌÌÌ
ÌÌÌÌÌÌ
ÌÌ
ÌÌÌÌ
ÌÌ
ÌÌÌÌÌÌ
ÌÌ
ÕÕÌÌ
ÚÚ
ŠŠ
ÜÜ
ÑÑ
Ô
Ó
ÒÒ
ÌÌÌÌ
ÕÕ
ÌÌ
ÑÑ
ÛÛ
Ì
ÌÌÌÌÌ
ÖÖ
ÌÌÌÌ
Ì
ÌÌÌÌÌ
ANALOG
GROUND
C21
C20
C11
12V SUPPLY
VEE
REF_OUT
VSSA
VDDA
43
44
45
46
47
48
49
50
51
52
VSS
53
VDD
54
C19
55
VEE
56
Ì
Ì
ÌÌ
ÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌÌ
3,3V SUPPLY
VCC
3,3V SUPPLY
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
12
31
13
30
14
29
28
27
26
25
24
22
ÌÌ
ÌÌ
ÌÌÌ
Ì
ÌÌ
Ì
Ì
"
ÌÌÌÌ
ÙÙ
Ì
ÌÌ
ÌÙÙ
ÌÌ
!
¦
Ž
Ÿ
¦
Ì̦¦
Ì
!
ÌÌ
23
21
20
19
17
18
16
15
PC20120831.1
NC
VDD
VDD1V8
3,3V SUPPLY
C15
C18
VSS
Figure 40. Recommended layout of the placement of decoupling capacitors (bottom ground plane not shown)
Internal Voltage Reference
Exposed Thermal Pad
REF_OUT is the analogue output pin which provides the
voltage reference used by the A/D converter. This pin must
be decoupled to the analogue ground by a 1 mF ceramic
capacitance CDREF. The connection path of this capacitor to
the VSSA on the PCB should be kept as short as possible in
order to minimize the serial inductance.
The line driver output amplifier in the NCN49599 is
capable of delivering 1.5 A into a complex load.
Output signal swing should be kept as high as possible.
This will minimize internal heat generation, reducing the
internal junction temperature. The line driver in the
NCN49599 can swing to within 1 V of either rail without
adding distortion.
An exposed thermal pad is provided on the bottom of the
device to facilitate heat dissipation. The printed circuit
board and soldering process must be carefully designed to
minimize the thermal resistance between the exposed pad
and the ambient. Refer to [1,8] for more information.
Internal Voltage Regulator
An internal linear regulator provides the 1.8 V core
voltage for the microcontroller. This voltage is connected to
pin VDD1V8. A ceramic decoupling capacitor of 1 mF to
ground must be connected as close as possible to this pin
(Figure 40).
The internal regulator should not be used to power other
components.
Table 28. DEVICE ORDERING INFORMATION
Temperature Range
Package Type
Shipping†
NCN49599MNG
−40°C – 125°C
QFN−56
Tube
NCN49599MNRG
−40°C – 125°C
QFN−56
Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
33
NCN49599
REFERENCES
5. IEC. IEC 61334−5−1. Distribution automation
using distribution line carrier systems – Part 5−1:
Lower layer profiles – The spread frequency shift
keying (S−FSK) profile. Online at
http://webstore.iec.ch/preview/info_iec61334−5−1
%7Bed2.0%7Db.pdf
6. ON Semiconductor. Mains synchronisation for
PLC modems (application note). 2013−03−01. The
latest version is available from your sales
representative.
7. ON Semiconductor. AND9165/D. Getting started
with power line communication (application note).
2014−11−01. Online at
http://www.onsemi.com/pub_link/Collateral/AND
9165−D.PDF
8. ON Semiconductor. AND8402/D. Thermal
Considerations for the NCS5651 (application
note). 2014−08−01. Online at
http://www.onsemi.com/pub/Collateral/AND8402
−D.PDF
In this document references are made to:
1. ON Semiconductor, Design Manual NCN49597/9,
December 2014. The latest version is available
from your sales representative.
2. CENELEC. EN 50065-1: Signaling on
low−voltage electrical installations in the
frequency range 3 kHz to 148,5 kHz. 2011−04−22.
Online at
http://www.cenelec.eu/dyn/www/f?p=104:110:102
2556227334229::::FSP_ORG_ID,FSP_PROJECT,
FSP_LANG_ID:821,22484,25
3. Électricité réseau distribution France (ERDF).
Linky PLC profile functional specification.
2009−09−30. Online at
http://www.erdfdistribution.fr/medias/Linky/ERD
F−CPT−Linky−SPEC−FONC−CPL.pdf.
4. DLMS User Association. DLMS/COSEM
Architecture and Protocols (“Green book”). 7th
edition. Online at
http://www.dlms.com/documentation/dlmsuacolou
redbookspasswordprotectedarea/index.html
www.onsemi.com
34
NCN49599
PACKAGE DIMENSIONS
QFN56 8x8, 0.5P
CASE 485CN
ISSUE O
ÉÉ
ÉÉ
PIN ONE
LOCATION
A B
D
L1
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
TOP VIEW
DETAIL B
0.10 C
A1
C
0.10
D2
DETAIL A
MOLD CMPD
ALTERNATE
CONSTRUCTION
SIDE VIEW
NOTE 4
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
DETAIL B
(A3)
A
0.08 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25mm FROM THE TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÉÉ
ÉÉ
ÉÉ
EXPOSED Cu
0.15 C
0.15 C
L
L
RECOMMENDED
MOUNTING FOOTPRINT*
C A B
M
56X
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
8.00 BSC
6.50
6.70
8.00 BSC
6.50
6.70
0.50 BSC
0.20
−−−
0.30
0.50
0.05
0.15
8.30
L
0.10
M
56X
6.74
C A B
0.60
1
E2
8.30
6.74
1
K
56
e
e/2
BOTTOM VIEW
56X
b
0.10
M
C A B
0.05
M
C
PKG
OUTLINE
NOTE 3
0.50
PITCH
56X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCN49599/D