A8672 Datasheet

A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Features and Benefits
Description
• High efficiency integrated FETs optimized for lower duty
cycle voltage conversion: 27 mΩ high side, 12 mΩ low side
• Power input voltage range: 3 to 16 V
• Control input voltage range: 4.5 to 16V
• Adjustable output voltage, down to 0.6 V
• 5 V LDO Regulator
• Extremely short minimum controllable on-time;
example: allows 12 V conversion to 0.6 V at >1 MHz
• Reference accuracy of ±1% throughout temperature range
¯T̄
¯ and Power OK pins for operating and
• F̄¯Ā¯Ū¯L̄
protection modes
• Low power mode (LPM) or fixed continuous conduction
mode (FCCM) operation
• Programmable soft-start / hiccup shutdown period
• Ultra-fast transient response
The A8672 is a synchronous buck converter capable of
delivering up to 8 A. The A8672 utilizes valley current mode
control, allowing very short on-times to be achieved. This makes
it ideal for applications that require very low output voltages
relative to the input voltage, combined with high switching
frequencies. Valley current mode control inherently provides
improved transient response over traditional switcher schemes,
through the use of a voltage feedforward loop and frequency
modulation during large signal load changes.
The A8672 includes a comprehensive set of diagnostic flags,
allowing the host platform to react to a myriad of different
conditions. A fault output indicates when either the temperature is becoming unusually high, or a single point failure
has occurred; for example, the switching node (LX) shorted to
ground, or the timing resistor going open-circuit. A Power OK
(POK) output is also provided after a fixed delay, to indicate
when the output voltage is within regulation. The selectable
pulse-by-pulse current limit avoids the requirement to oversize
the inductor to cope with large fault currents.
Applications
• Servers
• Point of load supplies
• Network and telecom
• Storage
Package: 28-contact QFN with exposed
thermal pad (suffix EG)
The device package (EG) is a 28-contact, 4 mm × 5 mm,
0.75 mm nominal overall height QFN with exposed thermal
pad. The package is lead (Pb) free, with 100% matte tin
leadframe plating.
Approximate size
Typical Application Diagram
C5
47 nF
VIN
12 V
C1
22 μF
C8
2.2 μF
C2
22 μF
C3
22 μF
C9
470 nF
C4
22 μF
R1
90.9kΩ
VIN
BOOT
TON
A8672
L1
1 μH
LX
C6
100 μF
FB
ILIM
EN
R2
20 kΩ
FAULT
POK
COMP
FAULT
R5
56 k Ω
POK
SS
C10
10 nF
R4
249 k Ω
PAD
R3
20 kΩ
AGND
PGND
C11
680 pF
VIN = 12 V, VOUT = 1.2 V, and fSW = 500 kHz
A8672-DS
C7
100 μF
R6
10 kΩ
VDD
VREG
BIAS
MODE
Vpull-up
VOUT
1.2 V
C12
22 pF
R7
10 kΩ
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Selection Guide
Part Number
Packing*
A8672EEGTR-T
1500 pieces per 7-inch reel
*Contact Allegro™ for additional packing options
Absolute Maximum Ratings
Characteristic
Symbol
VIN, VDD, TON, VREG, BIAS and EN
Pin Voltage
VI
LX Pin Voltage
BOOT Pin Voltage
VLX
VBOOT
All Other Pins
–
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Notes
Rating
Unit
With respect to GND
–0.3 to 18
V
With respect to GND
–0.6 to VIN + 0.3
V
–2.0
V
VLX – 0.3 to
VLX + 8.0
V
t < 50 ns, with respect to GND
With respect to GND
–0.3 to 7.0
V
–40 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
E temperature range
Table of Contents
Specifications
Thermal Characteristics
Functional Block Diagram
Pin-out Diagram and Terminal List
Electrical Characteristics
Functional Description
Basic Operation
Output Voltage Selection
Switch On-Time and Switching Frequency
Valley Current Limit
Inductor Selection
2
3
3
4
5
7
7
7
7
8
8
Output Capacitor Selection
Input Capacitor Selection
Soft-Start and Output Overloads
Fault Handling and Reporting
Control Loop
Control Loop Design Approach
Thermal Considerations
Regulator Efficiency
9
9
10
12
14
15
18
19
Layout
20
Package Outline Drawing
21
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Functional Block Diagram
VDD
5V LDO
Regulator
EN
BOOT VIN
BIAS
Bias
Regulator
LX
Enable
VREG
Driver
On
Timer
TON
Control
Logic
Driver
BIAS
Off
Timer
-
ILIM
MODE
+
Current
Amplifier
Hiccup
+
VDD UVLO
FB OV
FB UV
TOT
FB OV
-
Regulator
Comparator
Fault
Reporting
and
Shutdown
Offset
OV Ref
+
Overvoltage
Comparator
TSD
+
FB UV
POK
FAULT
Undervoltage
Comparator
-
gm Amplifier
-
FB
+
Hiccup
UV Ref
Ref
FB
COMP
PAD
PGND
-
Soft Start
and Hiccup
Period
0.6 V
Ref
SS
AGND
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Package Thermal Resistance (Junction to Ambient)
RθJA
Package Thermal Resistance (Junction to Pad)
RθJP
Test Conditions*
Estimated, on 4-layer PCB based on JEDEC
standard
Value
Unit
33
ºC/W
2
ºC/W
*Additional thermal information available on the Allegro website
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
23 BIAS
24 MODE
25 ILIM
26 SS
28 FB
AGND
1
22 LX
PGND
2
21 LX
PGND
3
PGND
4
PGND
5
18 LX
PGND
6
17 LX
VIN
7
16 LX
VIN
8
15 BOOT
20 LX
EN 14
19 LX
POK 13
FAULT 12
VREG 11
VDD
9
PAD
TON 10
Pin-out Diagram
27 COMP
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Terminal List Table
Number
Name
Function
1
AGND
Analog ground. Connect to PGND at PAD of device. This pin should be used as the FB resistor divider
ground reference for optimal accuracy (see Typical Applications section circuit diagrams).
2,3,4,5,6
PGND
Power ground. Connect to PAD of device.
7,8
VIN
Power input to the drain of the internal high-side MOSFET. This pin must be locally bypassed (see Typical
Applications section circuit diagrams).
9
VDD
Power input for the control circuit and drive signals for the internal switching MOSFETs. This pin can be
either connected directly to VIN, or in applications where a low VIN voltage is used, it can be driven by a
separate power source to ensure adequate overdrive of the switching MOSFETs and control supply.
10
TON
On-Time pin. The resistor connected between this pin and VIN defines the on-time of the regulator. This in
turn defines the switching frequency for a given output voltage.
11
VREG
5 V LDO regulator output and supply for internal control circuitry.
12
¯ĀŪ¯L̄¯T̄
¯
F̄
¯ĀŪ¯L̄¯T̄
¯ output. This pin is logic low if the on-time exceeds a certain value, if the LX node is
Open drain F̄
shorted to ground, or if the thermal shutdown threshold (TJ > 140°C) has been reached (see Fault Handling
and Reporting table).
13
POK
Open drain Power Okay (power good) output. This pin is logic low if any fault (as defined in the Fault
Handling and Reporting table) occurs, other than an overtemperature condition (TJ > 140°C).
14
EN
Enable pin. This pin is a logic input that turns the converter on or off. When EN > VENHI , the part turns on.
15
BOOT
High-side gate drive supply input. This pin supplies the drive for the high-side switching MOSFET switch.
16,17,18,19,
20,21,22
LX
23
BIAS
24
MODE
25
ILIM
26
SS
27
COMP
28
FB
Feedback input pin of the error amplifier. Connect a resistor divider from the converter output voltage node,
VOUT, to this pin to set the converter output voltage. This pin is also monitored for both output overvoltage
and undervoltage conditions (see Fault Handling and Reporting table for more details).
–
PAD
Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the
PCB. This pad must be soldered to the PCB for proper operation and should be connected to the ground
plane by through-hole vias (see Layout section for further details).
The source of the internal high-side switching MOSFET. The output inductor and BOOT capacitor should be
connected to this pin (see Typical Applications section circuit diagrams).
Internal regulated bias supply for the control circuit and drives for switching MOSFETs (see Typical
Applications section circuit diagrams for recommended capacitors).
When pulled to the VREG supply via a 10 kΩ resistor, fixed continuous conduction mode (FCCM) is
maintained across the full load range. When pulled directly to GND, the switcher enters lower power mode
(LPM) at light loads.
Valley current limit setting. Connect a resistor to ground to set a voltage between 2.75 and 1.5 V that
corresponds to a valley overload current of between 9 and 3 A (typ).
Soft-start ramp pin. The capacitor connected to this pin defines the rate of rise of the output voltage and
the effective inrush current. Soft-start also defines the hiccup shutdown period with either an overload or
overvoltage condition.
Output of the error amplifier and compensation node. Connect a series R-C network from this pin to GND for
control loop regulation.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
ELECTRICAL CHARACTERISTICS1 Valid at TJ = –20°C to 125°C and VIN = 12 V; unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
General
Input Voltage Range (Power)
VIN
3
–
16
V
Input Voltage Range (Control)
VDD
4.5
–
16
V
Input VIN Leakage Current
Ileak
Input VDD Quiescent Current
IDD
Feedback Voltage
VFB
Maximum Switching Frequency
fsw(max)
Minimum Switching Frequency
fsw(min)
On-Time Tolerance
Δton
VIN = 12 V, LX = GND
–
–
5
μA
VEN = 5 V, VFB = 1.2 V, no switching
–
–
3
mA
μA
VDD = 16 V, VEN = 0 V
7.0 V ≤ VIN ≤ 16 V, VFB = VCOMP
RTON = 60 kΩ
–
1
10
0.594
0.600
0.606
V
–
1000
–
kHz
–
200
–
kHz
–10
–
10
%
Maximum On-Time Period
ton(max)
2.5
3.5
4.5
μs
Minimum On-Time Period
ton(min)
–
50
90
ns
–
–
350
ns
–
27
–
mΩ
Minimum Off-Time Period
toff(min)
High-Side MOSFET On-Resistance
RDS(on)HS
Low-Side MOSFET On-Resistance
RDS(on)LS
Soft Start Source Current2
Soft Start Sink
Current2
Soft Start Threshold
Soft Start Ramp Time1
ISS(src)
IDS = 0.2 A
IDS = 0.2 A
–
12
–
mΩ
VSS > VSSPWM
–
–30
–
μA
–
5
–
μA
VSS rising
–
600
–
mV
CSS = 10 nF
–
200
–
μs
4.75
5.00
5.25
V
–
±50
±250
nA
ISS(snk)
VSSPWM
tSS
5 V LDO Regulator
Output Voltage
VREG
IREG = 0 to 30 mA, VIN > 6 V
Amplifier and Power Stage Gain
Feedback Input Bias Current2
IFB
VFB = 0.6 V
Error Amplifier Open Loop Voltage
Gain1
AVEA
–
60
–
dB
Error Amplifier Transconductance1
gmCOMP
600
800
1000
μA/V
Error Amplifier Maximum Source/Sink
Current2
ICOMP(max) VFB = VFB0 ±0.4 V
–
±52
–
μA
COMP Voltage to Current Gain1
gmPOWER
–
4
–
A/V
Enable High Threshold
VENHI
1.8
–
–
V
Enable Low Threshold
VENLO
–
–
0.8
V
Enable Hysteresis
VENHYS
150
250
–
mV
–
50
–
μA
Enable
Enable Current2
IEN
VEN = 3.3 V
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
ELECTRICAL CHARACTERISTICS1 (continued) Valid at TJ = –20°C to 125°C and VIN = 12 V; unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Power OK
Power Good Threshold (Rising)
VPOK(HI)
Feedback voltage relative to reference voltage,
POK = high
92
95
98
%
Power Good Threshold (Falling)
VPOK(LO)
Feedback voltage relative to reference voltage,
POK = high
107
110
113
%
Power Good Hysteresis
VPOKHYS
POK= low
–
5
–
%
POK Rising Delay
tdPOK
–
90
–
μs
POK Output Voltage
VPOK
IPOK = 10 mA, POK asserted
–
–
500
mV
POK Leakage Current
IPOK
VPOK = 5.5 V, POK not asserted
–
–
1
μA
TOT
Fault Reporting
¯ĀŪ¯L̄¯T̄
¯ Overtemperature
F̄
Temperature rising
–
140
–
°C
¯ĀŪ¯L̄¯T̄
¯ Overtemperature Hysteresis
F̄
TOTHYS
Fault release = TOT – TOTHYS
–
20
–
°C
¯ĀŪ¯L̄¯T̄
¯ Output Voltage
F̄
VFAULT
IFAULT = 10 mA, fault asserted
–
–
500
mV
¯ĀŪ¯L̄¯T̄
¯ Leakage
F̄
IFAULT
VFAULT = 5.5 V, fault not asserted
–
–
1
μA
Undervoltage Threshold (Falling)
VUVFB
Feedback voltage relative to reference voltage
–
75
–
%
Undervoltage Hysteresis
VUVHYS
–
5
–
%
115
120
125
%
–
5
–
%
Protection
Overvoltage Threshold (Rising)
VOVFB
Overvoltage Hysteresis
VOVHYS
Valley Current Limit Voltage Range
Valley Current Limit
Feedback voltage relative to reference voltage
ILIMVR
ILIM
1.0
–
2.75
V
ILIM resistor = 169 kΩ
3.0
4.0
5.0
A
ILIM resistor = 249 kΩ
6.0
8.0
10.0
A
Either valley current limit or overvoltage
condition reached
–
50
–
μs
Hiccup On Period1
tHICOC
CSS = 10 nF, first shutdown event
–
10
–
ms
Hiccup Shutdown Period1
tHICSD
CSS = 10 nF, second and subsequent shutdown
events
-
1.2
-
ms
Pulse-by-Pulse Negative Valley
Current Limit
INLIM
FCCM selected
–2.4
–1.9
–1.4
A
FB Overvoltage Duration
tUVFB
High-side MOSFET off, low-side MOSFET on
–
50
–
μs
High-Side MOSFET Protection Current
IHIPRO
LX node short-circuited to GND
–
25
–
A
High-Side MOSFET Protection Voltage
VHIPRO
LX node short-circuited to GND
450
650
850
mV
VDD Undervoltage Lockout (Rising)
VDD Undervoltage Lockout Hysteresis
VUVLO
–
4.2
4.45
V
VUVLOHYS
–
300
–
mV
Temperature rising
–
165
–
°C
Recovery = TSD – TSDHYS
–
15
–
°C
Thermal Shutdown Threshold
TSD
Thermal Shutdown Hysteresis
TSDHYS
1Specifications
throughout the junction temperature, TJ , range of –20ºC to 125ºC are assured by design and characterization unless otherwise noted.
2Positive current is into the node or pin, negative current is out of the node or pin.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Characteristic Performance
Efficiency at 300 kHz, Input Voltage = 12 V
100
VOUT = 5 V
VOUT = 3.3 V
VOUT = 2.5 V
Efficiency (%)
90
VOUT = 1.2 V
80
Fixed conƟnuous conducƟon mode
Inductor series: Pulse PG0642NL
70
0
1
2
3
4
5
6
Load Current (A)
Efficiency at 500 kHz, Input Voltage = 12 V
100
VOUT = 5 V
VOUT = 3.3 V
VOUT = 2.5 V
Efficiency (%)
90
VOUT = 1.2 V
80
Fixed conƟnuous conducƟon mode
Inductor series: Pulse PG0642NL for V OUT = 1.2 V to 3.3 V,
Pulse PG0871 for V OUT = 5 V
70
0
1
2
3
4
5
6
Load Current (A)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Functional Description
Basic Operation
At the beginning of a switching cycle, the high-side switch is
turned on for a duration determined by the current flowing into
TON. The magnitude of current is determined by the value of the
input voltage and the value of the on-time resistor (RTON, R1 in
the Typical Applications section circuit diagrams).
During the on-time period, the current builds up through the
inductor at a rate determined by the voltage developed across it
and the inductance value. When the on-time period elapses, the
output of an RS latch resets, turning off the high-side switch.
After a small dead-time delay, the low-side switch is turned on.
The current through the inductor decays at a rate determined
by the output voltage and the inductance value. The current is
sensed through the low-side switch and is compared to the current demand signal. The current demand signal is generated by
comparing the output voltage (stepped down to the FB pin) with
an accurate reference voltage.
When the current through the low-side switch drops to the current
demand level, the low-side switch is turned off. After a further
dead-time delay, the high-side switch is turned on again, and the
process is repeated.
Output Voltage Selection
The output voltage (VOUT) of the converter is set by selecting the
appropriate feedback resistors using the following formula:
VOUT = VFB
where:
R6
+ 1 + IFB
R7
R6 R7
R6 + R7
(1)
VFB is the reference voltage,
R6 and R7 are as shown in the Typical Applications section
circuit diagrams, and
IFB is the reference bias current.
It is important to consider the tolerance of the feedback resistors,
because they directly affect the overall setpoint accuracy of the
output voltage.
It is also important to consider the actual resistor values selected
and consider the trade-offs. High value resistors will minimize
the shunt current flowing through the feedback network, enhancing efficiency. However, the offset error produced by the refer-
ence bias current will increase, affecting the regulation. In addition, high value resistors are more prone to noise pick-up effects
which may affect performance. As some kind of compromise, it
is recommended that R7 be in the region of 10 kΩ.
Switch On-Time and Switching Frequency
The switching frequency of the converter is selected by choosing
the appropriate on-time. The on-time can be estimated to a first
order by using the following formula:
ton =
VOUT
VIN
1
fSW
(2)
where:
VOUT is the output voltage,
fSW is the switching frequency, and
VIN is the nominal input voltage.
To factor-in the effects of resistive voltage drops in the converter
circuit, the following formula can be used to produce a more
accurate estimate of what the on-time has to be for a required
switching frequency:
ton =
VOUT + (RDS(on)LS + DCRL ) IOUT
VIN + (RDS(on)LS – RDS(on)HS ) IOUT
1
fSW
(3)
where:
RDS(on)LS
is the low-side MOSFET on-resistance,
RDS(on)HS
is the high-side MOSFET resistance, and
DCRL is the inductive resistance.
The switching frequency will vary slightly as the resistive voltage
drops in the circuit change, either due to temperature effects or to
input voltage variations.
Note that when selecting the switching frequency, care should
be taken to ensure the converter does not operate near either the
minimum on-time (50 ns) or the minimum off-time (250 ns).
Minimum on-times will typically occur in combinations of
maximum input voltage, minimum output voltage with minimum
load, and maximum switching frequency. Minimum off-times
will typically occur in combinations of minimum input voltage,
maximum output voltage with maximum load, and maximum
switching frequency.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
The ton from either of the above formulae can be used to determine the TON resistor value, RTON (R1 in Typical Applications
section circuit drawings):
RTON = (VIN – 0.67)
ton – 8 ×10–9
– 500
25 ×10–12
(4)
Table 1 provides preferred resistor values for a given output
voltage at target switching frequencies of 500 kHz, 700 kHz, and
1 MHz:
Valley Current Limit
The Valley Current Limit ( ILIM ) threshold can be programmed to
any level between 9 and 3 A by selecting an appropriate resistor
(RLIM ) connected between the ILIM pin and ground. The resistor
can be selected either by using the following formula, or by using
the graph in figure 1 for the typical Valley Current Limit:
RLIM = (21.8 × ILIM ) + 79
(5)
where RLIM is in kΩ.
The maximum peak-to-peak ripple current occurs at the maximum input voltage. To a reasonable approximation, the minimum
duty cycle can be found:
VOUT
(6)
D(min) =
VIN (max)
The required (minimum) inductance can be found:
L(min) =
VIN –VOUT
Iripp
D(min)
1
fSW
Note that the inductor manufacturer tolerances on the inductance
value should be taken into account. This can be as high as ±30%.
It is recommended that gapped ferrite solutions be used as
opposed to powdered iron solutions. This is because powdered
iron cores exhibit relatively high core losses, especially at higher
switching frequencies. Higher core losses do have a detrimental
impact on the long term reliability of the component.
Inductors are typically specified at two current levels:
Inductor Selection
The main factor in selecting the inductance value is the ripple
current. The ripple current affects the output voltage ripple and
current limit. A reasonable figure of merit for the ripple current
(Iripp) is 25% of the maximum load. So for a maximum load of
6 A, the peak-to-peak ripple current should be 1.5 A.
• Saturation Current (Isat) The worst case maximum peak cur-
rent should not exceed the saturation current and indeed some
margin should be allowed. The maximum peak current in an
inductor occurs during an overload condition where the circuit
operates in current limit. The typical valley current limit (ILIM)
is 8 A, with R4 = 249 kΩ. The peak current through the inductor
is effectively the valley current limit plus the ripple current:
Isat > ILIM + Iripp
Switching Frequency, fSW
VOUT
(V)
RTON
(kΩ)
700 kHz
VOUT
(V)
RTON
(kΩ)
1 MHz
VOUT
(V)
RTON
(kΩ)
5.0
374
5.0
267
5.0
182
3.3
243
3.3
174
3.3
121
2.5
187
2.5
133
2.5
90.9
1.8
137
1.8
95.9
1.8
64.9
1.5
113
1.5
80.6
1.5
54.9
1.2
90.9
1.2
63.4
1.2
43.2
1.0
76.8
1.0
52.3
1.0
35.7
0.8
60.4
0.8
42.2
0.8
28.7
0.6
44.2
0.6
30.9
0.6
23.2
(8)
300
ILIM Resistor Value, RLIM (kΩ)
Table 1. Recommended RTON Resistor Values
500 kHz
(7)
250
200
150
100
50
0
2
4
6
8
10
Valley Current Limit (Typical), ILIM (A)
Figure 1. Valley Current Limit determination: value of external resistor on
ILIM pin versus valley current limit
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
• Rms Current (Irms) It is important to understand how the rms
current level is specified in terms of ambient temperature. Some
manufacturers quote an ambient whilst others quote a temperature that includes a self-temperature rise. For example, if an
inductor is rated for 85°C and includes a self-temperature rise of
25°C at maximum load, then the inductor cannot be safely operated beyond an ambient temperature of 60°C at full load.
The rms current through the inductor should not exceed the rating for the inductor, taking into account the maximum ambient
temperature. The maximum rms current is effectively the valley
current limit (ILIM) plus half of the ripple current:
Irms(max) > ILIM + Iripp / 2
(9)
A final consideration in the selection of the inductor is the series
resistance (DCR). A lower DCR will reduce the power loss and
enhance power efficiency. The trade-off in using an inductor with
a relatively low DCR is the physical size is typically larger.
Recommended inductor: PIMC065T-XXMN-11 (XX is value)
series manufactured by Cyntec or the PG0871 series manufactured by Pulse Electronics. Table 2 provides preferred inductor
values for a given output voltage, 2 A output at target switching
frequencies of 500 kHz, 700 kHz, and 1 MHz.
Output Capacitor Selection
The output capacitor has two main functions: influence the control loop response (see the Control Loop section), and determine
the magnitude of the output voltage ripple.
The output voltage ripple can be approximated to:
Vripp =
Iripp
8
(10)
fSW COUT
where:
Iripp is the peak-to-peak current in the inductor (see the Inductor
Selection section), and
COUT is the output capacitance.
It is recommended that ceramic capacitors be used, taking into
account: size, cost, reliability, and performance. It is imperative
that ceramic type X5R or X7R are used. On no account should
Y5V, Y5U, Z5U, or similar be used, because the capacitance
tolerance and the temperature stability is very poor.
There is generally no need to consider the effects of heating
caused by the ripple current flowing into the output capacitor.
This is because the equivalent series resistance (ESR) of ceramic
capacitors is extremely low.
When using ceramic capacitors, it is important to consider the
effects of capacitance reduction due to the E-field. To avoid this
voltage bias effect, it is recommended that the capacitor rated
voltage be at least twice that of the actual output voltage. So for
example, with a 5 V output, the capacitor should be rated to 10 V.
For the majority of applications, a capacitance of 200 μF is recommended to ensure good transient response.
Table 2. Recommended Inductor Values
Switching Frequency, fSW
500 kHz
700 kHz
1 MHz
VOUT
(V)
L
(μH)
VOUT
(V)
L
(μH)
VOUT
(V)
L
(μH)
5.0
3.7
5.0
2.6
5.0
2.2
3.3
3.7
3.3
2.2
3.3
1.7
2.5
2.6
2.5
1.7
2.5
1.2
1.8
2.2
1.8
1.7
1.8
1
1.5
1.7
1.5
1.2
1.5
1
1.2
1.2
1.2
1
1.2
0.8
1.0
1.2
1.0
1
1.0
0.54
0.8
1
0.8
0.8
0.8
0.47
0.6
0.8
0.6
0.47
0.6
0.47
Input Capacitor Selection
The function of the input capacitor is to provide a low impedance
shunt path for the current drawn by the A8672 when the highside switch is on. This minimizes the amount of ripple current
reflected back into the source supply. This reduces the potential
for higher conducted electromagnetic interference (EMI).
In a correctly designed system, with a quality capacitor positioned adjacent to the VIN pin and the PGND pin, this capacitor
should supply the high-side switch current minus the average
input current. During the high-side switch off-cycle, the capacitor
is charged by the average input current.
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Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
The effective rms current that flows in the input filter capacitor is:
1/
2
VOUT IOUT
VIN
(11)
Irms =
–1
VOUT
VIN
The amount of ripple voltage (Vripp ) that appears across the
input terminals (VIN with respect to GND) is determined by the
amount of charge removed from the input capacitor during the
high-side switch conduction time. If a capacitor technology such
as an electrolytic is used, then the effects of the ESR should also
be taken into account.
The amount of input capacitance (CIN) required for a given ripple
voltage can be found:
CIN =
where:
Irms ton
Vripp
(12)
ton is the on-time of the high-side switch (see the Switch OnTime and Switching Frequency section; note that maximum ton
occurs at minimum input voltage), and
CIN is the input filter capacitance.
As mentioned in the Output Capacitor Selection section, the
effects of voltage biasing should be taken into account when
choosing the capacitor voltage rating. If ceramic capacitors are
being used, then there is generally no need to consider the effects
of ESR heating.
Soft-Start, Output Overloads and Overvoltages
The soft-start routine controls the rate of rise of the reference
voltage, which in turn controls the FB pin, and thereby the output voltage (VOUT )(see figure 2). This function minimizes the
amount of inrush current drawn from the input voltage (VIN ) and
potential voltage overshoot on the output rail (VOUT ).
A soft-start routine is initiated when the enable pin (EN) is
high, no overvoltage exists on the output, the thermal protection circuitry is not activated, and VIN is above the undervoltage
threshold. Immediately after EN goes high, the soft-start capacitor is charged via an internal 10 μA source and PWM switching
action occurs.
The Soft-Start Ramp Time, tss , can be found from the following
formula:
C
0.6
tSS = SS
(13)
30 ×10 –6
where CSS is C11 in the Typical Application circuit diagrams.
During the Soft-Start Ramp Time (see A in figure 2), the reference is ramped from 0 up to 0.6 V, and the output voltage ( VOUT )
tracks the reference voltage. The POK flag is held low until the
output voltage reaches 95% (typical) of the target voltage and a
delay of 90 μs (typical) occurs.
When an output overcurrent event occurs, the regulator immediately limits the valley current at a constant level on a pulse-by
pulse basis. The output voltage will tend to fold back, depending
on how low the output impedance is. When the output voltage
drops below 90% (typical) of the target voltage, the POK flag
goes low. If the overload occurs for shorter than the Hiccup On
Period (<50 μs; B in figure 2), the output will automatically
recover to the target level. If the overload occurs for longer than
the Hiccup On Period (>50 μs; C in figure 2), the regulator
will shut down, the soft-start capacitor will be discharged, and
(assuming no other fault conditions exist and the enable pin is
still high) the regulator will be delayed by the Hiccup Shutdown
Period (D in figure 2).
The Hiccup Shutdown Period ensures that prolonged overload
conditions do not cause excessive junction temperatures to occur.
After the Hiccup Shutdown Period has elapsed, the output voltage is again brought up, controlled by the soft-start function.
However, if the overload condition still exists and still remains
after the Soft-Start Ramp Time has elapsed, the regulator will
shut down and the process will repeat until the fault is removed.
The Hiccup Shutdown Period is determined by the discharge of
the soft-start capacitor to zero voltage. During normal operation,
the soft-start capacitor CSS is charged to 5 V. In the event of an
overload where the Hiccup On Period exceeds 50 μs, the length
of the first Hiccup Shutdown Period event can be found:
tSS(first) = (CSS × 5) / 5 × 10–6
(14)
So for example, with a CSS of 10 nF, the first Hiccup Shutdown
Period event is 10 ms.
Assuming the overload is still applied, the length of the second
and subsequent Hiccup Shutdown Periods depends on the load
resistance applied and how far the soft-start capacitor is charged
before switching action occurs. The Hiccup Shutdown Period is
approximately ten times the length of the switching period.
The overvoltage protection operates in a similar way to the overcurrent protection using the same Hiccup Circuitry.
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Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Although the A8672 is optimized for ceramic output capacitors,
large value electrolytic capacitors can be used where either special hold-up, or power sequencing is required. Note the guidelines
for selecting large value capacitors in the Control Loop section.
When selecting larger-value output capacitors, it is important that
the soft-start period is appropriately scaled to take into account
the charging of these capacitors. For example, if the soft-start is
optimized for a 200 μF ceramic output capacitor and a 2000 μF
capacitor is added to the output, there is every possibility that the
converter will remain in an overload condition after the soft-start
and the Hiccup On Period have elapsed. This mode of operation
could prevent the output ever reaching the target output voltage.
To demonstrate the above, consider the following example: a
regulator programmed for a 5 V output, 200 μF output capacitor,
and a soft-start time-off of 1 ms.
Assume there is no load current draw until 5 V is reached. At
start-up, the regulator has to charge the output capacitor. From
C×V = I×t , the charging current into the capacitor is:
Enable (EN)
0V
Soft-Start (SS)
0V
A
A
Soft-Start Ramp Time
Soft-Start Ramp Time
Target output voltage
95% of
Target
Output Voltage
Target output voltage
95% of
Target
90% of
Target
0V
Valley Current Limit
Maximum load
Load Current
0A
B
<50 μs
Hiccup On
Period
Maximum load
C
>50 μs
Hiccup On
Period
D
90 μs
POK Delay
90 μs
POK Delay
Hiccup Shutdown
Period
90 μs
POK Delay
power OK (POK)
0V
Figure 2. Operation of the soft-start function
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Fixed Frequency High Current Synchronous Buck Regulator
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A8672
I = 200 μF × 5 / 1 ms = 1 A
Now if a 2000 μF capacitor is added to the output, the capacitor
would require a charge current of:
I = 2000 μF × 5 / 1 ms = 10 A
In this condition, the A8672 would run into the pulse-by-pulse
current limit, limiting the average charge current to 8.75 A (typ).
An average current of 8.75 A, assumes a valley current limit of
8 A and a half ripple current of 0.75 A. This means that after the
soft-start delay of 1 ms, the output voltage would only be charged
to:
V = 8.75 A × 1 ms / 2000 μF = 4.375 V
After the soft-start period is completed, the output capacitor
would be charged for a short duration, defined by the Hiccup On
Period. Then the converter would shut down and, after the Hiccup
Shutdown Period had elapsed, would enter the start-up process
again. This mode is highly undesirable and a more appropriate
soft-start capacitor should be selected.
The effects of adding an output capacitor with too-large value
would be a condition similar to starting-up into a short-circuit
across the output; where the regulator enters a hiccup mode of
operation.
If the output of the A8672 is pre-biased at start-up, the switcher
will remain in a high impedance state until the soft-start has
reached the feedback voltage ( VFB ) amplitude. This avoids the
output voltage being discharged. After the soft-start threshold
exceeds the FB pin voltage, PWM switching action occurs and
the output voltage is brought up under the control of the soft-start
circuit (see figure 3).
Note that when the regulator is turned off, it enters a high
impedance mode (all switches off) and if the output voltage is
discharged it is done so by the load (at A in figure 3). If the load
does not discharge the output, the output voltage remains in a
pre-biased condition.
Fault Handling and Reporting
Table 3 describes the action taken for particular faults including
¯T̄
¯ and POK flags.
the status of the F̄¯Ā¯Ū¯L̄
Enable (EN)
0V
Soft-Start/ Hiccup (SS)
0V
Soft-Start Ramp Time
Target output voltage
95% of
Target
Pre-biased output voltage
Output Voltage
0V
Soft-start voltage
less than feedback
voltage (VFB)
No PWM switching
Feedback voltage (VFB)
brought-up under
soft-start control
90 μs
PWM switching
POK Delay
A
Load pulls
the output
voltage low
Power OK (POK)
0V
Figure 3. Operation of the soft-start function with pre-biasing
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A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Table 3. Fault Handling and Reporting
A8672 Condition
95% (typ) < VFB < 110% (typ)
VFB < 95% (typ)
VFB < 90% (typ)
VFB > 120% (typ)
POK
Flag
¯T̄
¯
¯¯Ā¯¯Ū¯L̄
F̄
Flag
Normal operation.
High
High
–
During start-up, the feedback voltage (VFB)
is increased under control of the soft-start
circuit.
Low
High
–
After start-up, if an overload occurs for less
than the Hiccup On Period (50 μs), the
regulator maintains switching operation.
Low
High
Auto-recovery
After start-up, if an overload occurs for greater
than the Hiccup On Period (50 μs), the
regulator turns off for Hiccup Shutdown Period
and then initiates a soft-start cycle.
Low
High
Auto-restart under control of soft-start
High-side MOSFET turns off and low-side
MOSFET switching is maintained. If the
feedback voltage (VFB) drops to <75% of
target VFB (undervoltage condition) within
50 μs (Hiccup On Period), a soft-start is
performed.
Low
High
Soft-start is performed
Comments
Action After Fault
If the feedback voltage (VFB) does not drop to
<75% of target VFB within 50 μs (Hiccup On
Period), the low-side MOSFET is turned off
and the high-side MOSFET remains off for the
duration of the Hiccup Shutdown Period.
Low
High
After the Hiccup Shutdown Period, a soft start
is performed; then if the fault is not present,
normal operation occurs, otherwise the cycle
is repeated
VDD < 4.0 V (typ)
Regulator immediately turns off.
Low
High
Auto-restart under the control of the soft-start
circuit, when VIN > 4.2 V (typ)
TJ > 140°C (typ)
Regulator keeps operating until TSD
threshold is reached (TJ > 165°C (typ)), and
¯ goes high.
¯¯Ā¯¯¯Ū¯L̄¯T̄
then F̄
High
Low
–
TJ > 165°C (typ)
Regulator immediately turns off.
Low
Low
Auto-restart under the control of the soft-start
circuit, when TJ < 145°C
The voltage across the series switch
is monitored. If the voltage exceeds
500 mV (typ), the regulator latches off.
Low
Low
Restart by cycling either the Enable pin, EN,
or the input voltage pin, VIN, low then high;
restarts under the control of the soft-start
circuit
ton > 3.5 μs (typ)
Regulator immediately turns off.
Low
Low
Restart by cycling either the Enable pin, EN,
or the input voltage pin, VIN, low then high;
restarts under the control of the soft-start
circuit
Any of the internal bias
(BIAS), VREG regulator, or
bootstrap supply voltages
are below the respective
undervoltage threshold
Regulator immediately turns off.
Low
High
Auto-restart under the control of the soft-start
circuit when the low voltage rises above the
respective UVLO threshold: BIAS, VREG, or
BOOT
LX pin shorted to GND
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Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Control Loop
To a first order, the small-signal loop can be modeled as shown in
figure 4. The control loop can be broken into two sections: power
stage and error amplifier.
Power Stage
The power stage includes the output filter capacitor (COUT),
the equivalent load (RLOAD), and: the inner current loop, PWM
modulator, and power inductor, which together are modeled as
a transconductance amplifier with a gain of 4 A / V. The signal
Vc , supplied to the power stage, is effectively the load current
demand signal. This signal effectively controls the valley current
through the inductor; the higher the load the larger the Vc signal.
To simplify matters, we will assume this signal controls the average current through the inductor as opposed to the valley current.
The effective DC gain of the power stage, without the output
capacitor and load resistor, is 4 A / V, where the signal Vc is limited to the range 0.36 to 2.75 V. The DC current is converted into
VOUT as the current flows into the load resistor. The overall DC
gain of the power stage is given as VOUT / Vc (see figure 5). At full
load, the Vc signal would be 6 /4 = 1.5 V.
Power Stage
Amplifier
gm =
4 A/V
Vc
Il
VOUT
From a small-signal point of view, the power inductor behaves
like a current source; the inductor can be ignored as far as the
bandwidth of the loop is concerned. The output capacitor integrates the ripple current through the inductor, effectively forming
a single pole with the output load.
The power stage pole can be found:
1
fp(PS) =
2 × × COUT × RLOAD
(15)
It can be seen that as the load changes, the position of the power
pole changes in the frequency domain. This may seem like an
issue in terms of where to optimize the loop, however, the change
in load also changes the gain in the power stage, thus compensating for this effect. Figure 5 illustrates how the loop response of the
power stage changes with a varying load. The position of fp1 and
G1 is one solution, fp2 and G2 is another solution, and so forth.
As the value of RLOAD increases (reducing load), the power
pole moves down in frequency and the DC gain increases.
Generally speaking this is not a problem, because even if the
pole approaches the low frequency pole produced by the error
amplifier, there is still plenty of gain in the system. In this case,
while the phase margin may be greatly reduced, even to a value
approaching 0°, because there is sufficient DC gain in the loop it
can be shown from Nyquist theory that the system is conditionally stable. The phase margin must be considered only at the 0 dB
crossover frequency.
RLOAD
COUT
G1
FB Pin
COMP
Pin
C12
gm =
800 μA / V
R5
Ro
R6
R7
VOUT
Vc
G2
Gain
(dB)
G3
RLOAD
increasing
Ref
C11
Error Amplifier
Figure 4. 1st order model of the small-signal control loop (see Typical
Applications section circuit diagrams for component references)
f p2
f p1
Frequency
f p3
Figure 5. Power stage DC gain characteristic
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Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
It is recommended that X5R/ X7R ceramic capacitors be used,
however, large-value capacitors such as electrolytic types can
be used. Care should be taken when selecting the value of an
electrolytic capacitor. As this capacitance is increased, the power
pole is pushed to such a low frequency that the gain can fall off
sufficiently to cause a loop instability.
If using an electrolytic capacitor, consideration should also be
given to the equivalent series resistance (ESR) value, because
this introduces a zero with the capacitance itself. It is important
to use a low-ESR type capacitor. It should be noted that capacitor
manufacturers usually quote an ESR which is a maximum at a
particular frequency (such as 100 kHz) and temperature (20°C).
The ESR does vary with frequency and temperature, plus there
are tolerance effects as well. If the zero produced by the ESR
of the output capacitor features in the control loop, it is strongly
recommended that a large tolerance be allowed. If necessary, the
high frequency pole in the error amplifier can be used to negate
the effects of this pole (see the Error Amplifier section).
Error Amplifier
The error amplifier is a transconductance amplifier. The DC
gain of the amplifier is 60 dB (1000) and, with a gm value of
800 μA / V, the effective output impedance of the amplifier can be
modeled as:
RO =
1000
= 1.25 MΩ
800 ×10–6
(16)
The transconductance amplifier has a high DC gain to ensure
good regulation. The gain is rolled off with a single pole positioned at a low frequency. A zero is positioned at higher frequencies to cancel the effects of the main power stage pole. A second
pole can be introduced which should have minimal effect on the
loop response, but is useful for reducing the effects of switching
noise.
1
2 × × RO × C11
1
2 × × R5 × C11
fz(EA) =
(18)
The high frequency pole occurs at:
fp2(EA) =
1
2 × × R5 × C12
(19)
The potential divider formed by R6 and R7 in figure 4 effectively introduces a DC offset to the loop. This can be found from:
VFB / VOUT .
Control Loop Design Approach
There are many different approaches to designing the feedback
loop. The optimum solution is to select a target phase margin
and bandwidth for optimum transient response. This typically
requires either simulation software or detailed Bode plot analysis
to generate a solution.
The particular approach described here derives a solution through
a series of basic calculations. This approach aims for a simple
–20 dB/decade roll off, from the low frequency error amplifier
pole (fp1(EA) ) to the 0 dB crossover point (fcross ). The 0 dB crossover point is aimed at a thirteenth of the switching frequency
(fSW). This factor is chosen as a compromise between good bandwidth and minimizing the phase lag introduced by the second
power pole, which occurs between 1/3 and 1/6 of the switching
frequency. In theory, this should introduce a phase margin of
90°, however, in practice it will be slightly less, due to the effects
of the second power pole. The introduction of this second pole
reduces the phase margin below 90°.
It is recommended that the error amplifier high frequency pole
should be positioned one octave below the switching frequency.
This provides some attenuation of the switching ripple whilst
having minimum impact on the closed loop response.
To achieve a –20 dB/decade roll off, the error amplifier zero is
positioned to coincide with the power pole at maximum load.
The low frequency pole occurs at:
fp1(EA) =
The zero occurs at:
(17)
Figure 6 illustrates the power stage gain, the error amplifier gain,
and then the combined overall loop response (power stage and
error amplifier).
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Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Design Example
Assuming: output voltage (VOUT) = 1.2 V, maximum load (IOUT)
= 6 A, switching frequency (fSW ) = 500 kHz, and output capacitance (COUT) = 200 μF. Analyze the response at full load.
= 20 Log10
1. Crossover frequency:
500 ×103
fcross =
= 38.5 kHz
13
2. Overall DC gain (refer to figure 6):
VOUT
DC gain (PS) = 20 Log10
Vc
DC gain (EA) = 60 dB+ 20 Log10
VFB
VOUT
+ 60 dB+ 20 Log10
Vc
VOUT
1.2
1.5
= 20 Log10
(20)
+ 60 dB + 20 Log10
0.6
1.2
= 52 dB
(21)
VFB
(23)
DC gain (All) = DC gain (PS) + DC gain (EA)
(22)
VOUT
Note: With a power stage gain of 4 A / V and a load of 6 A, the
corresponding Vc = 6 / 4 = 1.5 V.
3. With a 38.5 kHz crossover and a 20 dB /decade increase
in gain, at what frequency does the gain reach 52 dB? The
–20 dB / decade roll off can be described as a single pole with this
transfer function for magnitude (G):
1
(24)
G=
2 × × f × RC
Gain
(dB)
DC gain (PS)
Power Stage
Frequency
fp(PS)
Gain
(dB)
DC gain (EA)
Error Amplifier
fp1(EA)
fp2(EA) Frequency
fz(EA)
Gain
(dB)
–2
Overall Loop
0d
B
DC gain (All)
/d
ec
ad
e
f cross
Frequency
Figure 6. Power stage, error amplifier, and combined overall control loop response
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Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
3a. We know that at 38.5 kHz the gain is 0 dB (1). Therefore the
constant RC can be worked out:
1
(25)
RC =
2 × × 38.5 ×103 × 1
= 4.13 ×10 – 6
3b. A magnitude of 52 dB requires a gain of 398. The error amplifier pole (fp1(EA) ), the frequency at which 398 is reached, is:
1
fp1(EA) =
(26)
2 × × 4.13 ×10 – 6 × 398
= 96.8 Hz
So the overall loop response objective is shown in figure 7.
4a. The error amplifier pole (fp1(EA) ) occurs at 96.8 Hz. Therefore, C11 can be found:
1
C11 =
(27)
2 × × RO × fp1(EA)
1
=
2 × × 1.25 ×10 6 × 96.8
= 1.3 nF
The nearest preferred value is 1.5 nF.
Overall Loop Response, Gain (dB)
4b. The power pole (fp(PS) ) can be found, because the output
capacitor (COUT) and maximum load (RLOAD) are known:
1
2 × × 1.5 ×10 –9 × 3979
= 26.67 kΩ
Nearest preferred value = 27 kΩ.
4d. The error amplifier high frequency pole (fp2(EA) ) is set an
octave below the switching frequency. Therefore, C12 can be
found:
1
(30)
C12 =
2 × × R5 × ( fSW /2)
1
=
3
2 × × 27 ×10 × (500 ×10 3 / 2)
= 24 pF
Nearest preferred value = 22 pF.
4e. Using the above compensation component selection technique, table 4 provides preferred component values for a given
output voltage, 6 A output, at target switching frequencies of
500 kHz, 700 kHz, and 1 MHz.
Table 4. Recommended R5 and C11 Values
fp1(EA)
Switching Frequency, fSW
500 kHz
fp(PS), fz(EA)
–2
0d
B/
de
ca
de
fcross
0.0968
(28)
2 × × RLOAD × COUT
1
=
2 × × 0.2 × 200 ×10 –6
= 3979 Hz
4c. The error amplifier zero (fz(EA) ) also occurs at 3.979 kHz to
cancel the effects of the power pole. Therefore, as C11 is known,
R5 can be found:
1
(29)
R5 =
2 × × C11 × fp(PS)
=
4. Select the RC components.
52
1
fp(PS) =
Frequency (kHz)
38.5
Figure 7. Design example objective: overall control loop response (power
stage and error amplifier)
700 kHz
1 MHz
VOUT
(V)
R4
(kΩ)
C7
(nF)
VOUT
(V)
R4
(kΩ)
C7
(nF)
VOUT
(V)
R4
(kΩ)
C7
(nF)
5.0
110
1.5
5.0
162
1.0
5.0
240
0.68
3.3
75
1.5
3.3
110
1.0
3.3
160
0.68
2.5
56
1.5
2.5
82
1.0
2.5
120
0.68
1.8
39
1.5
1.8
62
1.0
1.8
91
0.68
1.5
33
1.5
1.5
51
1.0
1.5
75
0.68
1.2
27
1.5
1.2
39
1.0
1.2
59
0.68
1.0
22
1.5
1.0
33
1.0
1.0
51
0.68
0.8
18
1.5
0.8
27
1.0
0.8
39
0.68
0.6
13
1.5
0.6
20
1.0
0.6
20
0.68
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Thermal Considerations
For a given set of conditions, the junction temperature of the
A8672 can be estimated by carrying out a few calculations. This
is important to ensure an adequate safety margin with respect to
the maximum junction temperature (150°C) to enhance reliability. This exercise also helps to understand the overall efficiency
of the regulator.
The general approach is to work out what thermal impedance
(RθJ-A) is required to maintain the junction temperature at a given
level, for a particular power dissipation. It should be noted that
this process is usually iterative to achieve the optimum solution.
The following steps can be used as a guideline for determining a
suitable thermal solution. First, estimate the maximum ambient
temperature (TA ) of the application. Second, define the maximum
junction temperature (TJ ). Note that the absolute maximum is
150°C. Third, determine the worst case power dissipation. This
will typically occur at maximum load and minimum VIN.
Design Example
Assuming: input voltage (VIN ) = 12 V, output voltage (VOUT) =
1.2 V, maximum load (IOUT) = 6 A, switching frequency (fSW )
= 500 kHz, target junction temperature (TJ) ≤ 125ºC, maximum
ambient temperature (TA ) = 85°C, and inductive resistance
(DCRL) = 6.7 mΩ.
1. The main power loss contributors are calculated separately:
= 8 × 10 –3
=
1+
TJ – 25
(32)
200
125 – 25
200
0.012 Ω
where RDS(on)LS(25C) is the RDS(on)LS value that can be found from
the Electrical Characteristics table in this datasheet.
c. Estimate the duty cycle (D) by applying equation 3 (ton ):
D = ton × fSW
VOUT + (RDS(on)LS + DCRL ) IOUT
=
VIN + (RDS(on)LS – RDS(on)HS ) IOUT
=
1.2 + (0.012 + 0.0067 ) 6
12 + (0.012 – 0.03 ) 6
(33)
1
fSW
1
500 103
fSW
500 103
= 0.11
d. The high side static loss can be determined:
PstaticHI = I 2OUT × D × RDS(on)HS(TJ)
(34)
= 62 × 0.11 × 0.03
= 0.119 W
e. The low side static loss can be determined:
• Switch static losses
a. Estimate the RDS(on) of the high-side switch at the maximum
target junction temperature:
RDS(on)HS(TJ) = RDS(on)HS(25C) 1 +
= 20 × 10 –3
RDS(on)LS(TJ) = RDS(on)LS(25C) 1 +
1+
TJ – 25
200
PstaticLO = I 2OUT × 1 – D × RDS(on)LS(TJ)
= × (1 – 0.11) × 0.012
= 0.385 W
(31)
125 – 25
200
= 0.03 Ω
where RDS(on)HS(25C) is the RDS(on)HS value that can be found
from the Electrical Characteristics table in this datasheet.
b. Estimate the RDS(on) of the low side switch at the given junction temperature:
(35)
62
• Switching losses The combined turn on and turn off losses for
both switches are calculated as:
VIN
× I OUT × 6 ×10 –9 × fSW × 2
2
12
=
× 6 × 6 ×10 –9 × 500 ×103 × 2
2
= 0.216 W
Pswitch =
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(36)
19
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
• Recirculation diode losses The recirculation diode losses
(low-side switch) are calculated as:
Precirc = 0.8 × I OUT × 6 ×10 –9 × fSW
(37)
= 0.8 × 6 × 6 ×10 –9 × 500 ×103
= 0.014 W
• Diode transit losses The recirculation diode losses (low-side
switch) are calculated as:
Ptransit = VIN × I OUT × 3 ×10 –9 × fSW
(38)
= 12 × 6 × 3 ×10 –9 × 500 ×103
= 0.108 W
• BIAS losses The supply bias losses are calculated as:
(39)
Pbias = VIN × 20 × 10 –3
= 0.24 W
2. The total losses in the A8672 can be estimated:
Ptotal = PstaticHI + PstaticLO + Pswitch + Precirc + Ptransit + Pbias (40)
= 0.119 + 0.385 + 0.216 + 0.014 + 0.108 + 0.24
= 1.082 W
3. The thermal impedance required for the solution can be found:
T – TA
RθJA = J
(41)
Ptotal
125 – 85
= 1.082
= 37 °C/W
For this particular solution, a high thermal efficiency board is
required to ensure the junction temperature is kept below 125°C.
It is recommended to use a PCB with at least four layers. The
A8672 should be mounted onto a thermal pad. A number of vias
should connect the thermal pad to at least one of the internal layers and the bottom side of the PCB. Both of these layers should
be a ground plane. See the Layout section for more information.
Regulator Efficiency
The overall regulator efficiency can be determined by including
the inductor loss. In the above thermal characteristics example,
the inductor resistance, DCRL = 6.7 mΩ. Therefore the inductor
power loss can be found::
PL = DCRL × I 2OUT
(42)
= 0.0067 × 62
= 0.241 W
The overall regulator efficiency can be found:
η =
VOUT × IOUT
(VOUT × IOUT ) + Ptotal+ PL
1.2 × 6
= (1.2 × 6) + 1.082 + 0.241
(43)
= 84.5 %
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Layout
Although the power dissipation in the A8672 is very low, it is recommended that the thermal pad of the device should be soldered
to an appropriate pad on the printed circuit board (PCB) to help
minimize the junction temperature and enhance the efficiency.
The PCB pad should in turn be connected to multiple ground
planes by several thermal vias. As a suggestion, the following
could be used: twenty vias, arranged in 5 rows of 4, with diameter 0.25 mm and spaced (pitch) 0.6 mm apart. The PCB pad not
only acts as a thermal connection, but also forms the star connection for the grounding system.
The ground return connection for the feedback resistor should be
Kelvin-connected directly back to the star ground. Note: To avoid
voltage offset errors in the output voltage, the feedback resistor
should not be connected to the filter capacitor or load grounds
returns.
Figure 8 illustrates the key objectives in the grounding system.
The filtering capacitors (C1 through C4, and C6 through C9)
should be connected as close as possible to the respective pins.
The ground connections for each of the capacitors should be
returned directly to the star connection (PCB pad). Again, these
connections should be as short as possible. Both the PGND and
AGND connections should connect directly to the PCB pad to
form the star connection.
Due to the high impedance nature of the COMP node, it is
important to ensure the compensation components are connected
as close as possible. The feedback trace from R6 and R7 to the
FB pin is also a high impedance input and should be as short as
possible and be placed well away from noisy connections such
as LX. It is recommended to keep any ground planes well away
from the LX node to avoid any potential noise coupling effects.
The support components (C10, C11, and C12), which are ground
referenced, should be connected together locally and then
returned directly to the star connection. Again, this ground should
not pick-up any of the filter capacitors or load ground returns.
A8672 Support
Components
SS
VIN
A8672
L1
VREG
R5 COMP
LX
BIAS
C10
C11
C12
C1
C2
C3
C4
PGND
C8
C9
AGND
C6
R6
C7
Thermal Pad
R7
Local ‘quiet’
Ground Trace
PCB
Pad
Ground Planes (internal planes and bottom surface of PCB)
Thermal Vias
Figure 8. Layout considerations for mounting the A8672
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
A8672
Package EG, 28-Contact QFN
0.30
4.00 BSC
0.20 MIN
28
1
2
0.50
28
1
2
A
5.00 BSC
3.65
5.00
0.90
1
28X
D
SEATING
PLANE
0.08 C
0.30 ±0.05
0.75 ±0.05
0.50 BSC
2.65
C
4.00
C
PCB Layout Reference View
Concept Drawing For Reference Only; not for tooling use
(reference JEDEC MO-220WGHD-3 except for contact length)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.40±0.10
3.65
B
2
1
28
2.65
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 QFN50P400X500X080-29M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
A8672
Fixed Frequency High Current Synchronous Buck Regulator
With Fault Warnings and Power OK
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23