TPS56121 SLUSAH4 – MARCH 2011 www.ti.com 4.5-V to 14-V Input High-Current Synchronous Buck Converter Check for Samples: TPS56121 FEATURES 1 • • • • 2 • • • • • • • DESCRIPTION 4.5-V to 14-V Input Voltage Range Incorporates Power Block Technology Up to 15-A Output Current Fixed Frequency Options of 300 kHz, 500 kHz and 1 MHz High-Side and Low-Side MOSFET RDS(on) Sensing Programmable Soft-Start 600-mV Reference Voltage with 1% Accuracy Voltage Mode Control with Feed-Forward Supports Pre-Biased Output Thermal Shutdown 22-Pin 5 mm x 6 mm PQFN PowerPAD™ Package TPS56121 is a high-efficiency and high-current synchronous buck converter designed to operate from a supply between 4.5 V and 14 V. The device is capable of producing an output voltage as low as 0.6 V at loads up to 15 A. Integrated NexFET™ Power MOSFETs provide a small foot print and ease of use. The device implements a voltage-mode control with voltage feed-forward compensation that responds instantly to input voltage change. TPS56121 is available in a thermally enhanced 22-pin PQFN (DQP) PowerPAD™ package. The device offers design flexibility with a variety of user programmable functions, including soft-start, overcurrent protection (OCP) levels, and loop compensation. OCP levels are programmed by a single external resistor connected from the ILIM pin to the circuit ground. During the initial power-on sequence, the device enters a calibration cycle, measures the voltage at the ILIM pin, and sets an internal OCP voltage level. During operation, the programmed OCP voltage level is compared to the voltage drop across the low-side FET when it is on to determine whether there is an overcurrent condition. It then enters a shutdown/restart cycle until the fault is removed. APPLICATIONS • • Point-of-Load (POL) Power Modules High Density DC-DC Converters for Telecom and Networking Applications SIMPLIFIED APPLICATION TPS56121 VOUT FB VIN COMP PGD VIN BOOT SW EN/SS VDD VIN VOUT ILIM BP GND SD UDG-11047 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, NexFET are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS56121 SLUSAH4 – MARCH 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE TA -40°C to 150°C Plastic QFN (DQP) PINS TRANSPORT MEDIA 22 Tape-and-reel MINIMUM QUANTITY ORDERABLE NUMBER 250 TPS56121DQPT 2500 TPS56121DQPR ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Electrostatic discharge Temperature (1) TYP –0.3 16.5 SW –3 25 SW (< 100 ns pulse width, 10 µJ) -5 VDD, VIN Voltage Range MIN BOOT –0.3 30 BOOT-SW (differential from BOOT to SW) –0.3 7 COMP, PGOOD, FB, BP, EN/SS, ILIM –0.3 7 (HBM) QSS 009-105 (JESD22-A114A) UNIT 2 (CBM) QSS 009-147 (JESD22-C101B.01) V kV 1.5 Junction, TJ –40 150 Storage, Tstg –55 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those included under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability. THERMAL INFORMATION TPS56121 THERMAL METRIC (1) PQFN UNITS 22 PINS θJA Junction-to-ambient thermal resistance 34.6 θJCtop Junction-to-case (top) thermal resistance 22.9 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 5.0 θJCbot Junction-to-case (bottom) thermal resistance 0.3 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VDD VIN Input voltage 4.5 14 V TJ Operating junction temperature –40 125 °C 2 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX TJ = 25°C, 4.5 V ≤ VVDD ≤ 14 V 597 600 603 –40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VVDD ≤ 14 V 594 600 606 UNITS VOLTAGE REFERENCE VFB FB input voltage mV INPUT SUPPLY VVDD Input supply voltage range 14 V IVDDSD Shutdown supply current VEN/SS = 0.2 V 4.5 80 120 µA IVDDQ Quiescent, non-switching Let EN/SS float, VFB = 1 V 2.5 5.0 mA VUVLO UVLO ON Voltage 4.0 4.3 V VUVLO(HYS) UVLO hysteresis 500 700 mV V ENABLE/SOFT-START VIH High-level input voltage, EN/SS 0.55 0.70 1.00 VIL Low-level input voltage, EN/SS 0.27 0.30 0.33 V ISS Soft-start source current 8 10 12 µA VSS Soft-start voltage level – Start of ramp 0.4 0.8 1.3 V 6.2 6.5 6.8 V 70 125 mV 300 330 kHz BP REGULATOR VBP Output voltage IBP = 10 mA VDO Regulator dropout voltage, VVDD – VBP IBP = 25 mA, VVDD = 4.5 V OSCILLATOR fSW Switching Frequency VRAMP (1) RCOMP = 40.2 kΩ, 4.5 V ≤ VVDD ≤ 14 V 270 RCOMP = open, 4.5 V ≤ VVDD ≤ 14 V 450 500 550 kHz RCOMP = 13.3 kΩ, 4.5 V ≤ VVDD ≤ 14 V 0.8 0.95 1.1 MHz VVDD/6.6 VVDD/6 VVDD/5.4 V 100 ns Ramp amplitude PWM DMAX (1) tON(min) (1) Maximum duty cycle fsw = 300 kHz, VFB = 0 V, 4.5 V ≤ VVDD ≤ 14 V 93% fsw = 500 kHz, VFB = 0 V, 4.5 V ≤ VVDD ≤ 14 V 90% fsw = 1 MHz, VFB = 0 V, 4.5 V ≤ VVDD ≤ 14 V 85% Minimum controllable pulse width ERROR AMPLIFIER GBWP AOL (1) (1) Gain bandwidth product 10 Open loop gain 60 24 MHz dB IIB Input bias current (current out of FB pin) VFB = 0.6 V IEAOP Output source current VFB = 0 V 1.5 mA IEAOM Output sink current VFB = 1 V 1.5 mA 75 nA POWER GOOD VOV Feedback upper voltage limit for PGOOD 655 675 700 VUV Feedback lower voltage limit for PGOOD 500 525 550 VPGD-HYST PGOOD hysteresis voltage at FB 30 45 RPGD PGOOD pull down resistance VFB = 0 V, IFB = 5 mA 30 70 Ω PGOOD leakage current 550 mV < VFB < 655 mV, VPGOOD = 5 V 10 20 µA IPGDLK (1) mV Ensured by design. Not production tested 3 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OUTPUT STAGE RHI High-side device resistance TJ = 25°C, (VBOOT – VSW) = 5.5 V 4.5 6.5 RLO Low side device resistance TJ = 25°C 1.9 2.7 mΩ OVERCURRENT PROTECTION (OCP) tPSSC(min) tBLNKH (2) (2) Minimum pulse time during short circuit 250 Switch leading-edge blanking pulse time (high-side detection) 150 IOCH OC threshold for high-side FET TJ = 25°C, (VBOOT – VSW) = 5.5 V IILIM ILIM current source TJ = 25°C VOCLPRO (2) Programmable OC range for low side TJ = 25°C FET tOFF OC retry cycles on EN/SS pin 27 34 ns 39 12 100 4 A µA 10.0 mV Cycle BOOT DIODE VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.8 V 145 ºC 20 ºC THERMAL SHUTDOWN TJSD (2) TJSDH (2) (2) Junction shutdown temperature Hysteresis Ensured by design. Not production tested 4 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com DEVICE INFORMATION DQP PACKAGE PQFN-22 (TOP VIEW) COMP 1 22 PGD FB 2 21 EN/SS GND 3 20 VDD BOOT 4 19 BP GND 5 18 ILIM SW 6 17 VIN SW 7 16 VIN SW 8 15 VIN SW 9 14 VIN SW 10 13 VIN SW 11 12 VIN GND (Thermal Pad) Note: The thermal pad is also an electrical ground connection. PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 4 O Gate drive voltage for the high-side FET. A 100-nF capacitor (typical) must be connected between this pin and the SW pin. To reduce a voltage spike at SW, a BOOT resistance between 5 Ω to 10 Ω may be placed in series with the BOOT capacitor to slow down start-up of the high-side FET. BP 19 O Output bypass for the internal regulator. Connect a low-ESR bypass ceramic capacitor of 1 µF or greater from this pin to GND. COMP 1 O Output of the error amplifier and connection node for loop feedback components. Optionally, a 40.2 kΩ resistor from this pin to GND sets switching frequency to 300KHz instead of the default value of 500KHz; while a 13.3 kΩ resistor from this pin to GND sets switching frequency to 1 MHz. EN/SS 21 I Logic-level input starts or stops the controller via an external user command. Allowing this pin to float turns the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV. The voltage ramp of this pin reaches 1.4 V (typical). FB 2 I Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage. 3 – GND 5 Ground reference for the device – Ground reference for the device. This is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first is to provide an electrical ground connection for the device. The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. 18 I A resistor connected from this pin to GND sets the overcurrent threshold for the device (the low-side FET). 22 O Open drain power good output. I Sense line for the adaptive anti-cross conduction circuitry. Acts as the common connection for the flying high-side FET driver. I Power input to the controller. A low-ESR bypass ceramic capacitor of 1 µF should be connected from this pin close to GND. GND Thermal Pad ILIM PGD 6 7 SW 8 9 10 11 VDD 20 5 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com PIN FUNCTIONS (continued) PIN NAME I/O DESCRIPTION NO. 12 13 14 VIN I 15 Power input to the high-side FET. 16 17 FUNCTIONAL BLOCK DIAGRAM + 10 mA Soft Start 0.6 VREF + 12.5% SS BP SS FB + EN/SS SD 0.6 VREF –12.5% Clock 6-V Regulator VDD BOOT Fault Controller + References OC 0.6 VREF SD BP VIN BP Calibration Circuit COMP Clock Oscillator PWM Logic FB Anti-Cross Conduction and Pre-Bias Circuit SW BP PWM + + 10 mA 0.6 VREF SS Thermal Shutdown 750 kW PGOOD OC Threshold Setting ILIM Fault Controller TPS56121 OC PAD UDG-11050 GND 6 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS 602 306 Switching Frequency (kHz) FB Pin Reference Voltage (mV) fSW = 300 kHz 601 600 599 598 597 596 305 304 303 302 301 595 594 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 VVDD = 4.5 V VVDD = 12 V 300 −40 −25 −10 110 125 Figure 1. Reference Voltage vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 2. Switching Frequency vs. Junction Temperature (300 kHz) 504 975 fSW = 500 kHz fSW = 1 MHz Switching Frequency (kHz) Switching Frequency (kHz) 502 500 498 496 494 492 5 20 35 50 65 80 Junction Temperature (°C) 95 875 850 −40 −25 −10 110 125 725 700 675 650 625 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 5. EN Pin High-Level Threshold Voltage vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 4. Switching Frequency vs. Junction Temperature (1 MHz) EN Pin Low−Level Threshold Voltage (mV) EN Pin High−Level Threshold Voltage (mV) 900 VVDD = 4.5 V VVDD = 12 V Figure 3. Switching Frequency vs. Junction Temperature (500 kHz) 600 −40 −25 −10 925 VVDD = 4.5 V VVDD = 12 V 490 488 −40 −25 −10 950 292.5 292.0 291.5 291.0 290.5 290.0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 6. EN Pin Low-Level Threshold Voltage vs. Junction Temperature 7 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com 2.44 80 2.43 Quiescent Current (mA) Shutdown Current (µA) TYPICAL CHARACTERISTICS (continued) 82 78 76 74 72 2.42 2.41 2.40 2.39 VVDD = 12 V 70 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 VVDD = 12 V 2.38 −40 −25 −10 110 125 10.5 975 10.4 950 10.3 10.2 10.1 10.0 9.9 9.8 9.7 110 125 925 900 875 850 825 800 775 750 9.6 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 725 −40 −25 −10 110 125 Figure 9. Soft-Start Source vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 10. Soft-Start Voltage Level vs. Junction Temperature 2.5 5.5 5.0 4.5 4.0 VVDD = 4.5 V VVDD = 12 V 3.5 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 11. High-Side On Resistance vs. Junction Temperature Low−Side On−Resistance (mΩ) 6.0 High−Side On−Resistance (mΩ) 95 Figure 8. Quiescent Current vs. Junction Temperature Soft−Start Voltage Level (mV) Soft−Start Source Current (µA) Figure 7. Shutdown Current vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (°C) 2.4 2.3 2.2 2.1 2.0 1.9 VVDD = 4.5 V VVDD = 12 V 1.8 1.7 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 12. Low-Side On Resistance vs. Junction Temperature 8 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS The efficiency curve shown in Figure 15 is measured with a 0.5-µH output inductor and a maximum DCR of 0.75 mΩ. The efficiency curve shown in Figure 16 is measured with a 0.3-µH output inductor and a maximum DCR of 0.54 mΩ. The power derating curves shown in Figure 17 and Figure 18 are measured on a 4" × 3.25", 0.062" thick FR4 board with 6 layers and 1 oz. copper. 750 Power−Good Threshold Voltage (mV) High−Side Overcurrent Threshold (A) 40 38 36 34 32 30 28 VVDD = 4.5 V VVDD = 12 V 26 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 600 550 500 VOV VUV 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 13. High-Side Overcurrent Threshold vs. Junction Temperature Figure 14. Power Good Threshold Voltage vs. Junction Temperature 100 100 95 80 70 60 50 fSW = 500 kHz VVIN = 12 V TA = 25°C 0 1 2 3 4 5 VOUT = 0.8 V VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V Efficiency (%) Efficiency (%) 650 450 −40 −25 −10 110 125 90 90 85 80 70 6 7 8 9 10 11 12 13 14 15 Load Current (A) 14 14 12 12 Output Current (A) 16 8 VOUT = 0.8 V VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 6 4 2 0 0 10 20 30 40 50 60 70 80 Ambient Temperature (°C) 0 1 5 6 7 8 9 10 11 12 13 14 15 Load Current (A) 6 VOUT = 0.8 V VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V 2 Figure 17. Output Current vs. Ambient Temperature (VVIN = 12 V) 4 8 VVIN = 12 V 100 110 3 10 4 90 2 VOUT = 0.8 V VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V Figure 16. Efficiency vs. Load Current (VVIN = 5 V) 16 10 fSW = 500 kHz VVIN = 5 V TA = 25°C 75 Figure 15. Efficiency vs. Load Current (VVIN = 12 V) Output Current (A) 700 0 0 20 40 60 80 Ambient Temperature (°C) VVIN = 5 V 100 110 Figure 18. Output Current vs. Ambient Temperature (VVIN = 5 V) 9 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com APPLICATION INFORMATION Introduction The TPS56121 is a 15-A high performance synchronous buck converter with two integrated N-channel NexFET™ power MOSFETs. The device implements a voltage-mode control with voltage feed-forward compensation that responds instantly to input voltage change. Pre-bias capability eliminates concerns about damaging sensitive loads. Voltage Reference The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power supply. 2.0 Input Voltage (V) 1.6 VEN/SS Calibration Time(1.9 ms) 1.3 V 1.2 0.8 0.7 V 0.4 VSS_INT 0 Time (ms) Figure 19. Startup Sequence and Timing Enable Functionality, Startup Sequence and Timing After input power is applied, an internal 40-μA current source begins to charge the soft-start capacitor connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal BP regulator followed by a calibration. Total calibration time is approximately 1.9 ms. See Figure 19. During the calibration, the device performs the following two functions. COMP Pin Impedance Sensing The device samples the impedance at the COMP pin and determines the appropriate operating switching frequency. If there is no resistor connected from the COMP pin to GND, the switching frequency is set to the default value of 500 kHz. If a resistor of 40.2 kΩ ± 10% is connected from the COMP pin to GND, the switching frequency is set to 300 kHz. Alternatively, if a resistor of 13.3 K ± 10% is connected from the COMP pin to GND, the switching frequency is set to 1 MHz. After a 1.1-ms time period, the COMP pin is then brought low for 0.8 ms. This ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the converter when it is allowed to start switching. Overcurrent Protection (OCP) setting The device sources 10 μA (typical) to the resistor connected from the ILIM pin to GND. The voltage developed across that resistor multiplied by a factor of 2 is then sampled and latched off internally as the OCP trip level for the low-side FET until one cycles the input or toggles the EN/SS. The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging 10 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com time once calibration is complete. The discharging current is from an internal current source of 140 μA and it pulls the voltage down to 0.4 V. It then initiates the soft-start by charging up the capacitor using an internal current source of 10 μA. The resulting voltage ramp on this pin is used as a second non-inverting input to the error amplifier after an 800 mV (typical) downward level-shift; therefore, the actual soft-start does not take place until the voltage at this pin reaches 800 mV. If the EN/SS pin is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to ensure that the chip is in shutdown mode. Soft-Start Time The soft-start time of the TPS56121 is user programmable by selecting a single capacitor. The EN/SS pin sources 10 μA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the 10 μA to charge the capacitor through a 600 mV range. There is some initial lag due to calibration and an offset (800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier. The soft-start is accomplished in a closed-loop, meaning that the error amplifier controls the output voltage at all times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start schemes. The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier controls the FB pin to. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800 mV offset voltage plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the converter has reached its final regulation voltage. The capacitance required for a given soft-start ramp time for the output voltage is calculated in Equation 1. æI ö CSS = ç SS ÷ ´ tSS è VFB ø where • • • • CSS is the required capacitance on the EN/SS pin (nF) ISS is the soft-start source current (10 μA) VFB is the feedback reference voltage (0.6 V) tSS is the desired soft-start ramp time (ms) (1) Oscillator The oscillator frequency is internally fixed at 500 KHz if there is no resistor connected from COMP pin to GND. Optionally, a 40.2-kΩ resistor from the COMP pin to GND sets the frequency to 300 KHz. Alternatively, a 13.3-kΩ resistor from COMP pin GND sets the frequency to 1 MHz. Overcurrent Protection (OCP) Programmable OCP level at ILIM is from 6 mV to 50 mV. With a scale factor of 2, the actual OC trip point across the low-side FET is in the range of 12 mV to 100 mV. If the voltage drop across ROCSET reaches 300 mV during calibration (No ROCSET resistor included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing. OCP level for the high-side FET is fixed at 34 A (typical). The high-side OCP provides pulse-by-pulse current limiting. OCP sensing for the low-side FET is a true inductor valley current detection, using sample and hold. Equation 2 can be used to calculate ROCSET. æ æ I öö ROCSET = ç IOUT(max ) - ç P-P ÷ ÷ ´ 95 + 500 2 è øø è where • • • IP-P is the peak-to-peak inductor current (A) IOUT(max) is the trip point for OCP (A) ROC(set) is the resistor used for setting the OCP level (Ω) (2) 11 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com An overcurrent (OC) condition is detected by sensing voltage drop across the low-side FET and across the high-side FET. If the voltage drop across either FET exceeds OC threshold, a count increments one count. If no OC condition is detected on either FET, the fault counter decrements by one counter. If three OC pulses are summed, a fault condition is declared which cycles the soft-start function in a hiccup mode. Hiccup mode is defined as four dummy soft-start timeouts followed by a real one if overcurrent condition is encountered during normal operation; or five dummy soft-start timeouts followed by a real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the fault condition is removed. Input Undervoltage Lockout (UVLO) The TPS56121 has fixed input under-voltage lockout (UVLO). In order for the device to turn on, the following conditions must be met: • the EN/SS pin voltage must be greater than VIH • the input voltage must exceed UVLO on voltage VUVLO The UVLO has a minimum of 500 mV hysteresis built-in. Pre-Bias Startup The TPS56121 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. There are no PWM pulses until the internal soft-start voltage rises above the error amplifier input (FB pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow on time. It then increments the on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage startup and ramp to regulation is smooth and controlled. Power Good The TPS56121 provides an indication that output is good for the converter. This is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include: • VFB is more than ±12.5% from nominal • soft-start is active • a short circuit condition has been detected NOTE When there is no power to the device, PGOOD is not able to pull close to GND if an auxiliary supply is used for the power good indication. In this case, a built in resistor connected from drain to gate on the PGOOD pull down device makes the PGOOD pin look approximately like a diode to GND. Thermal Shutdown If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator are turned off. Both high-side FET and low-side FET are kept off. When the junction cools to the required level (125°C typical), the PWM initiates soft start as during a normal power-up cycle. 12 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com DESIGN EXAMPLE Introduction This design example describes a 15-A, 12-V to 1.2-V design using the TPS56121 high-current integrated buck converter. The system specifications are listed in Table 1. Table 1. TPS56121 Design Example Parameters PARAMETER TEST CONDITIONS MIN TYP 8.0 MAX VIN Input voltage VIN(ripple) Input ripple IOUT = 15 A VOUT Output voltage 0 A ≤ IOUT ≤ 15 A Line regulation 8 V ≤ VIN ≤ 14 V 0.5% 0.5% 1.164 1.2 Load regulation 0 A ≤ IOUT ≤ 15 A VRIPPLE Output ripple IOUT= 15 A VOVER Output overshoot 5 A ≤ IOUT ≤ 10 A 50 VUNDER Output undershoot 5 A ≤ IOUT ≤ 10 A 50 IOUT Output current 8 V ≤ VIN ≤ 14 V tSS Soft-start time VIN = 12 V ISCP Short- circuit current trip point η Efficiency fSW Switching frequency V 0.5 V 1.236 V 24 0 mV mV mV 15 A 1.5 ms 90 % 20 VIN = 12 V, IOUT = 12.5 A UNIT 14 A 500 Size kHz 0.6 In2 + Figure 20. Design Example Schematic 13 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com Design Procedure Switching Frequency Selection To achieve a balance between small size and high efficiency for this design, use switching frequency of 500 kHz. Inductor Selection (L1) Synchronous buck power inductors are typically sized for between approximately 20% and 40% peak-to-peak ripple current (IRIPPLE). Using this target ripple current, the required inductor size can be calculated as shown in Equation 3. VIN(max) - VOUT V 1 14 V - 1.2 V 1.2 V 1 L» ´ OUT ´ = ´ ´ = 487nH 0.3 ´ IOUT VIN(max) fSW 0.3 ´ 15 A 14 V 500kHz (3) Selecting a standard 680-nH inductor value, IRIPPLE =7.3A. The RMS current through the inductor is approximated in Equation 4. 2 IL(rms ) = (I ( ) ) + ( L avg 2 1 ´ I RIPPLE 12 ( ) )= (IOUT )2 + ( 2 1 ´ I RIPPLE 12 ( ) )= (15 )2 + ( 1 ´ 12 (3.2 )2 )= 15.03 A (4) Output Capacitor Selection (C18, C20, C23) The selection of the output capacitor is typically driven by the output transient response. The selection of the output capacitor is typically driven by the output transient response. • loop bandwidth delay • inductor slew-rate delay • transient slew-rate For applications with VIN(min) > 2 × VOUT the calculation is shown in Equation 5. 2 COUT(min ) = ITRAN(max) 3p ´ BW ´ VOVER + (ITRAN(max) ) ´ L 2 ´ (VOUT )´ VOVER - ITRAN(max) ´ tFALL VOVER = 2 (5 ) ´ 680nH 5 A ´ 1ms 5 + = 177 mF + 142 mF - 50 mF = 269 mF 3p ´ 60kHz ´ 50mV 2 ´ 1.2 ´ 50mV 50mV (5) With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is approximated inEquation 6. æ ö IRIPPLE æ ö 3.2 A VRIPPLE(tot) - ç ÷ 24mV - ç ÷ VRIPPLE(tot) - VRIPPLE(cap) 8 ´ COUT ´ fSW ø 8 ´ 269 mF ´ 500kHz ø è è ESRMAX = = = = 6.5mW IRIPPLE IRIPPLE 3.2 A (6) In order to meet the low ESR and high capacitance requirements of this design, 5 47-µF, 1210, 2 22-µF, 1206, and 1 10-µF, 0805 ceramic capacitors are selected. The combination of multiple capacitor types and ceramic capacitors of different sizes provides a wider band to the filtering frequencies of the output capacitors. 14 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com Inductor Peak Current Rating With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated by Equation 7. ´ COUT 1.2 V ´ 275 mF V = = 0.22 A ICHARGE = OUT tSS 1.5ms (7) IL(peak ) = IOUT(max) + (12 ´ IRIPPLE )+ ICHARGE = 15 A + (12 ´ 3.2A )+ 0.22 A = 16.8 A (8) Table 2. Inductor Requirements Summary PARAMETER VALUE UNITS 680 nH RMS current (thermal rating) 15.03 A Peak current (saturation rating) 16.8 A L Inductance IL(rms) IL(peak) PG0871.681NL, 680-nH, 2.3-mΩ, 24-A inductor is selected with a 24-A saturation current and 19-ARMS thermal rating. A physically larger inductor with a lower DCR could be selected for higher efficiency, but this small inductor better meets the 0.6 maximum PCB area requirement. Bootstrap Capacitor (C14) The bootstrap capacitor maintains power to the high-side driver during the high-side switch ON time. Per the requirements of the integrated MOSFET, the value of CBOOT is 100 nF with a minimum 10-V rating. Bootstrap Resistor (R2) The bootstrap resistor slows the rising edge of the SW voltage to reduce ringing and improve EMI. Per the datasheet recommendation a 5.1-Ω resistor is selected. VDD Bypass Capacitor (C11) Per the TPS56221 recommended pin terminations, VDD is bypassed to GND with a 1.0-µF capacitor. BP5 Bypass Capacitor (C12) Per the TPS56221 recommended pin terminations, VDD is bypassed to GND with at least 1.0-µF capacitor. For additional filtering and noise immunity, a 4.7-µF capacitor is selected. Soft-Start Capacitor (C13) The soft-start capacitor provides a constant ramp voltage to the error amplifier to provide controlled, smooth start-up. The soft-start capacitor is sized using Equation 9. I 10 mA ´ 1.5ms = 25nF » 22nF CSS = SS ´ tSS = VFB 0.6 V (9) Current Limit (R1) The TPS56221 uses the negative drop across the internal low-side FET at the end of the OFF-time to measure the valley of the inductor current. Allowing for a minimum of 30% over maximum load, the programming resistor is selected using Equation 10. æ æ æI öö æ 3.2 A ö ö ROCSET = 95 ´ ç 1.3 ´ IOUT(max) - ç RIPPLE ÷ ÷ + 500 W = 95 ´ ç 1.3 ´ 15 A - ç ÷ ÷ + 500 W = 2.20 kW » 2.87 kW 2 øø è 2 øø è è è (10) 15 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com Feedback Divider (R4, R7) The TPS56121 converter uses a full operational amplifier with an internally fixed 0.600-V reference. R4 is selected between 10 kΩand 50 kΩ for a balance of feedback current and noise immunity. With R4 set to 20.5 kΩ, The output voltage is programmed with a resistor divider given by Equation 11. VFB ´ RFB 0.600 V ´ 20.5kW RBIAS = = = 20.5kW » 20.5kW (VOUT - VFB ) 1.2 V - 0.600 V (11) Compensation (C15, C16, C17, R3, R6) Using the TPS40k Loop Stability Tool for 60 kHz of bandwidth and 60 degrees of phase margin with an R4 value of 20.5 kΩ, the following values are obtained. • C17 = C_1 = 470 pF • C15 = C_2 = 1000 pF • C16 = C_3 = 22 pF • R6 = R_2 = 1.27 kΩ • R3 = R_3 = 22.1 kΩ XXX DESIGN EXAMPLE PERFORMANCE CHARACTERISTICS Output voltage 12 V to 1.2V at 0-A to 15-A input current. 94 225 90 80 180 Gain (dB) 88 60 135 86 40 90 84 20 45 82 0 0 80 −20 78 −40 VIN = 8 V VIN = 12 V VIN = 14 V 76 74 0 3 6 9 Load Current (A) 12 Figure 21. Efficiency vs Load Current −60 0.1 15 Phase (°) 92 Efficiency (%) 100 fSW = 500 kHz −45 −90 Gain Phase 1 10 Frequency (kHz) 100 −135 1000 Figure 22. Loop Response 60 kHz Bandwidth, 54° Phase Margin Figure 23. Output Ripple 20 mV/div, 1.0 µs/div, 20 MHz Bandwidth, AC Coupled 16 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 TPS56121 SLUSAH4 – MARCH 2011 www.ti.com Table 3. List of Materials for TPS56221 Design Example REFERENCE DESiGNATOR QTY VALUE DESCRIPTION SIZE PART NUMBER MANUFACTURER C1 3 22 µF Capacitor, Ceramic, 25V, X5R, 20% 1210 Std Std C4 1 100 µF Capacitor, Aluminum, 16VDC, ±20% D8 EEEFP1C101AP Panasonic C5 1 1.0 µF Capacitor, Ceramic, 25V, X7R, 20% 0805 Std Std C6 1 3.3 µF Capacitor, Ceramic, 25V, X7R, 20% 0805 Std Std C7 4 10 µF Capacitor, Ceramic, 25V, X7R, 20% 1206 Std Std C11 1 1.0 µF Capacitor, Ceramic, 25V, X5R, 20% 0805 Std Std C12 1 4.7 µF Capacitor, Ceramic, 10V, X5R, 20% 0805 Std Std C13 1 22 µF Capacitor, Ceramic, 16V, X7R, 20% 0402 Std Std C14 1 100 µF Capacitor, Ceramic, 16V, X7R, 20% 0402 Std Std C15 1 1000 pF Capacitor, Ceramic, 25V, X7R, 10% 0402 Std Std C16 1 22 pF Capacitor, Ceramic, 25V, C0G, 10% 0402 Std Std C17 1 470 pF Capacitor, Ceramic, 25V, C0G, 10% 0402 Std Std C18 2 22 µF Capacitor, Ceramic, 6.3V, X5R, 20% 1206 Std Std C20 1 10 µF Capacitor, Ceramic, 6.3V, X5R, 20% 0805 Std Std C21 5 47 µF Capacitor, Ceramic, 6.3V, X5R, 20% 1210 Std Vishay L1 1 320 nH IND, SMT Power ±15% 7.6 x 7.4 mm PG0871.681NL Pulse R1 1 2.87 kΩ Resistor, Chip, 1/16W, 1% 0402 Std Std R2 1 5.1 Ω Resistor, Chip, 1/16W, 1% 0402 Std Std R3 1 22.1 kΩ Resistor, Chip, 1/16W, 1% 0402 Std Std R4 1 20.5 kΩ Resistor, Chip, 1/16W, 1% 0402 Std Std R6 1 1.27 kΩ Resistor, Chip, 1/16W, 1% 0402 Std Std R7 1 20.5 kΩ Resistor, Chip, 1/16W, 1% 0402 Std Std 1 TPS56121 DQP 15 A, 600 kHz, synchronous buck converter QFN-22 6 × 5 mm TPS56121DQP U1 TI 17 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS56121 PACKAGE OPTION ADDENDUM www.ti.com 28-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS56121DQPR ACTIVE SON DQP 22 2500 Pb-Free (RoHS Exempt) CU SN Level-2-260C-1 YEAR TPS56121DQPT ACTIVE SON DQP 22 250 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS56121DQPR Package Package Pins Type Drawing SON DQP 22 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 6.3 1.8 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS56121DQPR SON DQP 22 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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