CAT140xx Voltage Supervisor with I2C Serial CMOS EEPROM Description The CAT140xx (see table below) are memory and supervisory solutions for microcontroller based systems. A CMOS serial EEPROM memory and a system power supervisor with brown−out protection are integrated together. Memory interface is via both the standard (100 kHz) as well as fast (400 kHz) I2C protocol. The CAT140xx provides a precision VCC sense circuit with two reset output options: CMOS active low output or CMOS active high. The RESET output is active whenever VCC is below the reset threshold or falls below the reset threshold voltage. The power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. Seven reset threshold voltages support 5 V, 3.3 V, 3 V and 2.5 V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 240 ms after the supply voltage exceeds the reset threshold level. Features http://onsemi.com SOIC−8 CASE 751BD PIN CONFIGURATION CAT 14016 / 08 / 04 / 02 NC / NC / NC / A0 1 8 VCC NC / NC / A1 / A1 2 7 RST/RST NC / A2 / A2 / A2 3 6 SCL VSS 4 5 SDA • Precision Power Supply Voltage Monitor 5 V, 3.3 V, 3 V and 2.5 V Systems 7 Threshold Voltage Options Active High or Low Reset ♦ Valid Reset Guaranteed at VCC = 1 V Supports Standard and Fast I2C Protocol 16−Byte Page Write Buffer Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial Temperature Range RoHS−Compliant 8−Pin SOIC Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ♦ • • • • • • • • • PIN FUNCTION ♦ Pin Name A0, A1, A2 Serial Data Input/Output SCL Serial Clock Input RST/RST Reset Output VCC Power Supply VSS Ground NC No Connect 14002 L 4.38 V M Device Address Inputs SDA Product Threshold Suffix Designation 4.63 V Function MEMORY SIZE SELECTOR THRESHOLD SUFFIX SELECTOR Nominal Threshold Voltage SOIC (W) Memory Density 2−Kbit 14004 4−Kbit 14008 8−Kbit 14016 16−Kbit 4.00 V J ORDERING INFORMATION 3.08 V T For Ordering Information details, see page 10. 2.93 V S 2.63 V R 2.32 V Z © Semiconductor Components Industries, LLC, 2011 November, 2011 − Rev. 3 1 Publication Order Number: CAT14002/D CAT140xx BLOCK DIAGRAM VCC SDA SCL VOLTAGE DETECTOR EEPROM A0 RST or RST A1 A2 VSS SPECIFICATIONS Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature –65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol NEND (Note 3) TDR Parameter Endurance Data Retention Min Units 1,000,000 Program/ Erase Cycles 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS VCC = +2.5 V to +5.5 V, unless otherwise specified. Symbol Parameter Test Conditions ICC Supply Current Read or Write at 400 kHz ISB Standby Current VCC < 5.5 V; All I/O Pins at VSS or VCC VCC < 3.6 V; All I/O Pins at VSS or VCC IL I/O Pin Leakage VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage SDA Min Pin at GND or VCC VCC ≥ 2.5 V, IOL = 3.0 mA http://onsemi.com 2 Typ Max Units 1 mA 10 22 mA 8 17 2 mA −0.5 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V 0.4 V CAT140xx Table 4. A.C. CHARACTERISTICS (MEMORY) (Note 1) VCC = 2.5 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified. Standard FSCL tHD:STA Clock Frequency Low Period of SCL Clock tHIGH High Period of SCL Clock Max Min 100 START Condition Hold Time tLOW Max Units 400 kHz 4 0.6 ms 4.7 1.3 ms 4 0.6 ms 4.7 0.6 ms Data in Hold Time 0 0 ms Data in Setup Time 250 100 ns tSU:STA START Condition Setup Time tHD:DAT tSU:DAT tR (Note 2) SDA and SCL Rise Time 1000 300 ns tF (Note 2) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time TI (Note 2) tWR tPU (Notes 2 & 3) 1. 2. 3. Min Parameter Symbol Fast 4 0.6 4.7 1.3 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs ms 0.9 100 ms ns 100 100 ns Write Cycle Time 5 5 ms Power−up to Ready Mode 1 1 ms Test conditions according to “A.C. Test Conditions” table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 5. A.C. TEST CONDITIONS Parameter Input Levels Test Conditions 0.2 x VCC to 0.8 x VCC Input Rise and Fall Times Input Reference Levels ≤50 ns 0.3 x VCC , 0.7 x VCC Output Reference Levels Output Load ms 0.5 x VCC Current Source: IOL = 3 mA; CL = 100 pF http://onsemi.com 3 CAT140xx Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION) VCC = Full range, TA = −40°C to +85°C unless otherwise noted. Typical values at TA = +25°C and VCC = 5 V for L/M/J versions, VCC = 3.3 V for T/S versions, VCC = 3 V for R version and VCC = 2.5 V for Z version. Symbol Parameter Threshold VTH Reset Threshold Voltage L M J T S R Z Symbol Parameter Conditions Min Typ Max Units TA = +25°C 4.56 4.63 4.70 V TA = −40°C to +85°C 4.50 TA = +25°C 4.31 TA = −40°C to +85°C 4.25 TA = +25°C 3.93 TA = −40°C to +85°C 3.89 TA = +25°C 3.04 TA = −40°C to +85°C 3.00 TA = +25°C 2.89 TA = −40°C to +85°C 2.85 TA = +25°C 2.59 TA = −40°C to +85°C 2.55 TA = +25°C 2.28 TA = −40°C to +85°C 2.25 Conditions Min Reset Threshold Tempco tRPD VCC to Reset Delay (Note 2) VCC = VTH to (VTH −100 mV) tPURST Reset Active Timeout Period TA = −40°C to +85°C VOL RESET Output Voltage Low (Push−pull, Active LOW, CAT140xx9) VOH VOL VOH 140 4.75 4.38 4.45 4.50 4.00 4.06 4.10 3.08 3.11 3.15 2.93 2.96 3.00 2.63 2.66 2.70 2.32 2.35 2.38 Typ (Note 1) Max Units 30 ppm/°C 20 ms 240 460 ms VCC = VTH min, ISINK = 1.2 mA R/S/T/Z 0.3 V VCC = VTH min, ISINK = 3.2 mA J/L/M 0.4 VCC > 1.0 V, ISINK = 50 mA 0.3 RESET Output Voltage High (Push−pull, Active LOW, CAT140xx9) VCC = VTH max, ISOURCE = −500 mA R/S/T/Z 0.8 VCC VCC = VTH max, ISOURCE = −800 mA J/L/M VCC − 1.5 RESET Output Voltage Low (Push−pull, Active HIGH, CAT140xx1) VCC > VTH max, ISINK = 1.2 mA R/S/T/Z 0.3 VCC > VTH max, ISINK = 3.2 mA J/L/M 0.4 RESET Output Voltage High (Push−pull, Active HIGH, CAT140xx1) 1.8 V < VCC ≤ VTH min, ISOURCE = −150 mA 1. Production testing done at TA = +25°C; limits over temperature guaranteed by design only. 2. RESET output for the CAT140xx9; RESET output for the CAT140xx1. http://onsemi.com 4 0.8 VCC V V V CAT140xx PIN DESCRIPTION SCL: SERIAL CLOCK The Serial Clock input pin accepts the Serial Clock generated by the Master. A0, A1, A2: Device Address Inputs The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. RESET/RESET: RESET OUTPUT This output is available in two versions: CMOS Active Low (CAT140xx9) and CMOS Active High (CAT140xx1). Both versions are push−pull outputs for high efficiency. SDA: SERIAL DATA ADDRESS The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. DEVICE OPERATION The CAT140xx products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard EEPROMs from ON Semiconductor. TRANSIENT DURATION [μs] initial voltage of 0.5 V above the threshold and drops below it by the amplitude of the overdrive voltage (VTH − VCC). Reset Controller Description The reset signal is asserted LOW for the CAT140xx9 and HIGH for the CAT140xx1 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140 ms (tPURST) after the power supply voltage has risen above the threshold. Reset output timing is shown in Figure 2. The CAT140xx devices protect mPs against brownout failure. Short duration VCC transients of 4 msec or less and 100 mV amplitude typically do not generate a Reset pulse. Figure 1 shows the maximum pulse duration of negative−going VCC transients that do not cause a reset condition. As the amplitude of the transient goes further below the threshold (increasing VTH − VCC), the maximum pulse duration decreases. In this test, the VCC starts from an TAMB = 25ºC CAT140xxZ CAT140xxM RESET OVERDRIVE VTH - VCC [mV] Figure 1. Maximum Transient Duration without Causing a Reset Pulse vs. Overdrive Voltage VTH VCC VRVALID t PURST t RPD t PURST t RPD RESET CAT140xx9 RESET CAT140xx1 Figure 2. RESET Output Timing http://onsemi.com 5 CAT140xx EMBEDDED EEPROM OPERATION Master device, which generates the serial clock and all START and STOP conditions. The CAT140xx acts as a Slave device. Master and Slave alternate as either transmitter or receiver. The CAT140xx supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a I2C BUS PROTOCOL The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 3). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Write command) or sends the Slave into standby mode (when following a Read command). Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. For normal Read/Write operations, the first 4 bits of the Slave address are fixed at 1010 (Ah). The next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. The last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The 3 address space extension bits are assigned as illustrated in Figure 4. A2, A1 and A0 must match the state of the external address pins, and a10, a9 and a8 are internal address bits. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 5). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 6. START The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. STOP The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a SCL SDA STOP CONDITION START CONDITION Figure 3. START/STOP Conditions http://onsemi.com 6 CAT140xx 1 0 1 0 A2 A1 A0 R/W CAT14002 1 0 1 0 A2 A1 a8 R/W CAT14004 1 0 1 0 A2 a9 a8 R/W CAT14008 1 0 1 0 a10 a9 a8 R/W CAT14016 Figure 4. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER) SCL FROM MASTER 1 8 9 DATA OUTPUT FROMTRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 5. Acknowledge Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 6. Bus Timing WRITE OPERATIONS Byte Write (Figure 7). While this internal cycle is in progress (tWR), the SDA output will be tristated and the CAT140xx will not respond to any request from the Master device (Figure 8). In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT140xx. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAT140xx device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory Page Write The CAT140xx writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 9). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been http://onsemi.com 7 CAT140xx Acknowledge Polling transmitted the CAT140xx will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’ to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the CAT140xx in a single write cycle. S T A R T BUS ACTIVITY: MASTER The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT140xx initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT140xx is still busy with the write operation, NoACK will be returned. If the CAT140xx has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7⎟ a0 d7÷d0 S T O P S P A C K SLAVE A C K A C K Figure 7. Byte Write Sequence SCL 8th Bit SDA ACK Byte n tWR STOP CONDITION START CONDITION ADDRESS Figure 8. Write Cycle Timing BUS ACTIVITY: MASTER S T A R T DATA BYTE n ADDRESS BYTE SLAVE ADDRESS DATA BYTE n+1 DATA BYTE n+P S T O P S SLAVE P A C K A C K A C K n=1 P ≤ 15 Figure 9. Page Write Timing http://onsemi.com 8 A C K A C K CAT140xx READ OPERATIONS Immediate Read address of the location it wishes to read. After the CAT140xx acknowledges the byte address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT140xx then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 11). Upon receiving a Slave address with the R/W bit set to ‘1’, the CAT140xx will interpret this as a request for data residing at the current byte address in memory. The CAT140xx will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the CAT140xx returns to Standby mode. Sequential Read If during a Read session, the Master acknowledges the 1st data byte, then the CAT140xx will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). Selective Read Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte POWER−ON RESET (POR) Each CAT140xx incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A CAT140xx device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR BUS ACTIVITY: MASTER trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. Delivery State The CAT140xx is shipped erased, i.e., all bytes are FFh. N O S T A R T S AT CO KP SLAVE ADDRESS P S A C K SLAVE SCL DATA BYTE 9 8 SDA8 th Bit DATA OUT NO ACK Figure 10. Immediate Read Sequence and Timing http://onsemi.com 9 STOP CAT140xx BUS ACTIVITY: MASTER S T A R T S T A R T ADDRESS BYTE SLAVE ADDRESS N O S AT CO KP SLAVE ADDRESS S S A C K SLAVE P A C K A C K DATA BYTE Figure 11. Selective Read Sequence BUS ACTIVITY: MASTER N O A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 DATA BYTE n+x Figure 12. Sequential Read Sequence ORDERING INFORMATION Orderable Part Numbers − CAT140xx Series (See Notes 1 − 4) Device Reset Threshold Voltage CAT140021LWI−GT3 4.50 to 4.75 V CAT140021SWI−GT3 2.85 to 3.00 V CAT140021TWI−GT3 3.00 to 3.15 V CAT140021LWI−G 4.50 to 4.75 V CAT140021SWI−G 2.85 to 3.00 V CAT140021TWI−G 3.00 to 3.15 V CAT140029LWI−GT3 4.50 to 4.75 V CAT140029SWI−GT3 2.85 to 3.00 V CAT140029TWI−GT3 3.00 to 3.15 V CAT140029LWI−G 4.50 to 4.75 V CAT140029SWI−G 2.85 to 3.00 V CAT140029TWI−G 3.00 to 3.15 V Package−Pins Shipping 3000 Tape & Reel 100 Tube SOIC−8 3000 Tape & Reel 100 Tube 1. All packages are RoHS−compliant (Lead−free, Halogen−free). 2. The standard lead finish is NiPdAu pre−plated (PPF) lead frames. 3. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 4. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com http://onsemi.com 10 CAT140xx PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CAT14002/D