FM24V05 512-Kbit (64 K × 8) Serial (I2C) F-RAM 512-Kbit (64 K × 8) Serial (I2C) F-RAM Features Functional Description ■ 512-Kbit ferroelectric random access memory (F-RAM) logically organized as 64 K × 8 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (See the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Advanced high-reliability ferroelectric process The FM24V05 is a 512-Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by EEPROM and other nonvolatile memories. ■ Fast 2-wire Serial interface (I2C) ❐ Up to 3.4-MHz frequency 2 ❐ Direct hardware replacement for serial (I C) EEPROM ❐ Supports legacy timings for 100 kHz and 400 kHz ■ Device ID ❐ Manufacturer ID and Product ID ■ Low power consumption ❐ 175 A active current at 100 kHz ❐ 90 A (typ) standby current ❐ 5 A (typ) sleep mode current Unlike EEPROM, the FM24V05 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared with other nonvolatile memories. Also, F-RAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. The FM24V05 is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than EEPROM. ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 8-pin small outline integrated circuit (SOIC) package ■ Restriction of hazardous substances (RoHS) compliant These capabilities make the FM24V05 ideal for nonvolatile memory applications, requiring frequent or rapid writes. Examples range from data logging, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM24V05 provides substantial benefits to users of serial (I2C) EEPROM as a hardware drop-in replacement. The device incorporates a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The device specifications are guaranteed over an industrial temperature range of –40 C to +85 C. For a complete list of related documentation, click here. Logic Block Diagram Counter Address Latch 64 K x 8 F-RAM Array 16 8 Serial to Parallel Converter SDA Data Latch 8 8 SCL Device ID and Manufacturer ID Control Logic WP A2-A0 Errata: STOP condition is optional for sleep mode entry. For more information, see Errata on page 18. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Cypress Semiconductor Corporation Document Number: 001-84462 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 6, 2015 FM24V05 Contents Pinout ................................................................................ 3 Pin Definitions .................................................................. 3 Functional Overview ........................................................ 4 Memory Architecture ........................................................ 4 I2C Interface ...................................................................... 4 STOP Condition (P) ..................................................... 4 START Condition (S) ................................................... 4 Data/Address Transfer ................................................ 5 Acknowledge / No-acknowledge ................................. 5 Slave Device Address ................................................. 6 High Speed Mode (Hs-mode) ...................................... 6 Addressing Overview .................................................. 6 Data Transfer .............................................................. 6 Memory Operation ............................................................ 6 Write Operation ........................................................... 6 Read Operation ........................................................... 7 Sleep Mode ................................................................. 9 Device ID ......................................................................... 10 Maximum Ratings ........................................................... 11 Operating Range ............................................................. 11 DC Electrical Characteristics ........................................ 11 Data Retention and Endurance ..................................... 12 Capacitance .................................................................... 12 Thermal Resistance ........................................................ 12 Document Number: 001-84462 Rev. *H AC Test Loads and Waveforms ..................................... 12 AC Test Conditions ........................................................ 12 AC Switching Characteristics ....................................... 13 Power Cycle Timing ....................................................... 14 Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagram ............................................................ 16 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Errata ............................................................................... 18 Part Numbers Affected .............................................. 18 FM24V05 I2C F-RAM Qualification Status ................ 18 FM24V05 Errata Summary ........................................ 18 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC® Solutions ...................................................... 21 Cypress Developer Community ................................. 21 Technical Support ..................................................... 21 Page 2 of 21 FM24V05 Pinout Figure 1. 8-pin SOIC pinout A0 1 A1 2 A2 3 VSS 4 Top View not to scale 8 VDD 7 WP 6 SCL 5 SDA Pin Definitions Pin Name I/O Type Description A2-A0 Input Device Select Address 2-0. These pins are used to select one of up to 8 devices of the same type on the same I2C bus. To select the device, the address value on the three pins must match the corresponding bits contained in the slave address. The address pins are pulled down internally. SDA Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. SCL Input Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. WP Input Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When WP is connected to ground, all addresses are write enabled. This pin is pulled down internally. VSS Power supply Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device. Document Number: 001-84462 Rev. *H Page 3 of 21 FM24V05 Functional Overview a new bus transaction can be shifted into the device, a write operation is complete. This is explained in more detail in the interface section. The FM24V05 is a serial F-RAM memory. The memory array is logically organized as 65,536 × 8 bits and is accessed using an industry-standard I2C interface. The functional operation of the F-RAM is similar to serial (I2C) EEPROM. The major difference between the FM24V05 and a serial (I2C) EEPROM with the same pinout is the F-RAM's superior write performance, high endurance, and low power consumption. I2C Interface The FM24V05 employs a bi-directional I2C bus protocol using few pins or board space. Figure 2 illustrates a typical system configuration using the FM24V05 in a microcontroller-based system. The industry standard I2C bus is familiar to many users but is described in this section. Memory Architecture By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24V05 is always a slave device. When accessing the FM24V05, the user addresses 64K locations of eight data bits each. These eight data bits are shifted in or out serially. The addresses are accessed using the I2C protocol, which includes a slave address (to distinguish other non-memory devices) and a two-byte address. The complete address of 16 bits specifies each byte address uniquely. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including START, STOP, data bit, or acknowledge. Figure 3 and Figure 4 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications section. The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the I2C bus. Unlike a serial (I2C) EEPROM, it is not necessary to poll the device for a ready condition because writes occur at bus speed. By the time Figure 2. System Configuration using Serial (I2C) nvSRAM V DD RPmin = (VDD - VOLmax) / IOL RPmax = tr / (0.8473 * Cb) SDA Microcontroller SCL V DD V DD A0 A1 A2 SCL A0 SCL A0 SCL SDA A1 SDA A1 SDA WP A2 WP #0 #1 A2 WP #7 STOP Condition (P) START Condition (S) A STOP condition is indicated when the bus master drives SDA from LOW to HIGH while the SCL signal is HIGH. All operations using the FM24V05 should end with a STOP condition. If an operation is in progress when a STOP is asserted, the operation will be aborted. The master must have control of SDA in order to assert a STOP condition. A START condition is indicated when the bus master drives SDA from HIGH to LOW while the SCL signal is HIGH. All commands should be preceded by a START condition. An operation in progress can be aborted by asserting a START condition at any time. Aborting an operation using the START condition will ready the FM24V05 for a new operation. If during operation the power supply drops below the specified VDD minimum, the system should issue a START condition prior to performing another operation. Document Number: 001-84462 Rev. *H Page 4 of 21 FM24V05 Figure 3. START and STOP Conditions full pagewidth SDA SDA SCL SCL S P STOP Condition START Condition Figure 4. Data Transfer on the I2C Bus handbook, full pagewidth P SDA Acknowledgement signal from slave MSB SCL S 1 2 7 9 8 1 Acknowledgement signal from receiver 2 3 4-8 ACK START condition 9 ACK All data transfers (including addresses) take place while the SCL signal is HIGH. Except under the three conditions described above, the SDA signal should not change while SCL is HIGH. Acknowledge / No-acknowledge The acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal LOW to acknowledge receipt of the byte. If the receiver does not drive SDA LOW, the condition is a no-acknowledge and the operation is aborted. S or P STOP or START condition Byte complete Data/Address Transfer S The receiver would fail to acknowledge for two distinct reasons. First is that a byte transfer fails. In this case, the no-acknowledge ceases the current operation so that the device can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not acknowledge to deliberately end an operation. For example, during a read operation, the FM24V05 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24V05 to attempt to drive the bus on the next clock while the master is sending a new command such as STOP. Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth DATA OUTPUT BY MASTER No Acknowledge DATA OUTPUT BY SLAVE Acknowledge SCL FROM MASTER 1 2 8 9 S START Condition Document Number: 001-84462 Rev. *H Clock pulse for acknowledgement Page 5 of 21 FM24V05 Slave Device Address Figure 6. Memory Slave Device Address The first byte that the FM24V05 expects after a START condition is the slave address. As shown in Figure 6, the slave address contains the device type or slave ID, the device select address bits, and a bit that specifies if the transaction is a read or a write. Bits 7-4 are the device type (slave ID) and should be set to 1010b for the FM24V05. These bits allow other function types to reside on the I2C bus within an identical address range. Bits 3-1 are the device select address bits. They must match the corresponding value on the external address pins to select the device. Up to eight FM24V05 devices can reside on the same I2C bus by assigning a different address to each. Bit 0 is the read/write bit (R/W). R/W = ‘1’ indicates a read operation and R/W = ‘0’ indicates a write operation. MSB handbook, halfpage 1 LSB 0 1 A2 0 A1 A0 R/W Device Select Slave ID High Speed Mode (Hs-mode) The FM24V05 supports a 3.4-MHz high speed mode. A master code (00001XXXb) must be issued to place the device into high speed mode. Communication between master and slave will then be enabled for speeds up to 3.4-MHz. A STOP condition will exit Hs-mode. Single- and multiple-byte reads and writes are supported. Figure 7. Data transfer format in Hs-mode handbook, full pagewidth Hs-mode F/S-mode S MASTER CODE 1 S SLAVE ADD. R/W 0 F/S-mode DATA A /1 P n (bytes+ ack.) No Acknowledge Addressing Overview After the FM24V05 (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The complete 16-bit address is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch; either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24V05 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (FFFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After the address bytes have been transmitted, data transfer between the bus master and the FM24V05 can begin. For a read operation the FM24V05 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24V05 will transfer the next sequential byte. If the acknowledge is not sent, the FM24V05 will end the read operation. For a write operation, the FM24V05 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. Document Number: 001-84462 Rev. *H Acknowledge or No Acknowledge Hs-mode continues S SLAVE ADD. Memory Operation The FM24V05 is designed to operate in a manner very similar to other I2C interface memory products. The major differences result from the higher performance write capability of F-RAM technology. These improvements result in some differences between the FM24V05 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address, then a memory address. The bus master indicates a write operation by setting the LSB of the slave address (R/W bit) to a '0'. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from FFFFh to 0000h. Unlike other nonvolatile memory technologies, there is no effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition. Internally, an actual memory write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using START or STOP Page 6 of 21 FM24V05 counter will not increment if writes are attempted to these addresses. Setting WP to a LOW state (VSS) will disable the write protect. WP is pulled down internally. condition prior to the 8th data bit. The FM24V05 uses no page buffering. The memory array can be write-protected using the WP pin. Setting the WP pin to a HIGH condition (VDD) will write-protect all addresses. The FM24V05 will not acknowledge data bytes that are written to protected addresses. In addition, the address Figure 8 and Figure 9 below illustrate a single-byte and multiple-byte write cycles in F/S mode. Figure 10 below illustrate a single-byte write cycles in Hs mode. Figure 8. Single-Byte Write Start By Master Stop Address & Data S Slave Address 0 A Address MSB A Address LSB A Data Byte A P By F-RAM Acknowledge Figure 9. Multi-Byte Write Start Stop Address & Data By Master S Slave Address 0 A Address MSB A Address LSB A Data Byte A Data Byte A P By F-RAM Acknowledge Figure 10. Hs-mode Byte Write Start Start & Enter Hs-mode Hs-mode command By Master S 0 0 0 0 1 X By F-RAM X X 1 S Slave Address 0 A No Acknowledge Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24V05 uses the internal address latch to supply the address. In a selective read, the user performs a procedure to set the address to a specific value. Current Address & Sequential Read As mentioned above the FM24V05 uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. Document Number: 001-84462 Rev. *H Stop & Exit Hs-mode Address & Data Address MSB A Address LSB A Data Byte A P Acknowledge To perform a current address read, the bus master supplies a slave address with the LSB set to a '1'. This indicates that a read operation is requested. After receiving the complete slave address, the FM24V05 will begin shifting out data from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Note Each time the bus master acknowledges a byte, this indicates that the FM24V05 should read out the next sequential byte. Page 7 of 21 FM24V05 2. The bus master issues a no-acknowledge in the 9th clock cycle and a START in the 10th. 3. The bus master issues a STOP in the 9th clock cycle. 4. The bus master issues a START in the 9th clock cycle. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24V05 attempts to read out additional data onto the bus. The four valid methods are: 1. The bus master issues a no-acknowledge in the 9th clock cycle and a STOP in the 10th clock cycle. This is illustrated in the diagrams below. This is preferred. If the internal address reaches FFFFh, it will wrap around to 0000h on the next read cycle. Figure 11 and Figure 12 below show the proper operation for current address reads. Figure 11. Current Address Read Start By Master No Acknowledge Address Stop S Slave Address By F-RAM 1 A Data Byte Acknowledge 1 P Data Figure 12. Sequential Read Start By Master Address No Acknowledge Acknowledge Stop S Slave Address By F-RAM 1 A Data Byte Acknowledge A Data Byte 1 P Data Figure 13. Hs-mode Current Address Read Start By Master S 0 0 0 0 By F-RAM Document Number: 001-84462 Rev. *H 1 X No Acknowledge Start & Enter Hs-mode Address Hs-mode command X X 1 S No Acknowledge Stop & Exit Hs-mode Slave Address 1 A Acknowledge Data Byte 1 P Data Page 8 of 21 FM24V05 Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB (R/W) set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24V05 acknowledges the address, the bus master issues a START condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a '1'. The operation is now a current address read. Figure 14. Selective (Random) Read Start Address By Master Start No Acknowledge Address Stop S Slave Address 0 A Address MSB A Address LSB A S Slave Address 1 A By F-RAM A low power mode called Sleep Mode is implemented on the FM24V05 device. The device will enter this low power state when the Sleep command 86h is clocked-in. Sleep Mode entry can be entered as follows: 1. The master sends a START command. 2. The master sends Reserved Slave ID F8h. 3. The FM24V05 sends an ACK. 4. The master sends the I2C-bus slave address of the slave device it needs to identify. The last bit is a 'Don't care' value (R/W bit). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 5. The FM24V05 sends an ACK. 6. The master sends a Re-START command. 7. The master sends Reserved Slave ID 86h. 1 P Data Acknowledge Sleep Mode Data Byte 8. The FM24V05 sends an ACK. 9. The master sends STOP to ensure the device enters sleep mode. Note Errata: Step 9 - Sending STOP is an optional step for FM24V05. The FM24V05 starts entering the Sleep mode from step 8 and releases the SDA line when in the Sleep mode. The LOW to HIGH transition on the SDA line when I2C clock is HIGH generates an unintended STOP. For more information, see Errata on page 18. Once in sleep mode, the device draws IZZ current, but the device continues to monitor the I2C pins. Once the master sends a Slave Address that the FM24V05 identifies, it will "wakeup" and be ready for normal operation within tREC time. As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. While the device is waking up, it will NACK the master until it is ready. Figure 15. Sleep Mode Entry Start Address By Master S Rsvd Slave ID (F8) By F-RAM Document Number: 001-84462 Rev. *H A Start Slave Address X A S Address Rsvd Slave ID (86) Stop A P Acknowledge Page 9 of 21 FM24V05 Device ID 5. The FM24V05 sends an ACK. 6. The master sends a Re-START command. 7. The master sends Reserved Slave ID F9h. 8. The FM24V05 sends an ACK. 9. The Device ID Read can be done, starting with the 12 manufacturer bits, followed by the 9 device identification bits, and then the 3 die revision bits. 10.The master ends the Device ID read sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. The FM24V05 device incorporates a means of identifying the device by providing three bytes of data, which are manufacturer ID, product ID, and die revision. The Device ID is read-only. It can be accessed as follows: 1. The master sends a START command. 2. The master sends Reserved Slave ID F8h. 3. The FM24V05 sends an ACK. 4. The master sends the I2C-bus slave address of the slave device it needs to identify. The last bit is a 'Don't care' value (R/W bit). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). Note The reading of the Device ID can be stopped anytime by sending a NACK command. Table 1. Device ID Device ID Description 23–12 (12 bits) Device ID (3 bytes) 11–8 (4 bits) 2–0 (3 bits) Product ID Manufacturer ID 004300h 7–3 (5 bits) 000000000100 Density Variation Die Rev 0011 00000 000 Note Product ID bits 0 and 4 are reserved. Figure 16. Read Device ID Start Address By Master Start No Acknowledge Acknowledge Address Stop S Rsvd Slave ID (F8) A Slave Address A S By F-RAM Acknowledge Document Number: 001-84462 Rev. *H Rsvd Slave ID (F9) A Data Byte A Data Byte A Data Byte 1 P Data Page 10 of 21 FM24V05 Maximum Ratings Surface mount lead soldering temperature (10 seconds) ....................................... +260 C Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –55 C to +125 C Electrostatic Discharge Voltage Human Body Model (AEC-Q100-002 Rev. E) .................. 2.5 kV Charged Device Model (AEC-Q100-011 Rev. B) ............. 1.25 kV Maximum accumulated storage time At 125 °C ambient temperature ................................. 1000 h At 85 °C ambient temperature ................................ 10 Years Latch-up current .................................................... > 140 mA Ambient temperature with power applied ................................... –55 °C to +125 °C * Exception: The “VIN < VDD + 1.0 V” restriction does not apply to the SCL and SDA inputs. Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V Operating Range Machine Model (AEC-Q100-003 Rev. E) ............................ 200 V Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V Range Ambient Temperature (TA) VDD DC voltage applied to outputs in High-Z state .................................... –0.5 V to VDD + 0.5 V Industrial –40 C to +85 C 2.0 V to 3.6 V Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VDD + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W DC Electrical Characteristics Over the Operating Range Parameter Description VDD Power supply IDD Average VDD current Test Conditions SCL toggling between VDD – 0.2 V and VSS, other inputs VSS or VDD – 0.2 V. Min Typ [1] Max Unit 2.0 3.3 3.6 V fSCL = 100 kHz – – 175 A fSCL = 1 MHz – – 400 A fSCL = 3.4 MHz – – 1000 A ISB Standby current SCL = SDA = VDD. All other inputs VSS or VDD. Stop command issued. – 90 150 A IZZ Sleep mode current SCL = SDA = VDD. All other inputs VSS or VDD. Stop command issued. – 5 8 A ILI Input leakage current (Except WP and A2-A0) VSS < VIN < VDD –1 – +1 A Input leakage current (for WP and A2-A0) VSS < VIN < VDD –1 – +100 A ILO Output leakage current VSS < VIN < VDD VIH Input HIGH voltage VIL Input LOW voltage VOL1 Output LOW voltage IOL = 2 mA, VDD > 2.7 V VOL2 Output LOW voltage IOL = 150 A Rin[2] Input resistance (WP, A2-A0) For VIN = VIL (Max) For VIN = VIH (Min) 1 –1 – +1 A 0.7 × VDD – VDD + 0.3 V – 0.3 – 0.3 × VDD V – – 0.4 V – – 0.2 V 50 – – k – – M Notes 1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested. 2. The input pull-down circuit is strong (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH. Document Number: 001-84462 Rev. *H Page 11 of 21 FM24V05 Data Retention and Endurance Parameter TDR NVC Description Test condition TA = 85 C Data retention Endurance Min Max Unit 10 – Years TA = 75 C 38 – TA = 65 C 151 – Over operating temperature 1014 – Cycles Capacitance Parameter [3] Description Test Conditions CO Output pin capacitance (SDA) CI Input pin capacitance Max Unit 8 pF 6 pF TA = 25 C, f = 1 MHz, VDD = VDD(typ) Thermal Resistance Parameter [3] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions 8-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 137 C/W 40 C/W AC Test Loads and Waveforms Figure 17. AC Test Loads and Waveforms 3.6 V 1.8 k OUTPUT 100 pF AC Test Conditions Input pulse levels .................................10% and 90% of VDD Input rise and fall times .................................................10 ns Input and output timing reference levels ................0.5 × VDD Output load capacitance ............................................ 100 pF Note 3. These parameters are guaranteed by design and are not tested. Document Number: 001-84462 Rev. *H Page 12 of 21 FM24V05 AC Switching Characteristics Over the Operating Range Alt. Parameter[4] Parameter F/S-mode [6] Description Hs-mode[6] Unit Min Max Min Max – 1.0 – 3.4 MHz fSCL[5] SCL clock frequency tSU; STA Start condition setup for repeated Start 260 – 160 – ns tHD;STA Start condition hold time 260 – 160 – ns tLOW Clock LOW period 500 – 160 – ns tHIGH Clock HIGH period 260 – 60 – ns tSU;DAT[7] tSU;DATA Data in setup 50 – 10 – ns tHD;DAT tHD;DATA Data in hold 0 – 0 – ns Data output hold (from SCL @ VIL) 0 – 0 – ns tR[8] tr Input rise time – 120 – 80 ns tF[8] tf Input fall time – 120 – 80 ns 260 – 160 – ns tDH STOP condition setup tSU;STO SCL LOW to SDA Data Out Valid – 450 – 130 ns tBUF tVD;DATA Bus free before new transmission 500 – 300 – ns tSP Noise suppression time constant on SCL, SDA – 50 – 5 ns tAA Figure 18. Read Bus Timing Diagram tHIGH tR ` tF tSP tLOW tSP SCL tSU:SDA 1/fSCL tBUF tHD:DAT tSU:DAT SDA tDH tAA Stop Start Start Acknowledge Figure 19. Write Bus Timing Diagram tHD:DAT SCL tHD:STA tSU:STO tSU:DAT tAA SDA Start Stop Start Acknowledge Notes 4. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified IOL and load capacitance shown in Figure 17. 5. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max). 6. Bus Load (Cb) considerations; Cb < 500 pF for I2C clock frequency (SCL) 1 MHz; Cb < 100 pF for SCL at 3.4 MHz. 7. In Hs-mode and VDD < 2.7 V, the tSU:DAT (min.) spec is 15 ns. 8. These parameters are guaranteed by design and are not tested. Document Number: 001-84462 Rev. *H Page 13 of 21 FM24V05 Power Cycle Timing Over the Operating Range Parameter Description Min Max Unit 250 – µs tPU Power-up VDD(min) to first access (START condition) tPD Last access (STOP condition) to power-down (VDD(min)) 0 – µs tVR [9, 10] VDD power-up ramp rate 50 – µs/V tVF [9, 10] VDD power-down ramp rate 100 – µs/V tREC [10] Recovery time from sleep mode – 400 µs VDD ~ ~ Figure 20. Power Cycle Timing VDD(min) tVR SDA I2 C START tVF tPD ~ ~ tPU VDD(min) I2 C STOP Notes 9. Slope measured at any point on the VDD waveform. 10. Guaranteed by design. Document Number: 001-84462 Rev. *H Page 14 of 21 FM24V05 Ordering Information Package Diagram Ordering Code FM24V05-G 51-85066 Package Type 8-pin SOIC Operating Range Industrial FM24V05-GTR All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions FM 24 V 05 - G TR Option: blank = Standard; TR = Tape and Reel Package Type: G = 8-pin SOIC Density: 05 = 512-Kbit Voltage: V = 2.0 V to 3.6 V I2C F-RAM Cypress Document Number: 001-84462 Rev. *H Page 15 of 21 FM24V05 Package Diagram Figure 21. 8-pin SOIC (150 Mils) Package Outline, 51-85066 51-85066 *F Document Number: 001-84462 Rev. *H 51-85066 *G Page 16 of 21 FM24V05 Acronyms Acronym Document Conventions Description Units of Measure ACK Acknowledge CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance Hz hertz I2C Inter-Integrated Circuit Kb 1024 bit I/O Input/Output kHz kilohertz JEDEC Joint Electron Devices Engineering Council k kilohm LSB Least Significant Bit MHz megahertz MSB Most Significant Bit M megaohm NACK No Acknowledge A microampere RoHS Restriction of Hazardous Substances s microsecond R/W Read/Write mA milliampere SCL Serial Clock Line ms millisecond SDA Serial Data Access ns nanosecond SOIC Small Outline Integrated Circuit ohm WP Write Protect % percent pF picofarad V volt W watt Document Number: 001-84462 Rev. *H Symbol Unit of Measure Page 17 of 21 FM24V05 Errata This document describes the errata for the serial I2C F-RAM FM24V05 (512-Kbit) product. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device's datasheet for a complete functional description. Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to [email protected]. Part Numbers Affected Part Number FM24V05 Device Characteristics 512-Kbit (64 K × 8) Serial (I2C) F-RAM with Device ID, 2.0 V to 3.6 V, Industrial temperature FM24V05 I2C F-RAM Qualification Status Production parts. FM24V05 Errata Summary The following table defines the errata applicability to available FM24V05 devices. Items Part Number 1. The I2C F-RAM enters Sleep mode without the STOP condition FM24V05-G FM24V05-GTR Silicon Revision Rev A Fix Status None. 1. The I2C F-RAM enters Sleep mode without the STOP condition ■ Problem Definition When the I2C master sends the last Reserved Slave ID (86h) of the Sleep command sequence, as shown in Figure 22, the I2C F-RAM returns an acknowledgement (ACK) and releases the SDA line after the rising edge of the 9th clock. If this LOW to HIGH transition on the SDA line happens when the I2C clock is HIGH, it artificially generates an unintended STOP. Figure 22. I2C F-RAM Sleep Cycle ■ Parameters Affected None of the existing parameters are affected. ■ Trigger Condition(S) The I2C master sends the last Reserved Slave ID (86h) of the Sleep command and receives an ACK from the I2C F-RAM. The I2C F-RAM starts entering the Sleep mode from the 9th rising edge of the I2C clock and releases the SDA line when in the Sleep mode. The LOW to HIGH transition on the SDA line when I2C clock is HIGH generates an unintended STOP. Document Number: 001-84462 Rev. *H Page 18 of 21 FM24V05 ■ Scope of Impact The ongoing I2C communication can be disrupted due to unintended STOP generated by the I2C F-RAM slave. ■ Workaround This issue can be mitigated by implementing one of the following two methods: The I2C master ignores any unintended STOP generated by the I2C F-RAM slave. 2 2 ❐ The I C master latches the ACK on the 9th rising edge of the I C clock and starts driving the SDA line LOW. This will ensure when the I2C F-RAM enters Sleep and releases the SDA line; it still remains LOW driven by the I2C master. This will prevent unintended LOW to HIGH transition when SCL is LOW. ❐ ■ Fix Status This issue is applicable to all the existing I2C F-RAM parts shown in this errata. The existing parts are in production status and will continue serving with errata. There is no plan to fix this issue in the existing silicon. Document Number: 001-84462 Rev. *H Page 19 of 21 FM24V05 Document History Page Document Title: FM24V05, 512-Kbit (64 K × 8) Serial (I2C) F-RAM Document Number: 001-84462 Rev. ECN No. Submission Date Orig. of Change ** 3902204 02/25/2013 GVCH New spec *A 3985098 05/09/2013 GVCH Removed FM24VN05 part related information Updated SOIC package marking scheme Description of Change *B 4014247 05/29/2013 GVCH Added Appendix A - Errata for FM24V05 *C 4045469 06/30/2013 GVCH All errata items are fixed and the errata is removed. *D 4283417 02/18/2014 GVCH Converted to Cypress standard format Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Added Input leakage current (ILI) for WP and A2-A0 Updated Data Retention and Endurance table Added Thermal Resistance table Removed Package Marking Scheme (top mark) *E 4564960 11/10/2014 GVCH Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *F 4700243 03/26/2015 GVCH Updated Package Diagram: spec 51-85066 – Changed revision from *F to *G. Added Errata. *G 4781095 05/29/2015 GVCH Updated Ordering Information: Fixed Typo (Replaced “001-85066” with “51-85066” in “Package Diagram” column). Updated to new template. *H 4874648 08/06/2015 Document Number: 001-84462 Rev. *H ZSK / PSR Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Page 20 of 21 FM24V05 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-84462 Rev. *H Revised August 6, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21