MC14175B D

MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each of the four flip−flops is positive−edge
triggered by a common clock input (C). An active−low reset input (R)
asynchronously resets all flip−flops. Each flip−flop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip−flops for
counter and toggle applications.
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Features
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SOIC−16
D SUFFIX
CASE 751B
Complementary Outputs
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Output Compatible with Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load
Functional Equivalent to TTL 74175
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
PIN ASSIGNMENT
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Value
Unit
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
−65 to +150
°C
260
°C
Input or Output Voltage Range
(DC or Transient)
Storage Temperature Range
Lead Temperature (8−Second Soldering)
R
1
16
VDD
Q0
2
15
Q3
Q0
3
14
Q3
D0
4
13
D3
D1
5
12
D2
Q1
6
11
Q2
Q1
7
10
Q2
VSS
8
9
C
MARKING DIAGRAMS
Symbol
DC Supply Voltage Range
SOEIAJ−16
F SUFFIX
CASE 966
16
16
14175BG
AWLYWW
1
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
MC14175B
ALYWG
1
SOIC−16
A
WL, L
YY, Y
WW, W
G
SOEIAJ−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
MC14175BDG
SOIC−16
(Pb−Free)
48 Units/Rail
MC14175BDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
NLV14175BDR2G* SOIC−16
(Pb−Free)
2500/Tape & Reel
MC14175BFELG
2000/Tape & Reel
Device
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9
1
Publication Order Number:
MC14175B/D
MC14175B
TRUTH TABLE
Inputs
Outputs
Clock
Data
Reset
Q
Q
X
0
1
X
X
1
1
1
0
0
1
Q
0
1
0
Q
1
No
Change
X = Don’t Care
9
CLOCK
1
RESET
4
D0
5
D1
12
D2
13
D3
Q0
2
Q0
3
Q1
7
Q1
6
Q2
10
Q2
11
Q3
15
Q3
14
VDD = PIN 16
VSS = PIN 8
Figure 1. Block Diagram
Figure 2. Timing Diagram
Figure 3. Functional Block Diagram
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2
MC14175B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C
25_C
VDD
125_C
Symbol
Vdc
Min
Max
Min
Typ
(Note 2)
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
“0” Level
“1” Level
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Source
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Max
Min
Max
Unit
VIL
Vdc
VIH
Vdc
IOH
mAdc
IT = (1.7 mA/kHz) f + IDD
IT = (3.4 mA/kHz) f + IDD
IT = (5.0 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
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3
MC14175B
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
tTLH, tTHL
Propagation Delay Time — Clock to Q, Q
tPLH, tPHL = (0.9 ns/pF) CL + 175 ns
tPLH, tPHL = (0.36 ns/pF) CL + 72 ns
tPLH, tPHL = (0.26 ns/pF) CL + 57 ns
tPLH, tPHL
Propagation Delay Time — Reset to Q, Q
tPHL = (0.9 ns/pF) CL + 280 ns
tPHL = (0.36 ns/pF) CL + 112 ns
tPHL = (0.26 ns/pF) CL + 87 ns
tPHL, tPLH
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
220
90
70
400
160
120
5.0
10
15
−
−
−
325
130
100
500
200
150
Unit
ns
ns
ns
Clock Pulse Width
tWH
5.0
10
15
250
100
75
110
45
35
−
−
−
ns
Reset Pulse Width
tWL
5.0
10
15
200
80
60
100
40
30
−
−
−
ns
fcl
5.0
10
15
−
−
−
4.5
11
14
2.0
5.0
6.5
mHz
tTLH, tTHL
5.0
10
15
−
−
−
−
−
−
15
5.0
4.0
ms
Data Setup Time
tsu
5.0
10
15
120
50
40
60
25
20
−
−
−
ns
Data Hold Time
th
5.0
10
15
80
40
30
40
20
15
−
−
−
ns
trem
5.0
10
15
250
100
80
125
50
40
−
−
−
ns
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
Reset Removal Time
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14175B
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14175B
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966
ISSUE A
16
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
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MC14175B/D