Revised March 2002 CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop General Description Features The CD40174BC consists of six positive-edge triggered Dtype flip-flops; the true outputs from each flip-flop are externally available. The CD40175BC consists of four positiveedge triggered D-type flip-flops; both the true and complement outputs from each flip-flop are externally available. ■ Wide supply voltage range: All flip-flops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all Q outputs to logical “0” and Q s (CD40175BC only) to logical “1”. 3V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS ■ Equivalent to MC14174B, MC14175B ■ Equivalent to MM74C174, MM74C175 All inputs are protected from static discharge by diode clamps to VDD and VSS. Ordering Code: Order Number CD40174BCM Package Number M16A Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD40174BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD40175BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD40175BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams CD40174B CD40175B Top View Top View © 2002 Fairchild Semiconductor Corporation DS005987 www.fairchildsemi.com CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop October 1987 CD40174BC • CD40175BC Truth Table Inputs Clear Clock Outputs D Q (Note 1) H L X X L H ↑ H H L H ↑ L L H H H X NC NC H L X NC NC H = HIGH Level L = LOW Level X = Irrelevant ↑ = Transition from LOW-to-HIGH level NC = No change Note 1: Q for CD40175B only www.fairchildsemi.com Q 2 Recommended Operating Conditions (Note 3) (Note 3) −0.5V to +18V DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5V to VDD +0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −55°C to +125°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) Note 3: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15 VDC Input Voltage (VIN) DC Electrical Characteristics (Note 3) CD40174BC/CD40175BC Symbol IDD VOL Parameter −55°C Conditions Min VIH IOL IOH IIN Typ +125°C Max Min Max VDD = 5V, VIN = VDD or VSS 1.0 1.0 Current VDD = 10V, VIN = VDD or VSS 2.0 2.0 60 VDD = 15V, VIN = VDD or VSS 4.0 4.0 120 LOW Level Output VDD = 5V Voltage VDD = 10V |IO| < 1 µA HIGH Level Output VDD = 5V Voltage VDD = 10V |IO| < 1 µA VDD = 15V VIL +25°C Min Quiescent Device VDD = 15V VOH Max 30 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 4.95 4.95 5 9.95 9.95 10 9.95 14.95 14.95 15 14.95 µA V 4.95 V LOW Level Input VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 HIGH Level Input VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 Current (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current Units V V 0.36 mA mA VDD = 15V, VIN = 0V 0.1 −10−5 0.1 −1.0 VDD = 15V, VIN = 15V −0.1 10−5 −0.1 1.0 µA Note 4: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD40174BC • CD40175BC Absolute Maximum Ratings(Note 2) CD40174BC • CD40175BC AC Electrical Characteristics (Note 5) TA = 25°C, CL = 50 pF, RL = 200k and tr = tf = 20 ns, unless otherwise specified Symbol tPHL, tPLH tPHL tPLH tSU tH tTHL, tTLH tWH, tWL tWL tRCL tfCL fCL CIN CPD Parameter Typ Max VDD = 5V 190 300 Logical “0” or Logical “1” from VDD = 10V 75 110 Clock to Q or Q (CD40175 Only) VDD = 15V 60 90 Propagation Delay Time to a VDD = 5V 180 300 Logical “0” from Clear to Q VDD = 10V 70 110 VDD = 15V 60 90 Propagation Delay Time to a Logical VDD = 5V 230 400 “1” from Clear to Q (CD40175 Only) VDD = 10V 90 150 VDD = 15V 75 120 Time Prior to Clock Pulse that VDD = 5V 45 100 Data must be Present VDD = 10V 15 40 VDD = 15V 13 35 Time after Clock Pulse that VDD = 5V −11 0 Data Must be Held VDD = 10V −4 0 VDD = 15V −3 0 Propagation Delay Time to a Transition Time Minimum Clock Pulse Width Minimum Clear Pulse Width Maximum Clock Rise Time Maximum Clock Fall Time Maximum Clock Frequency Input Capacitance Power Dissipation Conditions Min VDD = 5V 100 200 VDD = 10V 50 100 VDD = 15V 40 80 VDD = 5V 130 250 VDD = 10V 45 100 VDD = 15V 40 80 VDD = 5V 120 250 VDD = 10V 45 100 VDD = 15V 40 80 VDD = 5V 15 VDD = 10V 5.0 VDD = 15V 5.0 Units ns ns ns ns ns ns ns ns µs VDD = 5V 15 50 VDD = 10V 5.0 50 VDD = 15V 5.0 50 VDD = 5V 2.0 3.5 VDD = 10V 5.0 10 VDD = 15V 6.0 12 µs MHz Clear Input 10 15 Other Input 5.0 7.5 Per Package (Note 6) 130 pF pF Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. www.fairchildsemi.com 4 CD40174BC • CD40175BC Switching Time Waveforms tr = tf = 20 ns 5 www.fairchildsemi.com CD40174BC • CD40175BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 6 CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com