MC74LVX74 Dual D-Type Flip-Flop with Set and Clear With 5.0 V−Tolerant Inputs The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. The signal level applied to the D input is transferred to O output during the positive going transition of the Clock pulse. Clear (CD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. http://onsemi.com SOIC−14 NB D SUFFIX CASE 751A TSSOP−14 DT SUFFIX CASE 948G Features • • • • • • • • • PIN ASSIGNMENT High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.5 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V These Devices are Pb−Free and are RoHS Compliant VCC CD2 D2 CP2 SD2 O2 O2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CD1 D1 CP1 SD1 O1 O1 GND 14−Lead (Top View) MARKING DIAGRAMS 14 14 SD1 4 SD D1 CP1 2 3 D 1 Q Q CP 5 6 O1 1 SOIC−14 NB O1 LVX74 A WL, L Y W, WW G or G CD CD1 LVX 74 ALYW G G LVX74G AWLYWW 1 TSSOP−14 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) SD2 10 PIN NAMES SD D2 CP2 12 11 D Q Q CP 9 8 O2 O2 CD CD2 13 Function CP1, CP2 D1, D2 CD1, CD2 SD1, SD2 On, On Clock Pulse Inputs Data Inputs Direct Clear Inputs Direct Set Inputs Outputs ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Figure 1. Logic Diagram © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 5 Pins 1 Publication Order Number: MC74LVX74/D MC74LVX74 OUTPUTS INPUTS SDn CDn CPn Dn On On OPERATING MODE L H H L X X X X H L L H Asynchronous Set Asynchronous Clear L L X X H H Undetermined H H H H ↑ ↑ h l H L L H Load and Read Register H H ↑ X NC NC Hold H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition; NC = No Change; X = High or Low Voltage Level or Transitions are Acceptable; ↑ = Low−to−High Transition; ↑ = Not a Low−to−High Transition; For ICC Reasons DO NOT FLOAT Inputs MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage –0.5 to +7.0 V Vin DC Input Voltage –0.5 to +7.0 V Vout DC Output Voltage –0.5 to VCC +0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation 180 mW Tstg Storage Temperature –65 to +150 _C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Dt/DV Operating Temperature, All Package Types Input Rise and Fall Time Min Max Unit 2.0 3.6 V 0 5.5 V 0 VCC V −40 +85 _C 0 100 ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions TA = 25°C VCC V Min 1.5 2.0 2.4 VIH High−Level Input Voltage 2.0 3.0 3.6 VIL Low−Level Input Voltage 2.0 3.0 3.6 VOH High−Level Output Voltage (Vin = VIH or VIL) IOH = −50mA IOH = −50mA IOH = −4mA 2.0 3.0 3.0 VOL Low−Level Output Voltage (Vin = VIH or VIL) IOL = 50mA IOL = 50mA IOL = 4mA 2.0 3.0 3.0 Iin Input Leakage Current Vin = 5.5V or GND ICC Quiescent Supply Current Vin = VCC or GND Typ TA = − 40 to 85°C Max Min 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.58 Max 2.0 3.0 0.0 0.0 Unit V 0.5 0.8 0.8 1.9 2.9 2.48 V V 0.1 0.1 0.36 0.1 0.1 0.44 V 3.6 ±0.1 ±1.0 mA 3.6 2.0 20.0 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 2 MC74LVX74 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol tPLH, tPHL tPLH, tPHL fmax tOSHL tOSLH Parameter Test Conditions Propagation Delay CP to O or O Propagation Delay SD or CD to O or O Maximum Clock Frequency (50% Duty Cycle) Output−to−Output Skew (Note 1) Min TA = −40 to 85°C Typ Max Min Max Unit ns VCC = 2.7V CL = 15pF CL = 50pF 7.3 9.8 15.0 18.5 1.0 1.0 18.5 22.0 VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 5.7 8.2 9.7 13.2 1.0 1.0 11.5 15.0 VCC = 2.7V CL = 15pF CL = 50pF 8.4 10.9 15.6 19.1 1.0 1.0 18.5 22.0 VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 6.6 9.1 10.1 13.6 1.0 1.0 12.0 15.5 VCC = 2.7V CL = 15pF CL = 50pF 55 45 135 60 50 40 VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 95 60 145 85 80 50 VCC = 2.7V VCC = 3.3 ±0.3V CL = 50pF CL = 50pF ns MHz 1.5 1.5 1.5 1.5 ns 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. TIMING REQUIREMENTS (Input tr = tf = 3.0ns) Parameter Symbol Guaranteed Limit VCC V TA = 25_C TA = −40 to 85_C Unit tw Minimum Pulse Width, CP 2.7V 3.3V ±0.3 8.5 6.0 10.0 7.0 ns tw Minimum Pulse Width, CD or SD 2.7V 3.3V ±0.3 8.5 6.0 10.0 7.0 ns tsu Minimum Setup Time, D to CP 2.7V 3.3V ±0.3 8.0 5.5 9.5 6.5 ns th Minimum Hold Time, D to CP 2.7V 3.3V ±0.3 0.5 0.5 0.5 0.5 ns Minimum Recovery Time, SD or CD to CP 2.7V 3.3V ±0.3 6.5 5.0 7.5 5.0 ns TA = 25°C TA = −40 to 85°C trec CAPACITIVE CHARACTERISTICS Typ Max Cin Input Capacitance 4 10 CPD Power Dissipation Capacitance (Note 2) 25 Symbol Min Parameter Min Max Unit 10 pF pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip−flop). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package) TA = 25°C Characteristic Symbol Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.5 V VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.5 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V http://onsemi.com 3 MC74LVX74 SWITCHING WAVEFORMS tw VCC 50% SD or CD GND tPHL VCC CP 50% 50% VCC O or O GND tw tPLH 1/fmax tPLH tPHL 50% VCC O or O trec 50% VCC VCC O or O 50% CP GND Figure 2. Figure 3. VALID VCC D 50% GND tsu th VCC 50% CP GND Figure 4. TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 5. http://onsemi.com 4 MC74LVX74 ORDERING INFORMATION Package Shipping† SOIC−14 NB (Pb−Free) 2500 Tape & Reel MC74LVX74DTG TSSOP−14 (Pb−Free) 96 Units / Rail MC74LVX74DTR2G TSSOP−14 (Pb−Free) 2500 Tape & Reel Device MC74LVX74DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MC74LVX74 PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MC74LVX74 PACKAGE DIMENSIONS D SOIC−14 NB CASE 751A−03 ISSUE K A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S e DETAIL A h A X 45 _ M A1 C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 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