Revised February 2005
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
■ Input voltage level translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
Package
Package Description
Number
74LVX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX74SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX74MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
© 2005 Fairchild Semiconductor Corporation
DS011606
Description
D1 , D2
Data Inputs
CP1, CP2
Clock Pulse Inputs
CD1, CD2
Direct Clear Inputs
SD1, SD2
Direct Set Inputs
Q1, Q1, Q2, Q2
Outputs
www.fairchildsemi.com
74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
May 1993
74LVX74
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
L
H
X
X
H
L
H
L
X
X
L
H
X
H
H
H
H
L
L
L
H
L
X
Q0
Q0
L
L
H
H
H
H
H
H
X
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
LOW-to-HIGH Clock Transition
Q0(Q0) Previous Q(Q) before LOW-to-HIGH Transition of Clock
www.fairchildsemi.com
2
Q
Recommended Operating
Conditions (Note 3)
0.5V to 7.0V
Supply Voltage (VCC )
DC Input Diode Current (IIK)
VI
Supply Voltage (VCC)
0.5V
20 mA
0.5V to 7V
DC Input Voltage (VI)
VO
0V to 5.5V
Output Voltage (VO)
DC Output Diode Current (IOK)
VO
2.0V to 3.6V
Input Voltage (VI)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
0.5V
VCC 0.5V
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Voltage (VO)
Input Rise and Fall Time ('t/'V)
DC Output Source
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
r25 mA
or Sink Current (IO)
DC VCC or Ground Current
r50 mA
65qC to 150qC
(ICC or IGND)
Storage Temperature (TSTG)
Power Dissipation
0 ns/V to 100 ns/V
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
180 mW
DC Electrical Characteristics
Symbol
VIH
Parameter
HIGH Level
Input Voltage
VIL
VOH
VOL
VCC
2.0
TA
Min
25qC
40qC to 85qC
TA
Typ
Max
Min
1.5
Units
Max
Conditions
1.5
3.0
2.0
2.0
3.6
2.4
2.4
V
LOW Level
2.0
0.5
Input Voltage
3.0
0.8
0.5
0.8
3.6
0.8
0.8
HIGH Level
2.0
1.9
2.0
1.9
Output Voltage
3.0
2.9
3.0
2.9
3.0
2.58
V
VIN
VIL or VIH
V
2.48
LOW Level
2.0
0.0
Output Voltage
3.0
0.0
0.1
0.1
VIN
0.1
0.1
3.0
0.36
0.44
V
VIL or VIH
IOH
50 PA
IOH
50 PA
IOH
4 mA
IOL
50 PA
IOL
50 PA
IOL
4 mA
IIN
Input Leakage Current
3.6
r0.1
r1.0
PA
VIN
5.5V or GND
ICC
Quiescent Supply Current
3.6
2.0
20.0
PA
VIN
VCC or GND
Noise Characteristics (Note 4)
Symbol
VCC
(V)
Parameter
TA
Typ
25qC
Limit
Units
CL (pF)
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.3
0.5
V
50
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.3
0.5
V
50
VIHD
Minimum High Level Dynamic Input Voltage
3.3
2.0
V
50
VILD
Maximum Low Level Dynamic Input Voltage
3.3
0.8
V
50
Note 4: Input tr
tf
3 ns
3
www.fairchildsemi.com
74LVX74
Absolute Maximum Ratings(Note 2)
74LVX74
AC Electrical Characteristics
Symbol
VCC
Parameter
tPLH
Propagation Delay
tPHL
CPn to Qn or Qn
(V)
2.7
3.3 r 0.3
tPLH
Propagation Delay
tPHL
CDn to SDn to Qn or Qn
2.7
3.3 r 0.3
tW
CPn or CDn or SDn
Pulse Width
tS
tREC
40qC to 85qC
TA
Min
Max
7.3
15
1.0
18.5
9.8
18.5
1.0
22
5.7
9.7
1.0
11.5
8.2
13.2
1.0
15
50
15
8.4
15.6
1.0
18.5
10.9
19.1
1.0
22
6.6
10.1
1.0
12
9.1
13.6
1.0
15.5
8.5
10
3.3 r 0.3
6
7
2.7
8.0
9.5
5.5
6.5
Hold Time
2.7
0.5
0.5
Dn to CPn
3.3 r 0.3
0.5
0.5
Recovery Time
2.7
6.5
7.5
3.3 r 0.3
5.0
5.0
Maximum Clock Frequency
2.7
3.3 r 0.3
15
50
ns
15
50
ns
15
50
ns
ns
ns
ns
55
135
50
15
45
60
40
50
95
145
80
60
85
50
MHz
tOSLH
Output to Output Skew
2.7
1.5
1.5
(Note 5)
3.3
1.5
1.5
|tPLHm–tPLHn|, tOSLH
15
50
tOSHL
Note 5: Parameter guaranteed by design. tOSLH
CL (pF)
Units
Max
3.3 r 0.3
CPn or SDn to CPn
fMAX
Typ
2.7
Setup Time
Dn to CPn
tH
25qC
TA
Min
50
ns
|tPHLm–tPHLn|
Capacitance
Symbol
TA
Parameter
Min
25qC
TA
Typ
Max
10
CIN
Input Capacitance
4
CPD
Power Dissipation
25
40qC to 85qC
Min
10
Capacitance (Note 6)
Note 6: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
www.fairchildsemi.com
4
Units
Max
pF
pF
74LVX74
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
www.fairchildsemi.com
74LVX74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
6
74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
7
www.fairchildsemi.com