ISL89400, ISL89401 ® Data Sheet August 11, 2009 100V, 1.25A Peak, High Frequency Half-Bridge Drivers FN6614.2 Features • Drives N-Channel MOSFET Half-Bridge The ISL89400, ISL89401 are 100V, high frequency, half-bridge N-Channel power MOSFET driver ICs. They are based on the popular HIP2100, HIP2101 half-bridge drivers, but offer several performance improvements. The ISL89400 has additional input hysteresis for superior operation in noisy environments and the inputs of the ISL89401 (like those of the ISL89400) can now safely swing to the VDD supply rail. Finally, both parts are available in a very compact 9 Ld DFN package and an 8 Ld SOIC to minimize the required PCB footprint. • Space Saving DFN Package • DFN Package Compliant with 100V Conductor Spacing Guidelines per IPC-2221 • Pb-Free (RoHS Compliant) • Bootstrap Supply Max Voltage to 114VDC • On-Chip 1Ω Bootstrap Diode • Fast Propagation Times for Multi-MHz Circuits • Drives 1nF Load with Typical Rise/Fall Times of 16ns Ordering Information • CMOS Compatible Input Thresholds (ISL89400) PART NUMBER PART TEMP. (Note) MARKING RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL89400AR3Z* 9400 -40 to +125 9 Ld 3x3 DFN L9.3x3 ISL89401AR3Z* 9401 -40 to +125 9 Ld 3x3 DFN L9.3x3 ISL89400ABZ** 89400 ABZ -40 to +125 8 Ld SOIC M8.15 ISL89401ABZ** 89401 ABZ -40 to +125 8 Ld SOIC M8.15 *Add “-T” suffix for tape and reel. **Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • No Start-up Problems • Outputs Unaffected by Supply Glitches, HS Ringing Below Ground or HS Slewing at High dV/dt • Low Power Consumption • Wide Supply Voltage Range (9V to 14V) • Supply Undervoltage Protection • 4.0Ω Typical Output Pull-up/Pull-down Resistance Applications • Telecom Half-Bridge Converters VDD 1 8 LO HB 2 7 VSS HO 3 6 LI 5 • Two-Switch Forward Converters ISL89400, ISL89401 (9 LD DFN) TOP VIEW ISL89400, ISL89401 (8 LD SOIC) TOP VIEW 4 • Independent Inputs Provide Flexibility • Telecom Full-Bridge Converters Pinouts HS • 3.3V/TTL Compatible Input Thresholds (ISL89401) HI • Active-Clamp Forward Converters • Class-D Audio Amplifiers VDD 1 HB 2 HO 3 6 HI HS 4 5 NC 9 LO 8 VSS EPAD 7 LI NOTE: EPAD = Exposed PAD. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.. ISL89400, ISL89401 Application Block Diagram +12V +100V SECONDARY CIRCUIT VDD HB DRIVE HI PWM CONTROLLER LI CONTROL HI HO HS LO DRIVE LO ISL89400 ISL89401 VSS REFERENCE AND ISOLATION Functional Block Diagram HB VDD UNDERVOLTAGE HO LEVEL SHIFT DRIVER HS HI ISL89401 UNDERVOLTAGE LO ISL89401 DRIVER LI VSS EPAD (DFN PACKAGE ONLY) *EPAD = EXPOSED PAD. THE EPAD IS ELECTRICALLY ISOLATED FROM ALL OTHER PINS. FOR BEST THERMAL PERFORMANCE, CONNECT THE EPAD TO THE PCB POWER GROUND PLANE. 2 FN6614.2 August 11, 2009 ISL89400, ISL89401 +48V +12V PWM ISL89400 ISL89401 SECONDARY CIRCUIT ISOLATION FIGURE 1. TWO-SWITCH FORWARD CONVERTER +48V SECONDARY CIRCUIT +12V PWM ISL89400 ISL89401 ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP 3 FN6614.2 August 11, 2009 ISL89400, ISL89401 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD, VHB - VHS (Notes 1, 2) . . . . . . . -0.3V to 18V LI and HI Voltages (Note 2) . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on LO (Note 2) . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on HO (Note 2) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V Voltage on HS (Continuous) (Note 2) . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 9 Ld DFN (Notes 3, 5) . . . . . . . . . . . . . 55 7.5 8 Ld SOIC (Note 4) . . . . . . . . . . . . . . . 115 N/A Max Power Dissipation at +25°C in Free Air (Notes 3, 5) . . . . . 2.27W Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Maximum Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB . . VHS + 8V to VHS + 14V and VDD - 1V to VDD + 100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. The ISL89400 and ISL89401 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating curve for this mode of operation. 2. All voltages referenced to VSS, unless otherwise specified. 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details. Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS TJ = -40°C to +125°C MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS VDD Quiescent Current IDD ISL89400; LI = HI = 0V - 0.1 0.25 - 0.3 mA VDD Quiescent Current IDD ISL89401; LI = HI = 0V - 0.3 0.45 - 0.55 mA VDD Operating Current IDDO ISL89400; f = 500kHz - 1.6 2.2 - 2.7 mA VDD Operating Current IDDO ISL89401; f = 500kHz - 1.9 2.5 - 3 mA Total HB Quiescent Current IHB LI = HI = 0V - 0.1 0.15 - 0.2 mA Total HB Operating Current IHBO f = 500kHz - 2.0 2.5 - 3 mA HB to VSS Current, Quiescent IHBS LI = HI = 0V; VHB = VHS = 114V - 0.05 1 - 10 µA HB to VSS Current, Operating IHBSO f = 500kHz; VHB = VHS = 114V - 0.9 - - - mA INPUT PINS Low Level Input Voltage Threshold VIL ISL89400 3.7 4.4 - 2.7 - V Low Level Input Voltage Threshold VIL ISL89401 1.4 1.8 - 1.2 - V High Level Input Voltage Threshold VIH ISL89400 - 6.6 7.4 - 8.4 V High Level Input Voltage Threshold VIH ISL89401 - 1.8 2.2 - 2.4 V VIHYS ISL89400 - 2.2 - - - V RI - 210 - 100 500 kΩ VDD Rising Threshold VDDR 6.8 7.3 7.8 6.5 8.1 V VDD Threshold Hysteresis VDDH - 0.6 - - - V HB Rising Threshold VHBR 6.2 6.9 7.5 5.9 7.8 V Input Voltage Hysteresis Input Pull-down Resistance UNDER VOLTAGE PROTECTION 4 FN6614.2 August 11, 2009 ISL89400, ISL89401 Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TJ = +25°C PARAMETERS SYMBOL HB Threshold Hysteresis TEST CONDITIONS VHBH TJ = -40°C to +125°C MIN TYP MAX MIN MAX UNITS - 0.6 - - - V BOOT STRAP DIODE Low Current Forward Voltage VDL IVDD-HB = 100µA - 0.5 0.6 - 0.7 V High Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.9 - 1 V Dynamic Resistance RD IVDD-HB = 100mA - 0.8 1 - 1.5 Ω LO GATE DRIVER Low Level Output Voltage VOLL ILO = 100mA - 0.4 0.5 - 0.7 V High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD - VLO - 0.4 0.5 - 0.7 V Peak Pull-Up Current IOHL VLO = 0V - 1.25 - - - A Peak Pull-Down Current IOLL VLO = 12V - 1.25 - - - A Low Level Output Voltage VOLH IHO = 100mA - 0.4 0.5 - 0.7 V High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB - VHO - 0.4 0.5 - 0.7 V Peak Pull-up Current IOHH VHO = 0V - 1.25 - - - A Peak Pull-down Current IOLH VHO = 12V - 1.25 - - - A HO GATE DRIVER Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified PARAMETERS SYMBOL Lower Turn-off Propagation Delay (LI Falling to LO Falling) TEST CONDITIONS TJ = +25°C TJ = -40°C to +125°C MIN TYP MAX MIN MAX UNITS tLPHL - 34 50 - 60 ns Upper Turn-off Propagation Delay (HI Falling to HO Falling) tHPHL - 31 50 - 60 ns Lower Turn-on Propagation Delay (LI Rising to LO Rising) tLPLH - 39 50 - 60 ns Upper Turn-on Propagation Delay (HI Rising to HO Rising) tHPLH - 39 50 - 60 ns Delay Matching: Upper Turn-Off to Lower Turn-On tMON 1 8 - - 16 ns Delay Matching: Lower Turn-Off to Upper Turn-On tMOFF 1 6 - - 16 ns Either Output Rise/Fall Time (10% to 90%/90% to 10%) tRC,tFC CL = 1nF - 16 - - - ns CL = 0.1µF - 0.8 1.0 - 1.2 µs Either Output Rise/Fall Time (3V to 9V/9V to 3V) tR,tF Minimum Input Pulse Width that Changes the Output tPW - - - - 50 ns Bootstrap Diode Turn-On or Turn-Off Time tBS - 10 - - - ns 5 FN6614.2 August 11, 2009 ISL89400, ISL89401 Pin Descriptions SYMBOL DESCRIPTION VDD Positive supply to lower gate driver. Bypass this pin to VSS. HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. HO High-side output. Connect to gate of high-side power MOSFET. HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. HI High-side input. LI Low-side input. VSS Chip negative supply, which will generally be ground. LO Low-side output. Connect to gate of low-side power MOSFET. NC No connect. EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. Timing Diagrams LI HI HI, LI tHPLH , tLPLH tHPHL, tLPHL LO tMOFF tMON HO, LO HO FIGURE 3. PROPAGATION DELAYS FIGURE 4. DELAY MATCHING Typical Performance Curves 10.0 10.0 T = -40°C T = +25°C 1.0 IDDO (mA) IDDO (mA) T = -40°C T = +125°C T = +25°C T = +125°C 1.0 T = +150°C T = +150°C 0.1 10k 100k FREQUENCY (Hz) FIGURE 5. ISL89400 IDD OPERATING CURRENT vs FREQUENCY 6 1M 0.1 10k 100k 1M FREQUENCY (Hz) FIGURE 6. ISL89401 IDD OPERATING CURRENT vs FREQUENCY FN6614.2 August 11, 2009 ISL89400, ISL89401 Typical Performance Curves (Continued) 10.00 10.00 T = +125°C T = -40°C 1.00 T = +25°C IHBO (mA) IHBO (mA) 1.00 0.10 0.10 T = -40°C T = +150°C T = +125°C 0.01 T = +150°C T = +25°C 10k 100k 0.01 1M 10k 100k FREQUENCY (Hz) FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY 500 FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY 450 VDD = VHB = 9V 400 VDD = VHB = 12V 300 250 350 300 250 150 -50 0 50 VDD = VHB = 12V 200 VDD = VHB = 14V 200 150 VDD = VHB = 9V 400 VOLL, VOLH (mV) VOLL, VOLH (mV) 450 350 100 150 VDD = VHB = 14V -50 0 TEMPERATURE (°C) 150 0.60 VHBH 0.55 7.2 VDDH, VHBH (V) VDDR, VHBR (V) 100 FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE VDDR 7.4 VHBR 7.0 6.8 50 TEMPERATURE (°C) FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE 7.6 1M FREQUENCY (Hz) 0.50 0.45 VDDH 0.40 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE 7 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE FN6614.2 August 11, 2009 ISL89400, ISL89401 Typical Performance Curves tLPLH 50 45 40 tHPLH 35 30 tLPHL 25 20 tHPHL -50 0 50 55 tLPLH, tLPHL, tHPLH, tHPHL (ns) tLPLH, tLPHL, tHPLH, tHPHL (ns) 55 (Continued) 100 tLPLH 50 45 tHPLH 40 35 30 tHPHL 25 20 150 -50 0 FIGURE 13. ISL89400 PROPAGATION DELAYS vs TEMPERATURE 9 tMOFF tMON, tMOFF (ns) tMON, tMOFF (ns) 150 10 9 8 7 6 5 4 0 50 tMON 7 6 5 4 3 tMON -50 8 100 2 150 tMOFF -50 0 TEMPERATURE (°C) 50 100 150 TEMPERATURE (°C) FIGURE 15. ISL89400 DELAY MATCHING vs TEMPERATURE FIGURE 16. ISL89401 DELAY MATCHING vs TEMPERATURE 1.25 1.25 1.00 1.00 IOLL, IOLH (A) IOHL, IOHH (A) 100 FIGURE 14. ISL89401 PROPAGATION DELAYS vs TEMPERATURE 10 0.75 0.50 0.25 0 50 TEMPERATURE (°C) TEMPERATURE (°C) 3 tLPHL 0.75 0.50 0.25 0 2 4 6 8 10 12 VLO, VHO (V) FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE 8 0 0 2 4 6 8 10 12 VLO, VHO (V) FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE FN6614.2 August 11, 2009 ISL89400, ISL89401 260 240 220 200 180 160 140 120 100 80 60 40 20 0 (Continued) IDD IDD, IHB (µA) IDD, IHB (µA) Typical Performance Curves IHB 0 5 10 15 20 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 IDD IHB 0 5 VDD, VHB (V) FIGURE 19. ISL89400 QUIESCENT CURRENT vs VOLTAGE 20 120 VHS TO VSS VOLTAGE (V) FORWARD CURRENT (A) 15 FIGURE 20. ISL89401 QUIESCENT CURRENT vs VOLTAGE 1.00 0.10 0.01 1.10-3 1.10-4 1.10-5 1.10-6 0.3 10 VDD, VHB (V) 0.4 0.5 0.6 0.7 0.8 FORWARD VOLTAGE (V) FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS 9 100 80 60 40 20 0 12 13 14 15 VDD to VSS VOLTAGE (V) 16 FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE FN6614.2 August 11, 2009 ISL89400, ISL89401 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 10 FN6614.2 August 11, 2009 ISL89400, ISL89401 Dual Flat No-Lead Plastic Package (DFN) L9.3x3 2X 9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 0.15 C A A D MILLIMETERS 2X 0.15 C B E SYMBOL MIN 0.80 0.90 1.00 - - - 0.05 - 0.20 REF 0.20 D D2 B A C SEATING PLANE 2.00 0.80 1 6 4, 7 2.10 6, 7 - 0.95 1.05 6, 7 0.50 BSC - 0.08 C k 0.60 - - - L 0.25 0.35 0.45 7 N D2 9 2 Rev. 0 3/06 7 NOTES: D2/2 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2 2. N is the number of terminals. 3. All dimensions are in millimeters. Angles are in degrees. NX k 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. (DATUM A) E2/2 E2 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N 6. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. N-1 NX b 7 E2 0.30 3.00 BSC e A3 SIDE VIEW (DATUM B) 5 INDEX AREA 0.10 C 0.25 - 3.00 BSC 1.85 E // NOTES A b TOP VIEW MAX A1 A3 5 INDEX AREA NOMINAL e (Nd-1)Xe REF. BOTTOM VIEW 4 0.10 M C A B 7. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 8. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. CL NX (b) (A1) 8 L 4 e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6614.2 August 11, 2009