HIP5500 ® July 1998 WN ITHDRA TE W T R A P O LE S S OB S N S PROCE IG S W DE NO NE Features • 500V Maximum Rating • 2A Peak Gate Drive • Ability to Interface and Drive N-Channel Power Devices With Complimentary Outputs For Buffered FETs • Fault Output, Overcurrent Detection and Undervoltage Holdoff • Over 600kHz Sawtooth Oscillator Frequency • Adjustable Deadtime Control • Soft-Start Capability • Low Current Standby State • Sleep Mode Reduces Bias Current When Not Enabled Applications • Switching and Distributed Power Supplies 3210.3 High Voltage IC Half Bridge Gate Driver The HIP5500, a high voltage integrated circuit (HVIC) halfbridge gate driver for standard power MOSFETs, IGBTs, and the new Intersil Buffered MOSFET (RFV10N50BE), can be employed in a wide variety of switching regulator circuits. The HIP5500 combines the functionality and flexibility of a PWM IC with the convenience of a high voltage half-bridge driver optimized for power supply inverters. It can be used either open-loop or in closed-loop fashion using the SS input for controlling the output waveform duty-cycle. The HIP5500 incorporates a precision oscillator, adjustable using an external resistor and capacitor. The resistor sets the capacitor charging current and the capacitor sets the integration time of a triangle wave. Another resistor connected to the DIS pin adjusts the dead-time and can be tailored to the application. The oscillator switches at twice the output waveform fundamental frequency. The result is an output waveform whose positive and negative half-cycles are near perfect balance (volt-second equalization). Short-Detect (SD) and Soft-Start (SS) inputs provide alternative means for limiting and regulating respectively the half-bridge output voltage. A capacitor on the SS input will begin charging up once the EN input is made high and causes the duty cycle of each half-cycle to “ramp” the duty cycle of the output waveform. • Electronic Lighting Supplies Ordering Information PART NUMBER File Number The SD input can sense a signal proportional to current, providing a means of shortening the conduction periods below that imposed by the SS input. TEMPERATURE RANGE PACKAGE HIP5500IP -40oC to +85oC 20 Lead Plastic DIP HIP5500IB -40oC to +85oC 20 Lead Plastic SOIC (W) Other circuits within the HIP5500 “match” upper and lower turn-on and turn-off propagation times in order to minimize flux imbalances when driving output transformer loads. Pinout HIP5500 (PDIP, SOIC) TOP VIEW 1 NC 1 20 HO RT 2 19 HO DIS 3 18 VB NC 4 17 VS CT 5 16 NC SD 6 15 NC FLT 7 14 GND SS 8 13 VCC EN 9 12 LO OSC 10 11 LO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HIP5500 Typical Application Block Diagram POWER TRANSFORMER + LOAD HO OSC FLT SD + 500VDC VB DIS VS VCC 15VDC + HO EN CT HO HO TO BUFFERED FETs BUFFERED FETs LO RT LO SS GND LO TO BUFFERED FETs LO - Functional Block Diagram VCC FLT NOR LATCH VB SD VCC VCC VB UV OSC VCC BUFFER RT LEVEL SHIFT OSCILLATOR CT VS UPPER DRIVE HO HO VCC VS DFF D Q CK DIS QN LOWER DRIVE VCC CURRENT SOURCE LO LO GND UV SS VCC EN 2 HIP5500 Absolute Maximum Ratings Thermal Information Offset Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . -VBS to +500V Floating Supply Voltage (VB to VS) . . . . . . . . . . . . . . -0.3V to +18V High Side Channel Output Voltage, VHO, VNHO . VS -0.5 to VB +0.5 Fixed Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . -0.5V to +18V Low Side Channel Output Voltage . . . . . . . . . . . -0.5V to VCC +0.5V All Other Pin Voltages (SD, RT, CT, DIS, SS, EN and FLT) . . . . . . . . . -0.5V to VCC +0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . -40oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC (SOIC - Lead Tips Only) Offset Supply Maximum dv/dt, dVS /dt . . . . . . . . . . . . . . . . . . 50V/ns ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W See Maximum Power Dissipation vs Temperature Curve Figure 21 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions (TJ = -40oC to +125oC Unless Otherwise Noted, All Voltages Referenced to VSS) Offset Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . -2.0V to +500V Floating Supply Voltage, V BS (VB to VS) . . . . . . . . . . +10V to +15V High Side Channel Output Voltage, VHO,VNHO . . . . . . . 0V to VBS Fixed Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . +10V to +15V Low Side Channel Output Voltage, V LO,VNLO. . . . . . . . . 0V to VCC All Other Pin Voltages (SD, RT, CT, DIS, SS, FLT and EN) 0V to VCC Electrical Specifications Discharge Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Min Discharge Resistor Range, RDIS . . . . . . . . . . . . . . . . . 1kΩ to 50kΩ Charging Resistor Range, R T . . . . . . . . . . . . . . . . . .6.8kΩ to 400kΩ Oscillator Capacitor Range, C T. . . . . . . . . . . . . . . . . 100pF to 0.1µF Oscillator Frequency Range . . . . . . . . . . . . . . . . . . . . . 300kHz Max Oscillator Capacitor Charge Current Range, IRT . . . . . 21µA to 5mA VCC = VBS = +15V, VS = GND = 0V, Unless Otherwise Specified TJ = -40oC TO +125oC TJ = +25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Quiescent VCC Current IQCC - 5.5 7.0 - 8.0 mA Quiescent VBS Current IQBS - 300 400 - 435 µA (VS - GND) = 5.0V - 0.4 3.0 - - µA RT = 0 - 2.0 3.5 - 5.0 mA 2 1/ V 3 CC < VSFT < /3V CC 70 110 145 60 160 µA Low to High Transition 7.5 7.8 8.5 7.4 8.6 V - 2 - - - V Quiescent Leakage Current ILK Standby V CC Current ISTBY SS Current Source ISFT/PWM Input Threshold V EN Input Hysteresis VEN-HYS Undervoltage Threshold VUVHL High to Low Transition 7.7 8.6 9.5 7.4 9.6 V Undervoltage Threshold VUVLH Low to High Transition 7.9 8.8 9.7 7.6 9.8 V Undervoltage Hysteresis VUVHYS 0.08 0.3 0.7 0.05 0.75 V Short Detect Threshold V THSD 3.5 4.0 4.5 3.4 4.6 V CT /RT Current Ratio ICTRAT IRT = 100µA, VCC /3 < VCT < 2/3VCC 0.9 1 1.1 0.85 1.15 µA HO, LO Peak Output Current IOUT + Sourcing, LO, HO = GND 1.5 1.95 - 1.0 - A HO, LO Peak Output Current IOUT - Sinking, LO, HO = VCC = VBS 1.5 2.0 - 1.0 - A LO, HO Peak Output Current IBUF + Sourcing, LO, HO = Vss 170 250 - 110 - mA LO, HO Peak Output Current IBUF - Sinking, LO, HO = VCC = VBS 170 230 - 110 - mA 3 HIP5500 Electrical Specifications VCC = VBS = +15V, VS = GND = 0V, Unless Otherwise Specified (Continued) TJ = -40oC TO +125oC TJ = +25oC PARAMETER SYMBOL Soft-Start VTHRESH, Low to High V TSSHL Soft-Start VTHRESH, High to Low TEST CONDITIONS MIN TYP MAX MIN MAX UNITS 7.5 7.8 8.1 7.4 8.2 V V TSSLH 7.2 7.5 7.8 7.1 7.9 V OSC Input Upper Threshold V TCTLH 9.8 10.4 11.0 9.7 11.1 V OSC Input Upper Threshold V TCTHL CT to DIS 5.0 5.6 6.2 4.9 6.3 V Oscillator Upper to Lower Threshold Difference VCTDIF VT CTLH - VT CTHL 4.5 4.8 5.1 4.4 5.2 V OSC_OUT RDS ON, Sinking OSCRDSL IOSC_OUT = -50mA 5 8.5 12 2 17 Ω OSC_OUT RDS ON, Sourcing OSCR DH IOSC_OUT = 50mA 14 19 30 9 40 Ω CT = 7.5V DIS Output On Resistance RDSDIS IDIS = 10mA 75 115 150 - 200 Ω FLT Output On Resistance RDSFLT IFLT = 5mA 100 165 230 40 320 Ω Dynamic Electrical Specifications VCC = VBS = +15V, GND = 0V, Unless Otherwise Specified TJ = -40oC TO +125oC TJ = +25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Turn-On Rise Time, HO, LO tDR CL = 2000pF - - 50 - - ns Turn-Off Fall Time, HO, LO tDF CL = 2000pF - - 50 - - ns Turn-On Rise Time, HO, LO tDNR CBUF = 200pF - 25 35 - - ns Turn-Off Fall Time, HO, LO tDNF CBUF = 200pF - 25 35 - - ns CT Fall to LO/HO Rise TPCTLH CT = VTCTHL LO/HO LOAD = 200pF - 475 700 - 925 ns CT Rise to LO/HO Fall TPCTHL CT = VTCTLH LO/HO LOAD = 200pF - 475 700 - 925 ns LO-HO Prop Delay Mismatch Delmatch TPCTLH and TPCTHL - 60 - - - ns CT Rise to DIS Fall TPCTDISHL CT = VTCTHL - 300 450 - 475 ns CT Fall to DIS Rise TPCTDISLH CT = VTCTLH - 600 800 - 825 ns - 200 - - - ns SD = VTHSD, LO/HO = 200pF - 425 850 - 1100 ns SS = VTSSLH, LO/HO = 200pF - 500 750 - 775 ns Minimum Dead Time tDTMIN Short Detect Propagation Delay Soft-Start Propagation Delay Time 4 tSDLO/HO tSSDLY HIP5500 Typical Performance Curves All Curves are V CC = +15V, TA = +25oC, Unless Otherwise Specified QUIESCENT VCC SUPPLY CURRENT (mA) 100.0 50 LEAKAGE CURRENT (µA) 20 10.0 5 2 1.0 0.5 0.2 0.1 0.05 0.02 0.01 0.005 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 1. OFFSET SUPPLY LEAKAGE CURRENT vs TEMPERATURE AT 300VDC VBS = 15V 275 VBS = 12V 225 175 VBS = 10V 125 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 65 VCC = 10V VCC = 12V VCC = 15V 55 50 VCC = 10V VCC = 12V VCC = 15V 45 40 35 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 5. ENABLE/DISABLE THRESHOLD (PERCENT V CC) vs TEMPERATURE AND V CC SUPPLY VOLTAGE 5 VCC = 12V VCC = 10V -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 VCC = 15V VCC = 12V VCC = 10V -40 -20 0 +20 +40 +60 TEMPERATURE (oC) +80 +100 +120 FIGURE 4. QUIESCENT STANDBY CURRENT vs TEMPERATURE AND VCC SUPPLY VOLTAGE ENABLE/DISABLE HYSTERESIS VOLTAGE (V) ENABLE/DISABLE THRESHOLD VOLTAGE (% OF VCC) FIGURE 3. QUIESCENT FLOATING BIAS SUPPLY CURRENT vs TEMPERATURE AND V BS SUPPLY VOLTAGE 60 VCC = 15V FIGURE 2. QUIESCENT V CC CURRENT vs TEMPERATURE AND V CC SUPPLY VOLTAGE STANDBY CURRENT (mA) QUIESCENT FLOATING BIAS SUPPLY CURRENT (µA) 325 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 -40 2.0 1.9 1.8 1.7 VCC = 15V 1.6 1.5 VCC = 12V 1.4 1.3 VCC = 10V 1.2 1.1 1.0 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 6. ENABLE/DISABLE HYSTERESIS VOLTAGE TEMPERATURE AND VCC SUPPLY VOLTAGE HIP5500 Typical Performance Curves All Curves are V CC = +15V, TA = +25oC, Unless Otherwise Specified (Continued) 1.9 FAULT_NOT OUTPUT VOLTAGE (V) SOFT-START CURRENT SOURCE (µA) 120 110 100 VCC = 15V VCC = 12V VCC = 10V 90 80 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 1.3 1.1 0.9 0.7 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 8. FAULT_NOT LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE AND V CC SUPPLY VOLTAGE, SINKING 5mA 100 1.00 VCC = 15V VCC = 12V VCC = 10V 80 CT TO RT CURRENT RATIO CT TRIGGER/DISCHARGE VOLTAGES (% OF VCC 1.5 0.5 -40 +120 FIGURE 7. SOFT-START CURRENT SOURCE CURRENT vs TEMPERATURE AND VCC SUPPLY VOLTAGE VCC = 10V VCC = 12V VCC = 15V 1.7 60 40 VCC = 15V VCC = 12V VCC = 10V 20 0.98 0.96 0.94 0.92 0.90 0 -40 -20 0 +20 +40 +60 +80 +100 +120 -40 -20 0 TEMPERATURE (oC) FIGURE 9. C T RAMP TRIGGER AND DISCHARGE VOLTAGE TRIP POINT vs TEMPERATURE AND VCC SUPPLY VOLTAGE +20 +40 +60 +80 TEMPERATURE (oC) +100 FIGURE 10. CT TO R T CURRENT SOURCE RATIO vs TEMPERATURE SD THRESHOLD VOLTAGE (% OF VCC) 27.5 VCC = 15V VCC = 12V VCC = 10V 27.0 26.5 26.0 25.5 25.0 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 11. SHUTDOWN THRESHOLD VOLTAGE (% OF VCC) vs TEMPERATURE AND VCC SUPPLY VOLTAGE 6 +120 HIP5500 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 -40 All Curves are V CC = +15V, TA = +25oC, Unless Otherwise Specified (Continued) VCC = 15V SOURCING CURRENT (mA) SINKING CURRENT (mA) Typical Performance Curves VCC = 12V VCC = 10V -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 9.5 9.0 TRIP 8.5 RESET -20 0 +20 +40 +60 +80 +100 +120 TEMPERATURE (oC) FIGURE 14. LOW-SIDE UNDERVOLTAGE THRESHOLD VOLTAGE (TRIP/RESET) vs TEMPERATURE VCC = 12V VCC = 10V -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 10.0 TRIP 9.5 9.0 8.5 RESET 8.0 7.5 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 15. HIGH-SIDE UNDERVOLTAGE THRESHOLD VOLTAGE(TRIP/RESET) vs TEMPERATURE 1.0 1.0 0.9 PROPAGATION DELAY (µs) PROPAGATION DELAY (µs) VCC = 15V FIGURE 13. BUFFER GATE OUTPUT SHORT CIRCUIT SOURCING CURRENT vs TEMPERATURE AND VCC SUPPLY VOLTAGE UNDER-VOLTAGE THRESHOLD VOLTAGE (V) UNDER-VOLTAGE THRESHOLD VOLTAGES (V) 10.0 7.5 -40 -40 +120 FIGURE 12. BUFFER GATE OUTPUT SHORT CIRCUIT SINKING CURRENT vs TEMPERATURE AND V CC SUPPLY VOLTAGE 8.0 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 0.8 0.7 0.6 0.5 0.4 0.3 0.2 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) +100 +120 FIGURE 16. PROPAGATION DELAY, CT TO GATE OUTPUTS vs TEMPERATURE AT VCC = +15V 7 0.8 CT -DIS FALL 0.6 CT -DIS RISE 0.4 0.2 0.0 -40 -20 0 +20 +40 +60 +80 TEMPERATURE (oC) FIGURE 17. PROPAGATION DELAY, C T TO DIS vs TEMPERATURE AT VCC = +15V +100 +120 HIP5500 Typical Performance Curves All Curves are V CC = +15V, TA = +25oC, Unless Otherwise Specified (Continued) 1.6 1.0 PROPAGATION DELAY (µs) PROPAGATION DELAY (µs) 0.9 1.2 0.8 SD-LO FALL 0.8 0.7 0.6 SD-LO RISE 0.5 0.4 0.3 0.4 -40 -20 0 +20 +40 +60 +80 +100 +120 0.2 -40 TEMPERATURE (oC) -20 0 +20 +40 +60 +80 +100 +120 TEMPERATURE (oC) FIGURE 18. PROPAGATION DELAY, SS TO LO GATE RISING vs TEMPERATURE AT VCC = +15V FIGURE 19. PROPAGATION DELAYS, SD TO LO GATE RISE/FALL vs TEMPERATURE AT VCC = +15V 3 1.0 2.75 POWER DISSIPATION (W) PROPAGATION DELAY (µs) 0.9 0.8 0.7 0.6 0.5 0.4 HIP5500IP 2 HIP5500IB 1.75 1.5 1.25 1 0.75 0.5 0.3 0.25 11 12 13 SUPPLY VOLTAGE (VCC) 14 FIGURE 20. PROPAGATION DELAY, C T TO GATE OUT vs SUPPLY VOLTAGE, VCC AT +25oC FOR RISING AND FALLING GATE OUTPUTS 1.0 VS = 400V VS = 300V VS = 200V VS = 100V 0.01 100 SWITCHING FREQUENCY (kHz) 1000 -20 0 +20 +40 +60 +80 +100 FIGURE 21. MAXIMUM POWER DISSIPATION vs TEMPERATURE VS = VSS = COM VBS = VCC = 15VDC TA = +25 oC 1.0 2100pF 0.1 907pF 100pF 0.01 10 100 SWITCHING FREQUENCY (kHz) NOTE: All switching losses assumed to be in IC. FIGURE 22. HIGH VOLTAGE POWER DISSIPATION vs SWITCHING FREQUENCY 8 +120 AMBIENT TEMPERATURE (oC) 10 VBS = VCC = 15V CL = 100pF TA = +25 oC 0.1 0.001 10 0 -40 15 POWER DISSIPATION (W) 0.2 10 HIGH VOLTAGE POWER DISSIPATION (W) 2.5 2.25 FIGURE 23. LOW VOLTAGE POWER DISSIPATION vs FREQUENCY 1000 9 OSC EN VCC SS CT SD REN CX CT1 R1 CSS RDIS RT LED1 NC NC GND 14 VCC 13 LO2 12 LO1 11 7 FLT 8 SS 9 EN 10 OSC GND NC NC NC NC 2 +15VDC VCC C4 CY J3 DBS 1 VS CZ C5 RG2 J4 CBS RG1 J2 FIGURE 24. EVALUATION BOARD SCHEMATIC HIP5500 NC4 16 VS 17 4 NC2 NC3 15 VB 18 3 DIS 6 SD HO2 19 2 RT 5 CT HO1 20 U1 1 NC1 RSD RBS 1 1 Q2 Q1 COM 3 2 3 2 VBUS C OUT2 CTAP B OUT1 A D C3 J1 C2 C1 HIP5500 HIP5500 COM C2 Q1 CY C1 VBUS U1 SS RSD CSS REN R1 Q2 C3 1 DBS CX CT 1 HIP5500 SD RT RDIS CBS RG1 CT RBS RG2 1 EN CZ +15VDC VCC C4 LED1 OSC D C C5 GND TRANSFORMER GND T1 A CTAP FIGURE 25. HIP5500 EVALUATION BOARD SILKSCREEN 10 B HIP5500 Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D) 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE N E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE A2 -C- SEATING PLANE A L D1 D1 e B1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 D 0.980 1.060 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 11 MILLIMETERS e eA 0.100 BSC - L 0.115 20 0.355 26.9 2.54 BSC 0.300 BSC eB N 0.204 24.89 7.62 BSC 0.430 - 0.150 2.93 20 5 6 10.92 7 3.81 4 9 Rev. 0 12/93 HIP5500 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA 0.25(0.010) M H B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C A M MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e C 0.10(0.004) B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 12 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MIN MILLIMETERS 20 0o 20 8o 0o 7 8o Rev. 0 12/93