INTERSIL ISL2111

ISL2110, ISL2111
®
Data Sheet
July 11, 2006
100V, 3A/4A Peak, High Frequency
Half-Bridge Drivers
Features
• Drives N-Channel MOSFET Half-Bridge
The ISL2110, ISL2111 are 100V, high frequency, half-bridge
N-channel power MOSFET driver ICs. They are based on
the popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. Peak output pull-up/
pull-down current has been increased to 3A/4A, which
significantly reduces switching power losses and eliminates
the need for external totem-pole buffers in many
applications. Also, the low end of the VDD operational supply
range has been extended to 8VDC. The ISL2110 has
additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL2111, like those of the
ISL2110, can now safely swing to the VDD supply rail.
ISL2110ABZ
2110ABZ
PKG.
DWG. #
8 Ld SOIC
ISL2110AR4Z 2110AR4Z
-40 to 125
12 Ld 4x4 DFN L12.4x4A
ISL2111ABZ
-40 to 125
8 Ld SOIC
-40 to 125
12 Ld 4x4 DFN L12.4x4A
ISL2111AR4Z 2111AR4Z
• SOIC and DFN Packages Compliant with 100V Conductor
Spacing Guidelines per IPC-2221
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1Ω Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns
• CMOS Compatible Input Thresholds (ISL2110)
• Independent Inputs Provide Flexibility
PACKAGE
(Pb-Free)
-40 to 125
2111ABZ
• SOIC and DFN Package Options
• 3.3V/TTL Compatible Input Thresholds (ISL2111)
Ordering Information
PART
NUMBER
PART
TEMP.
(Notes 1, 2) MARKING RANGE (°C)
FN6295.1
M8.15
M8.15
• No Start-Up Problems
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground or HS Slewing at High dv/dt
• Low Power Consumption
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. Add “-T” suffix for Tape and Reel packing option.
• 1.6Ω/1Ω Typical Output Pull-Up/Pull-Down Resistance
Applications
• Telecom Half-Bridge DC/DC Converters
• Telecom Full-Bridge DC/DC Converters
• Two-Switch Forward Converters
• Active-Clamp Forward Converters
• Class-D Audio Amplifiers
Pinouts
ISL2110, ISL2111 (SOIC)
TOP VIEW
VDD
1
8
LO
HB
2
7
VSS
HO
3
6
LI
HS
4
5
HI
ISL2110, ISL2111 (DFN)
TOP VIEW
VDD
1
12 LO
NC
2
11 VSS
NC
3
HB
4
9
NC
HO
5
8
LI
HS
6
7
HI
10 NC
EPAD
NOTE: EPAD = Exposed PAD.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL2110, ISL2111
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
VDD
HB
DRIVE
HI
CONTROL
HI
PWM
CONTROLLER
LI
HO
HS
DRIVE
LO
LO
ISL2110
ISL2111
REFERENCE
AND
ISOLATION
VSS
Functional Block Diagram
HB
VDD
UNDER
VOLTAGE
HO
LEVEL SHIFT
DRIVER
HS
HI
ISL2111
ISL2111
UNDER
VOLTAGE
LO
DRIVER
LI
VSS
EPAD (DFN Package Only)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
2
FN6295.1
July 11, 2006
ISL2110, ISL2111
+48V
+12V
PWM
SECONDARY
CIRCUIT
ISL2110
ISL2111
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
ISL2110
ISL2111
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
3
FN6295.1
July 11, 2006
ISL2110, ISL2111
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB - VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Voltage on HO (Note 4) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
Maximum Recommended Operating Conditions
θJA (°C/W)
θJC (°C/W)
SOIC (Note 5) . . . . . . . . . . . . . . . . . . .
95
N/A
DFN (Note 6) . . . . . . . . . . . . . . . . . . . .
40
3
Max Power Dissipation at 25°C in Free Air (SOIC, Note 5) . . . . 1.3W
Max Power Dissipation at 25°C in Free Air (DFN, Note 6) . . . . . 3.1W
Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55°C to 150°C
Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . . 300°C
For recommended soldering conditions see Tech Brief TB389.
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . VHS + 7V to VHS + 14V and VDD - 1V to VDD + 100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
3. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating
curve for this mode of operation.
4. All voltages referenced to VSS unless otherwise specified.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
For θJC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = -40°C to
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
SUPPLY CURRENTS
VDD Quiescent Current
IDD
ISL2110; LI = HI = 0V
-
0.1
0.25
-
0.3
mA
VDD Quiescent Current
IDD
ISL2111; LI = HI = 0V
-
0.3
0.45
-
0.55
mA
VDD Operating Current
IDDO
ISL2110; f = 500kHz
-
3.4
5.0
-
5.5
mA
VDD Operating Current
IDDO
ISL2111; f = 500kHz
-
3.5
5.0
-
5.5
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
Total HB Operating Current
IHBO
f = 500kHz
-
3.4
5.0
-
5.5
mA
HB to VSS Current, Quiescent
IHBS
LI = HI = 0V; VHB = VHS = 114V
-
0.05
1.5
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz; VHB = VHS = 114V
-
1.2
-
-
-
mA
INPUT PINS
Low Level Input Voltage Threshold
VIL
ISL2110
3.7
4.4
-
3.5
-
V
Low Level Input Voltage Threshold
VIL
ISL2111
1.4
1.8
-
1.2
-
V
High Level Input Voltage Threshold
VIH
ISL2110
-
6.6
7.4
-
7.6
V
High Level Input Voltage Threshold
VIH
ISL2111
-
1.8
2.2
-
2.4
V
VIHYS
ISL2110
-
2.2
-
-
-
V
RI
-
210
-
100
500
kΩ
VDD Rising Threshold
VDDR
6.1
6.6
7.1
5.8
7.4
V
VDD Threshold Hysteresis
VDDH
-
0.6
-
-
-
V
Input Voltage Hysteresis
Input Pull-down Resistance
UNDER VOLTAGE PROTECTION
4
FN6295.1
July 11, 2006
ISL2110, ISL2111
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
TJ = -40°C to
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
HB Rising Threshold
VHBR
5.5
6.1
6.8
5.0
7.1
V
HB Threshold Hysteresis
VHBH
-
0.6
-
-
-
V
BOOT STRAP DIODE
Low Current Forward Voltage
VDL
IVDD-HB = 100µA
-
0.5
0.6
-
0.7
V
High Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.9
-
1
V
Dynamic Resistance
RD
IVDD-HB = 100mA
-
0.7
1
-
1.5
Ω
LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.1
0.18
-
0.25
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD - VLO
-
0.16
0.23
-
0.3
V
Peak Pull-Up Current
IOHL
VLO = 0V
-
3
-
-
-
A
Peak Pull-Down Current
IOLL
VLO = 12V
-
4
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.1
0.18
-
0.25
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB - VHO
-
0.16
0.23
-
0.3
V
Peak Pull-Up Current
IOHH
VHO = 0V
-
3
-
-
-
A
Peak Pull-Down Current
IOLH
VHO = 12V
-
4
-
-
-
A
HO GATE DRIVER
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = -40°C
to 125°C
TJ = 25°C
MIN
TYP
MAX
MIN
MAX
UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
tLPHL
-
32
50
-
60
ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
tHPHL
-
32
50
-
60
ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
tLPLH
-
39
50
-
60
ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
tHPLH
-
38
50
-
60
ns
Delay Matching: Upper Turn-Off to Lower Turn-On
tMON
1
8
-
-
16
ns
Delay Matching: Lower Turn-Off to Upper Turn-On
tMOFF
1
6
-
-
16
ns
Either Output Rise Time (10% to 90%)
tRC
CL = 1nF
-
9
-
-
-
ns
Either Output Fall Time (90% to 10%)
tFC
CL = 1nF
-
7.5
-
-
-
ns
Either Output Rise Time (3V to 9V)
tR
CL = 0.1µF
-
0.3
0.4
-
0.5
µs
Either Output Fall Time (9V to 3V)
tF
CL = 0.1µF
-
0.19
0.3
-
0.4
µs
Minimum Input Pulse Width that Changes the Output
tPW
-
-
-
-
50
ns
Bootstrap Diode Turn-On or Turn-Off Time
tBS
-
10
-
-
-
ns
5
FN6295.1
July 11, 2006
ISL2110, ISL2111
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
Positive supply to lower gate driver. Bypass this pin to VSS.
HB
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
High-side output. Connect to gate of high-side power MOSFET.
HS
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HI
High-side input.
LI
Low-side input.
VSS
Chip negative supply, which will generally be ground.
LO
Low-side output. Connect to gate of low-side power MOSFET.
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI
HI,
LI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 3. PROPAGATION DELAYS
FIGURE 4. DELAY MATCHING
Typical Performance Curves
10
IDDO (mA)
IDDO (mA)
10
1
0.1
10
100
FREQUENCY (kHz)
1 .10
T = -40C
T = 25C
T = 125C
T = 150C
3
1
0.1
10
100
FREQUENCY (kHz)
1 .10
3
T = -40C
T = 25C
T = 125C
T = 150C
FIGURE 5. ISL2110 IDD OPERATING CURRENT vs
FREQUENCY
6
FIGURE 6. ISL2111 IDD OPERATING CURRENT vs
FREQUENCY
FN6295.1
July 11, 2006
ISL2110, ISL2111
Typical Performance Curves
(Continued)
10
IHBSO (mA)
IHBO (mA)
10
1
0.1
0.01
10
1 .10
100
FREQUENCY (kHz)
1
0.1
0.01
3
FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY
3
FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY
200
300
250
VOLL, VOLH (mV)
VOHL, VOHH (mV)
1 .10
100
FREQUENCY (kHz)
T = -40C
T = 25C
T = 125C
T = 150C
T = -40C
T= 25C
T = 125C
T = 150C
200
150
150
100
100
50
50
0
50
TEMPERATURE (C)
100
50
150
50
VDD = VHB = 8V
VDD = VHB = 12V
VDD = VHB = 14V
50
TEMPERATURE (C)
100
150
FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE
0.7
6.5
0.65
VDDH, VHBH (V)
6.7
6.3
6.1
5.9
5.7
0.6
0.55
0.5
0.45
5.5
5.3
0
VDD = VHB = 8V
VDD = VHB = 12V
VDD = VHB = 14V
FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
VDDR, VHBR (V)
10
50
0
50
100
150
0.4
50
0
TEMPERATURE (C)
VDDR
VHBR
50
100
150
TEMPERATURE (C)
VDDH
VHBH
FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
7
FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FN6295.1
July 11, 2006
ISL2110, ISL2111
(Continued)
55
50
45
40
35
30
25
55
tLPLH, tLPHL, tHPLH, tHPHL (ns)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
Typical Performance Curves
50
0
50
TEMPERATURE (C)
100
50
45
40
35
30
25
150
50
0
tLPLH
tLPHL
tHPLH
tHPHL
8
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
tMON, tMOFF (ns)
tMON, tMOFF (ns)
7
6.5
6
5.5
5
4.5
0
150
FIGURE 14. ISL2111 PROPAGATION DELAYS vs
TEMPERATURE
7.5
50
100
tLPLH
tLPHL
tHPLH
tHPHL
FIGURE 13. ISL2110 PROPAGATION DELAYS vs
TEMPERATURE
4
50
TEMPERATURE (C)
50
TEMPERATURE (C)
100
150
50
0
tMON
tMOFF
50
TEMPERATURE (C)
100
150
tMON
tMOFF
FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE
FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE
3.5
4.5
4
3
2.5
IOLL, IOLH (A)
IOHL, IOHH (A)
3.5
2
1.5
1
3
2.5
2
1.5
1
0.5
0
0.5
0
2
4
6
VLO, VHO (V)
8
10
12
FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
8
0
0
2
4
6
VLO, VHO (V)
8
10
12
FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT
VOLTAGE
FN6295.1
July 11, 2006
ISL2110, ISL2111
IDD, IHB (uA)
120
110
100
90
80
70
60
50
40
30
20
10
0
(Continued)
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
IDD, IHB (uA)
Typical Performance Curves
0
5
10
VDD, VHB (V)
15
20
IDD
IHB
VDD to VSS VOLTAGE (V)
FORWARD CURRENT (A)
0.01
4
1 .10
5
1 .10
6
0.3
15
20
120
0.1
1 .10
10
VDD, VHB (V)
FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE
1
3
5
IDD
IHB
FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE
1 .10
0
0.4
0.5
0.6
FORWARD VOLTAGE (V)
0.7
0.8
FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS
9
100
80
60
40
20
0
12
13
14
VHS to VSS VOLTAGE (V)
15
16
FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE
FN6295.1
July 11, 2006
ISL2110, ISL2111
Dual Flat No-Lead Plastic Package (DFN)
Micro Lead Frame Plastic Package (MLFP)
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
0.15
A
C
D
A
D/2
D1
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
-
0.85
0.90
-
A1
0.00
0.01
0.05
-
A2
-
0.65
0.70
-
0.30
5, 8
A3
D1/2
b
2X
0.15
N
E1/2
E/2
E1
6
C
B
0.15
9
C
B
4.00 BSC
-
3.75 BSC
-
2.65
0.15
C
E2
B
TOP VIEW
A
4X 0
A2
A
//
0.08
C
SEATING
PLANE
A1
A3
SIDE VIEW
C
0.10
C
2.95
7, 8
-
3.75 BSC
1.43
e
2X
2.80
4.00 BSC
E1
1 2 3
2X
-
D
E
INDEX
AREA
0.23
D1
D2
E
0.20 REF
0.18
1.58
1.73
7, 8
0.50 BSC
-
k
0.635
-
-
-
L
0.30
0.40
0.50
8
N
12
Nd
2
6
3
P
0.24
0.42
0.60
θ
-
-
12
Rev. 0 8/03
7
8
NOTES:
D2
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
(Nd-1)Xe
REF.
2. N is the number of terminals.
D2/2
1
3. Nd refer to the number of terminals on D.
2 3
4. All dimensions are in millimeters. Angles are in degrees.
6
INDEX
AREA
E2
7
8
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX k
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
E2/2
4X P
N N-1
NX b
0.10
e
5
M
C A B
BOTTOM VIEW
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for
the L dimension.
CL
NX b
A1
L
5
C C
5
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
10
FN6295.1
July 11, 2006
ISL2110, ISL2111
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
FN6295.1
July 11, 2006