CM1216 6 and 8-Channel Low Capacitance ESD Arrays Product Description The CM1216 family of diode arrays provide sESD protection for electronic components or sub−systems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (VP) or negative (VN) supply rail. The CM1216 protects against ESD pulses up to ±15 kV per the IEC 61000−4−2 standard. This device is particularly well−suited for protecting systems using high−speed ports such as USB2.0, IEEE1394 (Firewire®, iLinkt), Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint. http://onsemi.com SOIC−8 SM SUFFIX CASE 751AC MSOP−8 MR SUFFIX CASE 846AD MSOP−10 MR SUFFIX CASE 846AE BLOCK DIAGRAM CH6 VP CH5 CH4 CH1 CH2 VN CH3 Features • Six and Eight Channels of ESD Protection • Provides ±15 kV ESD Protection on Each Channel per the • • • • • • • IEC 61000−4−2 ESD Requirements Channel Loading Capacitance of 1.6 pF Typical Channel I/O to GND Capacitance Difference of 0.04 pF Typical Mutual Capacitance of 0.13 pF Typical Minimal Capacitance Change with Temperature and Voltage Each I/O Pin Can Withstand Over 1000 ESD Strikes SOIC and MSOP Packages These Devices are Pb−Free and are RoHS Compliant CM1216−06SM CM1216−06MR CH8 CH7 CH1 CH2 VP CH6 CH5 CH3 CH4 VN CM1216−08MR MARKING DIAGRAM Applications • IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps • DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, • • • LCD Displays Serial ATA Ports in Desktop PCs and Hard Disk Drives PCI Express Ports General Purpose High−Speed Data Line ESD Protection XXXXX AYWWG G XXXXXX A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† CM1216−06SM SOIC (Pb−Free) MSOP (Pb−Free) MSOP (Pb−Free) 2500/Tape & Reel CM1216−06MR CM1216−08MR 4000/Tape & Reel 4000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 3 1 Publication Order Number: CM1216/D CM1216 PACKAGE / PINOUT DIAGRAMS Top View Top View Top View CH1 CH2 VN CH3 8−Pin SOIC−8 1 2 3 4 8 7 6 5 CH1 CH2 CH3 CH4 VN CH6 VP CH5 CH4 1 2 3 4 5 E168 CH6 VP CH5 CH4 8 7 6 5 E166 1 2 3 4 E166 CH1 CH2 VN CH3 10 9 8 7 6 CH8 CH7 VP CH6 CH5 10−Pin MSOP−10 8−Pin MSOP−8 Table 1. PIN DESCRIPTIONS Pin Name Type Description 1 I/O ESD Channel 2 2 I/O ESD Channel 4 4 3 I/O ESD Channel 5 5 4 I/O ESD Channel VN 3 3 5 GND Negative voltage supply rail CH5 6 6 6 I/O ESD Channel CH6 8 8 7 I/O ESD Channel VP 7 7 8 PWR Positive voltage supply rail CH7 − − 9 I/O ESD Channel CH8 − − 10 I/O ESD Channel MSOP−8 SOIC−8 MSOP−10 Pin No. Pin No. Pin No. CH1 1 1 CH2 2 CH3 CH4 SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Supply Voltage (VP−VN) 6 V Diode Forward DC Current 20 mA (VN−0.5) to (VP+0.5) V DC Voltage at any Channel Input Operating Temperature Range Ambient Junction −40 to +85 −40 to +125 Storage Temperature Range −40 to +150 °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Temperature Range (Ambient) Package Power Rating MSOP8 Package (CM1216−06MR) SOIC8 Package (CM1216−06SM) MSOP10 Package (CM1216−08MR) Rating Units −40 to +85 °C 400 600 400 http://onsemi.com 2 mW CM1216 Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol Parameter Conditions VP Operating Supply Voltage (VP−VN) IP Operating Supply Current (VP−VN) = 3.3 V VF Diode Forward Voltage Top Diode Bottom Diode IF = 20 mA; TA = 25°C Channel Leakage Current Channel Input Capacitance ILEAK CIN DCIN CMUTUAL VESD VCL RDYN Min 0.6 0.6 Typ Max Units 3.3 5.5 V 8 mA V 0.8 0.8 0.95 0.95 TA = 25°C; VP = 5 V, VN = 0 V ±0.1 ±1.0 mA At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V (Note 2) 1.6 2.0 pF Channel Input Capacitance Matching Mutual Capacitance (VP−VN) = 3.3 V ESD Protection Peak Discharge Voltage at any channel input, in system, contact discharge per IEC 61000−4−2 standard TA = 25°C (Notes 2 and 3) Channel Clamp Voltage Positive Transients Negative Transients IPP = 1 A, tP = 8/20 mS; TA = 25°C Dynamic Resistance Positive transients Negative transients IPP = 1 A, tP = 8/20 mS; TA = 25°C 0.04 pF 0.13 pF kV ±15 +9.0 −1.5 0.6 0.4 1. All parameters specified at TA = −40°C to +85°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded. 3. From I/O pins to VP or VN only. VP bypassed to VN with low ESR 0.2 mF ceramic capacitor. PERFORMANCE CHARACTERISTICS Figure 1. Typical Variation of CIN vs. VIN (f = 1 MHz, VP= 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, TA = 255C) http://onsemi.com 3 V W CM1216 APPLICATION INFORMATION Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. The CM1213 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 μF ceramic chip capacitor be connected between VP and the ground plane. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section. L1 POSITIVE SUPPLY PATH OF ESD CURRENT PULSE (IESD) LINE BEING PROTECTED D1 C1 ONE CHANNEL D2 SYSTEM OR CIRCUITRY BEING PROTECTED CHANNEL INPUT GROUND RAIL CHASSIS GROUND Figure 2. Application of Positive ESD Pulse between Input Channel and Ground http://onsemi.com 4 CM1216 PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC−01 ISSUE B 2X D E1 2X 0.10 C D EXPOSED PAD 5 ÉÉ ÉÉ 1 PIN ONE LOCATION DETAIL A D A 8 5 F 8 G E h 2X 4 4 0.20 C e 1 BOTTOM VIEW 8X b 0.25 C A-B D B A 0.10 C A2 8X A SEATING PLANE SIDE VIEW A1 b1 L 0.25 (L1) DETAIL A q SOLDERING FOOTPRINT* 2.72 0.107 1.52 0.060 7.0 0.275 2.03 0.08 0.6 0.024 ÉÉ ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ c H GAUGE PLANE 0.10 C A END VIEW TOP VIEW C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. 0.10 C A-B Exposed Pad 4.0 0.155 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 c1 (b) SECTION A−A DIM A A1 A2 b b1 c c1 D E E1 e L L1 F G h q MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_ CM1216 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O SYMBOL MIN NOM MAX 1.10 A E A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 E1 0.65 BSC e L 0.60 0.40 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 6 CM1216 PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE−01 ISSUE O SYMBOL MIN NOM 1.10 A E E1 MAX A1 0.00 0.05 0.15 A2 0.75 0.85 0.95 b 0.17 0.27 0.23 c 0.13 D 2.90 3.00 3.10 E 4.75 4.90 5.05 E1 2.90 3.00 3.10 0.50 BSC e L 0.40 L1 0.80 0.25 BSC L2 θ 0.60 0.95 REF 0º 8º DETAIL A TOP VIEW D A END VIEW A2 A1 c e b q SIDE VIEW L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A FireWire is a registered trademark of Apple Computer. Inc. iLink is a trademark of S. J. Electro Systems, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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