MC74HC164B D

MC74HC164B
8-Bit Serial-Input/ParallelOutput Shift Register
High−Performance Silicon−Gate CMOS
The MC74HC164B is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The MC74HC164B is an 8−bit, serial−input to parallel−output shift
register. Two serial data inputs, A1 and A2, are provided so that one
input may be used as a data enable. Data is entered on each rising edge
of the clock. The active−low asynchronous Reset overrides the Clock
and Serial Data inputs. Schmitt−trigger action at the Clock input
enhances the device’s tolerance to slower rise and fall times and
immunity to noise of the input clock signal.
www.onsemi.com
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
14
1
1
Features
•
•
•
•
•
•
•
•
•
HC164BG
AWLYWW
14
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 V to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7 A Requirements
Chip Complexity: 244 FETs or 61 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
14
1
HC
164B
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
A
L, WL
Y
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 2
1
Publication Order Number:
MC74HC164B/D
MC74HC164B
PIN ASSIGNMENT
A1
1
14
LOGIC DIAGRAM
VCC
SERIAL
DATA
INPUTS
A1
3
1
DATA
2
4
A2
2
13
QH
QA
3
12
QG
6
QB
4
11
QF
10
QC
5
10
QE
11
QD
6
9
RESET
GND
7
8
CLOCK
A2
5
CLOCK
RESET
8
12
13
9
QA
QB
QC
QD
QE
PARALLEL
DATA
OUTPUTS
QF
QG
QH
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
Outputs
Reset Clock A1 A2 QA QB
L
H
H
H
X
X
X
H
D
X
X
D
H
… QH
L … L
No Change
D QAn … QGn
D QAn … QGn
L
D = data input
QAn − QGn = data shifted from the preceding
stage on a rising edge at the clock input.
ORDERING INFORMATION
Device
Package
MC74HC164BDG
MC74HC164BDR2G
55 Units / Rail
SOIC−14
(Pb−Free)
NLV74HC164BDR2G*
MC74HC164BDTR2G
NLV74HC164BDTR2G*
Shipping†
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
www.onsemi.com
2
MC74HC164B
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
_C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to
GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
No Limit
No Limit
No Limit
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
www.onsemi.com
3
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC164B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
−55_C to
25_C
v 85_C
v 125_C
Unit
Vout = 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
V
Minimum Positive−Going Input
Threshold Voltage
(Figure 3)
Vout = 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.0
1.5
2.3
3.0
0.95
1.45
2.25
2.95
0.95
1.45
2.25
2.95
V
VT−
max
Maximum Negative−Going Input
Threshold Voltage
(Figure 3)
Vout = VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.9
1.4
2.0
2.6
0.95
1.45
2.05
2.65
0.95
1.45
2.05
2.65
V
VT− min
Minimum Negative−Going Input
Threshold Voltage
(Figure 3)
Vout = VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
V
VHmax
(Note 1)
Maximum Hysteresis Voltage
(Figure 3)
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
V
VHmin
(Note 1)
Minimum Hysteresis Voltage
(Figure 3)
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Symbol
Parameter
VT+
max
Maximum Positive−Going Input
Threshold Voltage
(Figure 3)
VT+ min
VOH
Minimum High−Level Output
Voltage
Test Conditions
Vin = VIH or VIL
|Iout| v 20 mA
Vin = VIH or VIL
VOL
Maximum Low−Level Output
Voltage
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
Vin = VIH or VIL
|Iout| v 20 mA
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4
40
160
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. VHmin > (VT+ min) − (VT− max); VHmax = (VT+ max) − (VT− min).
www.onsemi.com
4
MC74HC164B
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
−55_C to
25_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
20
40
50
10
20
35
45
10
20
30
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
160
100
32
27
200
150
40
34
250
200
48
42
ns
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
175
100
35
30
220
150
44
37
260
200
53
45
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
180
Power Dissipation Capacitance (Per Package)*
pF
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
−55_C to
25_C
v 85_C
v 125_C
Unit
tsu
Minimum Setup Time, A1 or A2 to Clock
(Figure 3)
2.0
3.0
4.5
6.0
25
15
7
5
35
20
8
6
40
25
9
6
ns
th
Minimum Hold Time, Clock to A1 or A2
(Figure 3)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
www.onsemi.com
5
MC74HC164B
PIN DESCRIPTIONS
INPUTS
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a data−enable input. When only one serial input is
used, the other must be connected to VCC.
OUTPUTS
Clock (Pin 8)
Reset (Pin 9)
Shift Register Clock. A positive−going transition on this
pin shifts the data at each stage to the next stage. The shift
Active−Low, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flip−flops and sets
Outputs QA − QH to the low level state.
QA − QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
SWITCHING WAVEFORMS
tr
tw
tf
VCC
90%
50%
10%
CLOCK
50%
GND
GND
tPHL
tw
1/fmax
tPLH
Q
VCC
RESET
Q
50%
tPHL
90%
50%
10%
trec
VCC
CLOCK
50%
tTHL
tTLH
GND
Figure 2.
Figure 1.
TEST POINT
OUTPUT
VALID
VCC
A1 OR A2
DEVICE
UNDER
TEST
50%
GND
tsu
CL*
th
VCC
CLOCK
50%
GND
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
www.onsemi.com
6
MC74HC164B
EXPANDED LOGIC DIAGRAM
CLOCK
A1
8
1
2
D
D
Q
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
A2
R
R
RESET
R
R
R
R
R
R
9
3
QA
4
5
QB
6
QC
10
QD
TIMING DIAGRAM
CLOCK
A1
A2
RESET
QA
QB
QC
QD
QE
QF
QG
QH
www.onsemi.com
7
11
QE
QF
12
QG
13
QH
MC74HC164B
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
8
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC164B
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
DETAIL A
h
A
X 45 _
M
A1
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74HC164B/D