SN74LS164 Serial-In Parallel-Out Shift Register The SN74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. • • • • • • http://onsemi.com LOW POWER SCHOTTKY Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 14 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS164N 14 Pin DIP 2000 Units/Box SN74LS164D 14 Pin 2500/Tape & Reel Publication Order Number: SN74LS164/D SN74LS164 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 Q6 Q5 Q4 MR CP 14 13 12 11 10 9 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 7 GND LOADING (Note a) PIN NAMES A, B CP MR Q0 – Q7 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 1 2 8 A LS164 B 8-BIT SHIFT REGISTER CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 3 4 5 6 10 11 12 13 VCC = PIN 14 GND = PIN 7 http://onsemi.com 2 HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. SN74LS164 LOGIC DIAGRAM 1 2 A D Q D CD 8 9 D Q Q D Q D Q D Q D Q D Q B CD CD CD CD CD CD CD CP MR VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q0 Q1 3 4 Q2 Q3 Q4 Q5 Q6 Q7 5 6 10 11 12 13 FUNCTIONAL DESCRIPTION Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A•B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH, or both inputs connected together. MODE SELECT — TRUTH TABLE OPERATING MODE Reset (Clear) Shift INPUTS OUTPUTS MR A B Q0 Q1–Q7 L X X L L–L H H H H I I h h I h I h L L L H q0 – q6 q0 – q6 q0 – q6 q0 – q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition. http://onsemi.com 3 SN74LS164 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Min Typ Max – 0.65 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs 0.8 V Guaranteed Input LOW Voltage for All Inputs – 1.5 V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 2.0 2.7 Unit 3.5 VCC = VCC MIN, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 20 – 0.4 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 27 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 36 Max Unit fMAX Maximum Clock Frequency tPHL Propagation Delay MR to Output Q 24 36 ns tPLH tPHL Propagation Delay Clock to Output Q 17 21 27 32 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW CP, MR Pulse Width 20 ns ts Data Setup Time 15 ns th Data Hold Time 5.0 ns trec MR to Clock Recovery Time 20 ns http://onsemi.com 4 Test Conditions 0V VCC = 5 5.0 SN74LS164 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance. I/f max 1.3 V MR tW 1.3 V CP trec tW tPLH tPHL Q 1.3 V 1.3 V 1.3 V 1.3 V CP 1.3 V 1.3 V tPHL CONDITIONS: MR = H Q Figure 1. Clock to Output Delays and Clock Pulse Width 1.3 V Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time 1/fmax tW 1.3 V CP ts(H) D * 1.3 V 1.3 V th(H) 1.3 V ts(L) 1.3 V 1.3 V Q 1.3 V th(L) 1.3 V 1.3 V Figure 3. Data Setup and Hold Times http://onsemi.com 5 1.3 V SN74LS164 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 646–06 ISSUE M 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F L N C –T– SEATING PLANE J K H G D 14 PL 0.13 (0.005) M M http://onsemi.com 6 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 ––– 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 ––– 10_ 0.38 1.01 SN74LS164 D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G M B M R X 45 _ C F –T– SEATING PLANE D 14 PL 0.25 (0.010) M T B J M K S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SN74LS164 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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