MC14099B
8-Bit Addressable Latches
The MC14099B is an 8−bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip
Enable.
A Master Reset capability is available on both parts.
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Features
•
•
•
•
•
•
•
•
SOIC−16 WD
DW SUFFIX
CASE 751G
Serial Data Input
Parallel Output
Master Reset
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load over the Rated Temperature
Range
MC14099B pin for pin compatible with CD4099B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
PIN ASSIGNMENT
MAXIMUM RATINGS (Voltages Referenced to VSS)
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Symbol
VDD
Vin, Vout
Iin, Iout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
Q7
1
16
VDD
RESE
T
DATA
WRITE
DISABLE
A0
2
15
Q6
3
14
Q5
4
13
Q4
5
12
Q3
A1
6
11
Q2
A2
7
10
Q1
VSS
8
9
Q0
MARKING DIAGRAM
16
14099BG
AWLYYWW
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9
1
Publication Order Number:
MC14099B/D
MC14099B
MC14099B
4
3
WRITE DISABLE
DATA
A0
A1
A2
RESET
5
6
DECODER
7
8
2
9
10
11
12
8
13
LATCHES 14
15
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VDD = 16
VSS = 8
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C
25_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
125_C
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance (Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Input Capacitance
MC14599B — Data (pin 3)
(Vin = 0)
Cin
−
−
−
−
15
22.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (1.5 mA/kHz) f + IDD
IT = (3.0 mA/kHz) f + IDD
IT = (4.5 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
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2
MC14099B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
5.0
10
15
−
−
−
200
75
50
400
150
100
Write Disable to Output Q
5.0
10
15
−
−
−
200
80
60
400
160
120
ns
Reset to Output Q
5.0
10
15
−
−
−
175
80
65
350
160
130
ns
CE to Output Q (MC14599B only)
5.0
10
15
−
−
−
225
100
75
450
200
150
ns
5.0
10
15
−
−
−
200
80
65
400
160
130
5.0
10
15
−
−
−
200
90
75
400
180
150
5.0
10
15
150
75
50
75
40
25
−
−
−
5.0
10
15
320
160
120
160
80
60
−
−
−
5.0
10
15
100
50
35
50
25
20
−
−
−
5.0
10
15
150
75
50
75
40
25
−
−
−
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
tTLH,
tTHL
Propagation Delay Time
Data to Output Q
tPHL,
tPLH
Propagation Delay Time, MC14599B only
Chip Enable, Write/Read to Data
tPHL,
tPLH
Address to Data
Pulse Widths
Reset
tw(H)
tw(L)
Write Disable
Unit
ns
ns
ns
ns
ns
ns
Set Up Time
Data to Write Disable
tsu
ns
Hold Time
Write Disable to Data
th
Set Up Time
Address to Write Disable
tsu
5.0
10
15
100
80
40
45
30
10
−
−
−
ns
Removal Time
Write Disable to Address
trem
5.0
10
15
0
0
0
– 80
– 40
– 40
−
−
−
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
MC14099B
FUNCTION DIAGRAM
RESET 2
9Q0
DATA 3
WRITE
4
DISABLE
EACH LATCH
TO
OTHER
LATCHES
ZERO
SELECT
10Q1
A0 5
11Q2
12Q3
ADDRESS
DECODER
A1 6
OTHER LATCHES
13Q4
14Q5
15Q6
A2 7
(M.S.B.)
1Q7
TRUTH TABLE
Write
Disable
Reset
Addressed
Latch
Unaddressed
Latches
0
0
Data
Qn*
0
1
Data
Reset {
1
0
Qn*
Qn*
1
1
Reset
Reset
CAUTION: To avoid unintentional data changes in the latches, Write
Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
*Qn is previous state of latch.
†Reset to zero state.
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4
MC14099B
SWITCHING WAVEFORMS
VDD
DATA OR
WRITE DISABLE
50%
VSS
tPHL
tPLH
90%
50%
10%
OUTPUT Q
tTHL
tTLH
tw(H)
VDD
RESET
50%
VSS
tPHL
OUTPUT Q
VDD
ADDRESS
50%
VSS
tw(L)
tsu
trem
VDD
WRITE
DISABLE
50%
VSS
tsu
th
VDD
DATA
50%
VSS
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5
MC14099B
ORDERING INFORMATION
Package
Shipping†
MC14099BDWG
SOIC−16 WB
(Pb−Free)
47 Units / Rail
MC14099BDWR2G
SOIC−16 WB
(Pb−Free)
1000 Units / Tape & Reel
NLV14099BDWR2G*
SOIC−16 WB
(Pb−Free)
1000 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
MC14099B
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G−03
ISSUE D
A
D
9
1
8
h X 45 _
H
E
0.25
8X
M
B
M
16
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
q
16X
M
B
B
T A
S
B
S
L
A
0.25
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
14X
C
A1
e
T
SEATING
PLANE
SOLDERING FOOTPRINT*
0.58
16X
11.00
1
16X
1.27
PITCH
1.62
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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For additional information, please contact your local
Sales Representative
MC14099B/D