MC14518B Dual Up Counters The MC14518B dual BCD counter and the MC14520B dual binary counter are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4–stage counters. The counter stages are type D flip–flops, with interchangeable Clock and Enable lines for incrementing on either the positive–going or negative–going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC14518B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi–stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. • • • • • http://onsemi.com MARKING DIAGRAMS 16 PDIP–16 P SUFFIX CASE 648 MC14518BCP AWLYYWW 1 Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Internal and External Speeds Logic Edge–Clocked Design — Incremented on Positive Transition of Clock or Negative Transition on Enable Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range 16 14518B SOIC–16 DW SUFFIX CASE 751G AWLYYWW 1 16 SOEIAJ–16 F SUFFIX CASE 966 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol Value Unit – 0.5 to +18.0 V – 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 3.) 500 mW TA Operating Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C VDD Vin, Vout Iin, Iout Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device Package Shipping MC14518BCP PDIP–16 2000/Box MC14518BDW SOIC–16 47/Rail MC14518BDWR2 SOIC–16 1000/Tape & Reel MC14518BF SOEIAJ–16 See Note 1. MC14518BFEL SOEIAJ–16 See Note 1. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. v Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 MC14518B AWLYWW 1 Publication Order Number: MC14518B/D MC14518B PIN ASSIGNMENT CA 1 16 VDD EA 2 15 RB Q0A 3 14 Q3B Q1A 4 13 Q2B Q2A 5 12 Q1B Q3A 6 11 Q0B RA 7 10 EB VSS 8 9 CB BLOCK DIAGRAM CLOCK 1 Q0 Q1 Q2 C 2 ENABLE R 3 4 Q3 5 6 Q0 11 Q1 Q2 Q3 12 7 CLOCK 9 C 10 ENABLE R 13 14 15 VDD = PIN 16 VSS = PIN 8 TRUTH TABLE Clock Enable Reset Action 1 0 Increment Counter 0 Increment Counter 0 No Change 0 No Change 0 No Change 0 No Change 1 Q0 thru Q3 = 0 0 X X 0 1 X X X = Don’t Care http://onsemi.com 2 MC14518B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ (4.) Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (0.6 µA/kHz) f + IDD IT = (1.2 µA/kHz) f + IDD IT = (1.7 µA/kHz) f + IDD 4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002. http://onsemi.com 3 µAdc MC14518B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q/Enable to Q tPLH, tPHL = (1.7 ns/pF) CL + 215 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL Reset to Q tPHL = (1.7 ns/pF) CL + 265 ns tPHL = (0.66 ns/pF) CL + 117 ns tPHL = (0.66 ns/pF) CL + 95 ns tPHL VDD Min Typ (8.) Max 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns 5.0 10 15 — — — 280 115 80 560 230 160 5.0 10 15 — — — 330 130 90 650 230 170 tw(H) tw(L) 5.0 10 15 200 100 70 100 50 35 — — — ns fcl 5.0 10 15 — — — 2.5 6.0 8.0 1.5 3.0 4.0 MHz tTHL, tTLH 5.0 10 15 — — — — — — 15 5 4 µs Enable Pulse Width tWH(E) 5.0 10 15 440 200 140 220 100 70 — — — ns Reset Pulse Width tWH(R) 5.0 10 15 280 120 90 125 55 40 — — — ns trem 5.0 10 15 –5 15 20 – 45 – 15 –5 — — — ns Clock Pulse Width Clock Pulse Frequency Clock or Enable Rise and Fall Time Reset Removal Time ns 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD 500 µF PULSE GENERATOR ID 0.01 µF CERAMIC C Q0 Q1 Q2 E Q3 R CL CL CL CL VSS 20 ns 20 ns 50% 90% 10% VARIABLE WIDTH VSS Figure 1. Power Dissipation Test Circuit and Waveform http://onsemi.com 4 MC14518B 20 ns VDD PULSE GENERATOR C 20 ns 90% 50% 10% CLOCK INPUT Q0 tWH Q1 E R Q2 Q3 CL CL VSS CL 50% 10% Q tf Figure 2. Switching Time Test Circuit and Waveforms 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 0 1 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 CLOCK ENABLE RESET 2 3 4 5 Q0 Q1 Q2 Q3 Q0 MC14520B tPHL 90% tr MC14518B VSS tWL tPLH CL VDD Q1 Q2 Q3 Figure 3. Timing Diagram http://onsemi.com 5 4 MC14518B Q0 D C R Q1 Q D Q C R Q2 Q D Q C R Q3 Q D Q C Q R Q RESET ENABLE CLOCK Figure 4. Decade Counter (MC14518B) Logic Diagram (1/2 of Device Shown) Q0 D C R Q1 Q D Q C R Q2 Q D Q C R Q D Q C RESET ENABLE CLOCK Figure 5. Binary Counter (MC14520B) Logic Diagram (1/2 of Device Shown) http://onsemi.com 6 Q3 Q R Q MC14518B PACKAGE DIMENSIONS PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC–16 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–03 ISSUE B A D 9 1 8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. h X 45 _ E 0.25 16X M T A S B S 14X e L A 0.25 B B A1 H 8X M B M 16 q SEATING PLANE T DIM A A1 B C D E e H h L q C http://onsemi.com 7 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC14518B PACKAGE DIMENSIONS SOEIAJ–16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966–01 ISSUE O 16 LE 9 Q1 M_ E HE 1 L 8 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX ––– 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 ––– 0.78 INCHES MIN MAX ––– 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 ––– 0.031 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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