MC74LCX16373 D

MC74LCX16373
Low-Voltage CMOS 16-Bit
Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX16373 is a high performance, non−inverting 16−bit
transparent latch operating from a 2.3 V to 3.6 V supply. The device is
byte controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16−bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX16373 inputs to be safely driven from 5.0 V devices.
The MC74LCX16373 contains 16 D−type latches with 3−state
5.0 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state outputs are controlled by the Output
Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When
OE is HIGH, the standard outputs are in the high impedance state, but
this does not interfere with new data entering into the latches.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Designed for 2.3 to 3.6 V VCC Operation
5.4 ns Maximum tpd
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance:
♦ Human Body Model >2000 V
♦ Machine Model >200 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. 11
1
http://onsemi.com
48
1
TSSOP−48
DT SUFFIX
CASE 1201
MARKING DIAGRAM
48
LCX16373G
AWLYYWW
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
MC74LCX16373/D
MC74LCX16373
1
OE1 1
48 LE1
O0 2
47 D0
O1 3
46 D1
GND 4
44 D2
O3 6
43 D3
VCC 7
42 VCC
O4 8
41 D4
O5 9
40 D5
48
O6 11
38 D6
O7 12
37 D7
O8 13
36 D8
O9 14
35 D9
GND 15
47
33 D10
O11 17
32 D11
VCC 18
31 VCC
O12 19
30 D12
2
D1
D2
D5
29 D13
28 GND
O14 22
27 D14
O15 23
26 D15
OE2 24
25 LE2
O5
Q
D6
O7
Q
D7
26
D15
D
22
O14
Q
D
12
nLE
37
O13
Q
27
D14
D
20
nLE
nLE
O6
Q
O12
D
11
nLE
38
29
D13
D
19
Q
D
9
nLE
40
O11
Q
30
D12
D
17
nLE
nLE
O4
Q
O10
Q
D
8
nLE
41
32
D11
D
D4
O13 20
O3
Q
16
nLE
D
6
nLE
D3
33
D10
D
43
GND 21
O2
Q
O9
Q
D
5
nLE
44
35
D9
D
14
nLE
O1
Q
O8
Q
D
3
nLE
46
36
D8
D
13
nLE
O0
Q
D0
34 GND
O10 16
25
LE2
nLE
39 GND
GND 10
OE2
LE1
45 GND
O2 5
24
OE1
23
nLE
O15
Q
D
Figure 2. Logic Diagram
Figure 1. Pinout: 48−Lead
(Top View)
Table 1. PIN NAMES
Pins
Function
OEn
Output Enable Inputs
LEn
Latch Enable Inputs
D0−D15
Inputs
O0−O15
Outputs
Outputs
Inputs
TRUTH TABLE
Inputs
Outputs
LE1
OE1
D0:7
O0:7
LE2
OE2
D8:15
O8:15
X
H
X
Z
X
H
X
Z
H
L
L
L
H
L
L
L
H
L
H
H
H
L
H
H
L
L
X
O0
L
L
X
O0
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs
http://onsemi.com
2
MC74LCX16373
ORDERING INFORMATION
Package
Shipping†
MC74LCX16373DTG
TSSOP−48
(Pb−Free)
39 Units / Rail
M74LCX16373DTR2G
TSSOP−48
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
Condition
Units
−0.5 to +7.0
V
−0.5 ≤ VI ≤ +7.0
V
−0.5 ≤ VO ≤ +7.0
Output in 3−State
V
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State. (Note 1)
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
MSL
Moisture Sensitivity
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
Operating
Data Retention Only
Min
Typ
Max
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
VI
Input Voltage
0
5.5
VO
Output Voltage
(HIGH or LOW State)
(3−State)
0
0
VCC
5.5
IOH
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
−24
−12
−8
IOL
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
+24
+12
+8
TA
Operating Free−Air Temperature
Dt/DV
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
http://onsemi.com
3
Units
V
V
V
mA
mA
−55
+125
°C
0
10
ns/V
MC74LCX16373
DC ELECTRICAL CHARACTERISTICS
TA = −55°C to +125°C
Symbol
VIH
VIL
VOH
VOL
Condition
Min
2.3 V ≤ VCC ≤ 2.7 V
1.7
2.7 V ≤ VCC ≤ 3.6 V
2.0
Characteristic
HIGH Level Input Voltage (Note 2)
LOW Level Input Voltage (Note 2)
HIGH Level Output Voltage
LOW Level Output Voltage
IOZ
3−State Output Current
IOFF
Power Off Leakage Current
Max
V
2.3 V ≤ VCC ≤ 2.7 V
0.7
2.7 V ≤ VCC ≤ 3.6 V
0.8
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
VCC − 0.2
VCC = 2.3 V; IOH = −8 mA
1.8
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
Units
V
V
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
0.2
V
VCC = 2.3 V; IOL = 8 mA
0.6
VCC = 2.7 V; IOL = 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
VCC = 3.6 V, VIN = VIH or VIL,
VOUT = 0 to 5.5 V
±5
mA
VCC = 0, VIN = 5.5 V or VOUT = 5.5 V
10
mA
IIN
Input Leakage Current
VCC = 3.6 V, VIN = 5.5 V or GND
±5
mA
ICC
Quiescent Supply Current
VCC = 3.6 V, VIN = 5.5 V or GND
20
mA
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
500
mA
DICC
Increase in ICC per Input
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W)
TA = −55°C to +125°C
VCC = 3.3 V ± 0.3 V
CL = 50 pF
Symbol
Parameter
VCC = 2.7 V
CL = 50 pF
VCC = 2.5 V ± 0.2 V
CL = 30 pF
Waveform
Min
Max
Min
Max
Min
Max
Units
tPLH
tPHL
Propagation Delay
Dn to On
1
1.5
1.5
5.4
5.4
1.5
1.5
5.9
5.9
1.5
1.5
6.5
6.5
ns
tPLH
tPHL
Propagation Delay
LE to On
3
1.5
1.5
5.5
5.5
1.5
1.5
6.4
6.4
1.5
1.5
6.6
6.6
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
1.5
6.1
6.1
1.5
1.5
6.5
6.5
1.5
1.5
7.9
7.9
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
6.0
6.0
1.5
1.5
6.3
6.3
1.5
1.5
7.2
7.2
ns
ts
Setup Time, HIGH or LOW Dn to
LE
3
2.5
2.5
3.0
ns
th
Hold Time, HIGH or LOW Dn to LE
3
1.5
1.5
2.0
ns
tw
LE Pulse Width, HIGH
3
3.0
3.0
3.5
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
http://onsemi.com
4
MC74LCX16373
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Min
Condition
Typ
Max
Units
VOLP
Dynamic LOW Peak Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV
Dynamic LOW Valley Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Condition
Typical
Units
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
8
pF
CPD
Power Dissipation Capacitance
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
20
pF
CIN
Parameter
VCC
Vmi
Vmi
Dn
tPHL
tPLH
0V
VOH
Vmo
On
Vmo
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
OEn
VCC
Dn
Vmi
Vmi
tPZH
tPHZ
ts
th
VCC
LEn
Vmo
tw
Vmo
0V
tPZL
On
VOH
VHZ
Vmo
On
0V
0V
tPLH, tPHL
tPLZ
VOH
Vmo
VLZ
VOL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
On
Vmo
VOL
WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted
Figure 3. AC Waveforms
Table 2. AC WAVEFORMS
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
2.5 V ± 0.2 V
Vmi
1.5 V
1.5 V
VCC / 2
Vmo
1.5 V
1.5 V
VCC / 2
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
http://onsemi.com
5
MC74LCX16373
VCC
PULSE
GENERATOR
R1
DUT
RT
CL
RL
Figure 4. Test Circuit
Table 3. TEST CIRCUIT
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 ± 0.3 V
6 V at VCC = 2.5 ± 0.2 V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
GND
CL =
CL =
RL =
RT =
50 pF at VCC = 3.3 ± 0.3 V or equivalent (includes jig and probe capacitance)
30 pF at VCC = 2.5 ± 0.2 V or equivalent (includes jig and probe capacitance)
R1 = 500 W or equivalent
ZOUT of pulse generator (typically 50 W)
http://onsemi.com
6
6 V or VCC × 2
OPEN
GND
MC74LCX16373
PACKAGE DIMENSIONS
48X
TSSOP−48
DT SUFFIX
CASE 1201−01
ISSUE B
K REF
0.12 (0.005)
T U
S
V
K
K1
T U
J J1
25
0.254 (0.010)
M
48
SECTION N−N
B
−U−
L
1
N
24
A
−V−
PIN 1
IDENT.
DETAIL E
D
0.076 (0.003)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
N
F
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
S
S
M
C
M
0.25 (0.010)
−W−
DETAIL E
H
G
MILLIMETERS
MIN
MAX
12.40
12.60
6.00
6.20
−−−
1.10
0.05
0.15
0.50
0.75
0.50 BSC
0.37
−−−
0.09
0.20
0.09
0.16
0.17
0.27
0.17
0.23
7.95
8.25
0_
8_
INCHES
MIN
MAX
0.488
0.496
0.236
0.244
−−−
0.043
0.002
0.006
0.020
0.030
0.0197 BSC
0.015
−−−
0.004
0.008
0.004
0.006
0.007
0.011
0.007
0.009
0.313
0.325
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT
48X
48X
0.32
1.00
8.45
1
0.50
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74LCX16373/D