74VCXH16373 Low−Voltage 1.8/2.5/3.3 V 16−Bit Transparent Latch With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74VCXH16373 is an advanced performance, non−inverting 16−bit transparent latch. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16373 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16−bit operation. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V. The 74VCXH16373 contains 16 D−type latches with 3−state 3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, (a latch output will change state each time its D input changes). When LE is LOW, the latch stores the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The data inputs include active bushold circuitry, eliminating the need for external pullup resistors to hold unused or floating inputs at a valid logic state. http://onsemi.com TSSOP−48 DT SUFFIX CASE 1201 48 1 MARKING DIAGRAM 48 VCXH16373 AWLYYWW 1 A WL YY WW Features PIN NAMES • Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V • • • • • • • • 3.9 ns max for 2.3 V to 2.7 V 6.8 ns max for 1.65 V to 1.95 V Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal Includes Active Bushold to Hold Unused or Floating Inputs at a Valid Logic State IOFF Specification Guarantees High Impedance When VCC = 0 V* Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V Machine Model >200 V Pb−Free Package is Available** *To ensure the outputs activate in the 3−state condition, the output enable pins should be connected to VCC through a pull−up resistor. The value of the resistor is determined by the current sinking capability of the output connected to the OE pin. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 = Assembly Location = Wafer Lot = Year = Work Week 1 Pins Function OEn LEn D0−D15 O0−O15 Output Enable Inputs Latch Enable Inputs Inputs Outputs ORDERING INFORMATION Package Shipping † 74VCXH16373DT TSSOP 39 / Rail 74VCXH16373DTR TSSOP 2500/Tape & Reel Device 74VCXH16373DTRG TSSOP 2500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. **For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Publication Order Number: 74VCXH16373/D 74VCXH16373 OE1 1 48 LE1 O0 2 O1 3 47 D0 46 D1 GND 4 O2 5 45 GND 44 D2 O3 6 43 D3 VCC 7 O4 8 42 VCC 41 D4 O5 9 GND 10 40 D5 39 GND O6 11 O7 12 38 D6 O8 13 36 D8 O9 14 GND 15 OE1 LE1 D0 D1 D2 37 D7 D3 35 D9 34 GND O10 16 O11 17 33 D10 32 D11 VCC 18 31 VCC O12 19 O13 20 30 D12 29 D13 GND 21 O14 22 28 GND 27 D14 O15 23 OE2 24 26 D15 25 LE2 D4 D5 D6 D7 1 OE2 48 LE2 nLE 47 D nLE 46 D nLE 44 D nLE 43 D nLE 41 D nLE 40 D nLE 38 D nLE 37 D 2 Q 3 Q 5 Q 6 Q 8 Q 9 Q 11 Q 12 Q Figure 1. 48−Lead Pinout (Top View) O0 D8 O1 D9 O2 D10 O3 D11 O4 D12 O5 D13 O6 D14 O7 D15 24 25 36 35 33 32 30 29 27 26 nLE D nLE D nLE D nLE D nLE D nLE D nLE D nLE D Figure 2. Logic Diagram OE1 1 LE1 48 25 LE2 24 OE2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 EN1 EN2 EN3 EN4 1 1∇ 1 2∇ 1 3∇ 1 4∇ 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 Figure 3. IEC Logic Diagram http://onsemi.com 2 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 Q Q Q Q Q Q Q Q 13 14 16 17 19 20 22 23 O8 O9 O10 O11 O12 O13 O14 O15 74VCXH16373 TRUTH TABLE Inputs Outputs Inputs Outputs LE1 OE1 D0:7 O0:7 LE2 OE2 D8:15 O8:15 X H X Z X H X Z H L L L H L L L H L H H H L H H L L X O0 L L X O0 H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs. O0 = No Change. ABSOLUTE MAXIMUM RATINGS Symbol Parameter VCC DC Supply Voltage VI VO Value Condition Unit −0.5 to +4.6 V DC Input Voltage −0.5 ≤ VI ≤ +4.6 V DC Output Voltage −0.5 ≤ VO ≤ +4.6 Output in 3−State V −0.5 ≤ VO ≤ VCC + 0.5 Note 1; Outputs Active V −50 VI < GND mA −50 VO < GND mA +50 VO > VCC mA IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit 1.65 1.2 3.3 3.3 3.6 3.6 V −0.3 3.6 V 0 0 VCC 3.6 V HIGH Level Output Current, VCC = 3.0 V − 3.6 V −24 mA IOL LOW Level Output Current, VCC = 3.0 V − 3.6 V 24 mA IOH HIGH Level Output Current, VCC = 2.3 V − 2.7 V −18 mA IOL LOW Level Output Current, VCC = 2.3 V − 2.7 V 18 mA IOH HIGH Level Output Current, VCC = 1.65 V − 1.95 V −6 mA IOL LOW Level Output Current, VCC = 1.65 V − 1.95 V 6 mA TA Operating Free−Air Temperature −40 +85 °C Dt/DV Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH Operating Data Retention Only (Active State) (3−State) http://onsemi.com 3 74VCXH16373 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH VIL VOH VOL II Characteristic HIGH Level Input Voltage (Note 2) LOW Level Input Voltage (Note 2) HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current II(HOLD) II (OD) Minimum Bushold Input Current Minimum Bushold Over−Drive Current Needed to Change State IOZ 3−State Output Current IOFF Power−Off Leakage Current ICC DICC 2. 3. 4. 5. Quiescent Supply Current (Note 5) Increase in ICC per Input Condition Min 1.65 V ≤ VCC < 2.3 V 0.65 x VCC 2.3 V ≤ VCC ≤ 2.7 V 1.6 2.7 V < VCC ≤ 3.6 V 2.0 Max V 1.65 V ≤ VCC < 2.3 V 0.35 x VCC 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V < VCC ≤ 3.6 V 0.8 1.65 V ≤ VCC ≤ 3.6 V; IOH = −100 mA VCC − 0.2 VCC = 1.65 V; IOH = −6 mA 1.25 VCC = 2.3 V; IOH = −6 mA 2.0 VCC = 2.3 V; IOH = −12 mA 1.8 VCC = 2.3 V; IOH = −18 mA 1.7 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 0.2 VCC = 1.65 V; IOL = 6 mA 0.3 VCC = 2.3 V; IOL = 12 mA 0.4 VCC = 2.3 V; IOL = 18 mA 0.6 VCC = 2.7 V; IOL = 12 mA 0.4 VCC = 3.0 V; IOL = 18 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 ±5.0 VCC = 3.0 V, VIN = 0.8 V 75 VCC = 3.0 V, VIN = 2.0 V −75 VCC = 2.3 V, VIN = 0.7 V 45 VCC = 2.3 V, VIN = 1.6 V −45 VCC = 1.65 V, VIN = 0.57 V 25 VCC = 1.65 V, VIN = 1.07 V −25 VCC = 3.6 V, (Note 3) 450 VCC = 3.6 V, (Note 4) −450 VCC = 2.7 V, (Note 3) 300 VCC = 2.7 V, (Note 4) −300 VCC = 1.95 V, (Note 3) 200 VCC = 1.95 V, (Note 4) −200 V V 1.65 V ≤ VCC ≤ 3.6 V; IOL = 100 mA 1.65 V ≤ VCC ≤ 3.6 V; 0V ≤ VI ≤ 3.6 V Unit V mA mA mA 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 3.6 V; VI = VIH or VIL ±10 mA VCC = 0 V; VI or VO = 3.6 V 10 mA 1.65 V ≤ VCC ≤ 3.6 V; VI = GND or VCC 20 mA 1.65 V ≤ VCC ≤ 3.6 V; 3.6 V ≤ VI, VO ≤ 3.6 V ±20 mA 2.7 V < VCC ≤ 3.6 V; VIH = VCC − 0.6 V 750 mA These values of VI are used to test DC electrical characteristics only. An external driver must source at least the specified current to switch from LOW−to−HIGH. An external driver must source at least the specified current to switch from HIGH−to−LOW. Outputs disabled or 3−state only. http://onsemi.com 4 74VCXH16373 AC CHARACTERISTICS (Note 6; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W) TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol Parameter VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V Waveform Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay Dn−to−On 1 0.8 0.8 3.0 3.0 1.0 1.0 3.4 3.4 1.5 1.5 6.8 6.8 ns tPLH tPHL Propagation Delay LE−to−On 1 0.8 0.8 3.0 3.0 1.0 1.0 3.9 3.9 1.5 1.5 7.8 7.8 ns tPZH tPZL Output Enable Time to High and Low Level 2 0.8 0.8 3.5 3.5 1.0 1.0 4.6 4.6 1.5 1.5 9.2 9.2 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 0.8 0.8 3.5 3.5 1.0 1.0 3.8 3.8 1.5 1.5 6.8 6.8 ns ts Setup Time, High or Low Dn−to−LE 3 1.5 1.5 2.5 ns th Hold Time, High or Low Dn−to−LE 3 1.0 1.0 1.0 ns tw LE Pulse Width, High 3 1.5 1.5 4.0 ns tOSHL tOSLH Output−to−Output Skew (Note 7) 0.5 0.5 0.5 0.5 0.75 0.75 ns 6. For CL = 50 pF, add approximately 300 ps to the AC maximum specification. 7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 W) TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol Parameter Waveform Min Max VCC = 2.7 V Min Max Unit tPLH tPHL Propagation Delay Dn−to−On 4 1.0 1.0 3.6 3.6 4.3 4.3 ns tPLH tPHL Propagation Delay LE−to−On 4 1.0 1.0 3.9 3.9 4.6 4.6 ns tPZH tPZL Output Enable Time to High and Low Level 5 1.0 1.0 4.7 4.7 5.7 5.7 ns tPHZ tPLZ Output Disable Time From High and Low Level 5 1.0 1.0 4.1 4.1 4.5 4.5 ns tOSHL tOSLH Output−to−Output Skew (Note 8) 0.5 0.5 0.5 0.5 ns 8. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 5 74VCXH16373 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol VOLP VOLV VOHV Condition Typ Unit VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.25 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.6 VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.8 VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.25 VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.6 VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.8 VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V 1.5 VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V 1.9 VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V 2.2 Characteristic Dynamic LOW Peak Voltage (Note 9) Dynamic LOW Valley Voltage (Note 9) Dynamic HIGH Valley Voltage (Note 10) V V 9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. 10. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the HIGH state. CAPACITIVE CHARACTERISTICS Symbol Parameter CIN Input Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance Condition Typical Unit Note 11 6 pF Note 11 7 pF Note 11, 10 MHz 20 pF 11. VCC = 1.8 V, 2.5 V or 3.3 V; VI = 0 V or VCC. http://onsemi.com 6 74VCXH16373 VIH Vm Dn Vm 0V tPLH tPHL VOH On Vm Vm VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 4. AC Waveforms VIH Vm OEn VIH Dn Vm Vm Vm 0V tPZH On 0V ts tPHZ VIH VOH Vy LEn Vm tw Vm tPLH, tPHL tPLZ ≈ VCC On Vm 0V ≈ 0V tPZL th VOH On Vm Vm VOL Vx VOL WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 5. AC Waveforms Table 1. AC WAVEFORMS VCC Symbol 3.3 V ± 0.3 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V VIH 2.7 V VCC VCC Vm 1.5 V VCC/2 VCC/2 Vx VOL + 0.3 V VOL + 0.15 V VOL + 0.15 V Vy VOH − 0.3 V VOH − 0.15 V VOH − 0.15 V http://onsemi.com 7 74VCXH16373 VCC PULSE GENERATOR RL DUT RT CL RL Figure 6. Test Circuit Table 2. TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V; VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V tPZH, tPHZ GND CL = 30 pF or equivalent (Includes jig and probe capacitance) RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W) http://onsemi.com 8 6 V or VCC × 2 OPEN GND 74VCXH16373 VIH Vm Dn Vm 0V tPLH tPHL VOH On Vm Vm VOL WAVEFORM 4 − PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 7. AC Waveforms VIH Vm OEn VIH Dn Vm Vm Vm 0V tPZH On 0V ts tPHZ VIH VOH Vy LEn Vm tw Vm tPLH, tPHL tPLZ ≈ VCC On Vm 0V ≈0V tPZL th Vm WAVEFORM 5 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VOH On Vm VOL Vx VOL WAVEFORM 6 − LE to On PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn−to−LE SETUP AND HOLD TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted Figure 8. AC Waveforms Table 3. AC WAVEFORMS VCC Symbol 3.3 V ± 0.3 V 2.7 V VIH 2.7 V 2.7 V Vm 1.5 V 1.5 V Vx VOL + 0.3 V VOL + 0.3 V Vy VOH − 0.3 V VOH − 0.3 V http://onsemi.com 9 74VCXH16373 VCC PULSE GENERATOR RL DUT RT CL RL Figure 9. Test Circuit Table 4. TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V; VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V tPZH, tPHZ GND CL = 50 pF or equivalent (Includes jig and probe capacitance) RL = 500 W or equivalent RT = ZOUT of pulse generator (typically 50 W) http://onsemi.com 10 6 V or VCC × 2 OPEN GND 74VCXH16373 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 1201−01 ISSUE A 48X ÇÇÇ ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K REF 0.12 (0.005) M T U S V S T U S J J1 25 0.254 (0.010) M 48 SECTION N−N B −U− L N 1 24 A −V− PIN 1 IDENT. N F DETAIL E D 0.076 (0.003) −T− SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K K1 C M 0.25 (0.010) −W− G H DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 −−− 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 −−− 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.488 0.496 0.236 0.244 −−− 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 −−− 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 74VCXH16373/D