Ordering number : ENA1625B LV8498CT Bi-CMOS IC For VCMs http://onsemi.com Constant-current Driver IC Overview The LV8498CT is a constant current driver IC for voice coil motors that supports I2C control integrating a digital/analog converter (DAC). It uses an ultraminiature WLP package and includes a current detection resistor for constant current control, which makes the IC ideal for miniaturization of camera modules intended for use in camera-equipped mobile phones. The output transistor has a low on-resistance of 1Ω and the resistance of the built-in current detection resistor is 1Ω, which minimizes the voltage loss and helps withstand voltage drop in VCC. The function is incorporated, which, by changing the current in a stepped pattern while taking time at rise and fall of the output current, provides the current a slope, improving the converging stability of the voice coil motor (current slope function). Functions • Constant current driver for voice coil motors. • Constant current control enabled by DAC (10 bits). • I2C bus control supported. • Wide operating voltage range (2.2 to 5.0V). • Built-in current detection resistor. • 6-pin WLP package used (1.27 × 0.87 × 0.25mm). • Built-in voltage drop protection circuit (VCC = 2V output off). • Built-in thermal protection circuit. • Low output block total-resistance of 2Ω helps withstand voltage drop in VCC. (Current detection resistance + output transistor on-resistance). • Built-in VCM overshoot preventive function (current slope function). Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 5.5 Output voltage VOUT max V VCC + 0.5 Input voltage VIN max V SCL, SDA, ENA 5.5 V GND pin source current IGND Allowable power dissipation Pd max 200 mA With specified substrate * 350 mW Operating temperature Topr -30 to +85 °C Storage temperature Tstg -40 to +150 °C * Specified substrate : 40mm × 40mm × 1.6mm, Single layer glass epoxy substrate Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 June, 2013 53011 SY/52511 SY/31710 SY 20091119-S00001 No.A1625-1/8 LV8498CT Allowable Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage VCC Maximum preset output current IO Input signal voltage VIN Conditions Ratings Unit 2.2 to 5.0 150 -0.3 to VCC+0.3 V mA V Electrical Characteristics at Ta = 25°C, VCC = 2.8V Parameter Symbol Ratings Conditions min Supply current Unit typ max ICC0a ENA = 0V, SCL=SDA=VCC 1 μA ICC0b ENA=SCL=SDA=VCC, PD = 1 1 μA ICC0c ENA=SCL=SDA=VCC, D0 to D9 = 0 1 μA 0.5 3 mA 0 1 μA VCC-0.3 V ICC1 ENA=SCL=SDA=VCC , D0 to D9 ≠ 0 Input current IIN SCL, SDA, ENA High level input voltage VIH Applied to SCL, SDA and ENA pin. Low level input voltage VIL Total resistance value of the output block (built-in resistor + transistor on-resistance) RTTL -1 1.5 -0.3 VCC = 2.8V, IOUT = 80mA 2 0.5 V 3 Ω DAC block Resolution 10 bits Relative accuracy INL ±2 LSB Differential linearity DNL ±1 LSB Full code current Ifull D0 to D9 = 1 150 mA Error code current 0 Izero D0 to D9 = 0 0 mA Spark killer diode Reverse current IS (leak) Forward voltage VSF IOUT=100mA 1 μA 1.3 V Package Dimensions unit : mm (typ) 3390 B 0.4 A 0.235 0.33 MAX 0.22 0.4 1 2 1.27 3 0.87 0.08 SIDE VIEW Pd max -- Ta 0.4 BOTTOM VIEW Allowable power dissipation, Pd max -- W SIDE VIEW 0.235 TOP VIEW Specified board : 40 × 40 × 1.6mm3 Single layer glass epoxy 0.35 0.3 0.2 0.18 0.1 0 --30 --20 0 20 40 60 80 100 120 Ambient temperature, Ta -- °C SANYO : WLP6K(1.27X0.87) No.A1625-2/8 LV8498CT Pin Assignment Bottom View ( Ball side up ) 2 3 1 Pin No. Pin Name A1 SCL 0.4 A 0.4 0.87 Pin Description I2C SCL input pin A2 ENA Enable & reset *1, 2 A3 GND Ground B1 SDA I2C SDA input pin B2 VCC Power supply pin B3 OUT Output pin B *1 : Setting the ENA pin to low powers down and resets the IC. It is necessary to power on the IC by setting the ENA pin to low and hold it high during normal operation. *2 : When the ENA pin is to be used with pull_up, it is necessary to send code 0 in advance after power-on. 1.27 Block Diagram VCC ENA ON/OFF Bias Reference voltage Voltage drop protection & thermal protection RESET VCM SDA SCL I2C IF I2C DECODE DAC 10bit current setting + - OUT RF Timing genaration GND No.A1625-3/8 LV8498CT Serial Bus Communication Specifications I2C serial transfer timing conditions Standard mode twH SCL th1 twL th2 tbuf SDA th1 ts2 ts1 ts3 Resend start condition Start condition ton Stop condition tof Input waveform condition Standard mode Parameter symbol Conditions min typ 0 max unit SCL clock frequency fscl SCL clock frequency 100 kHz Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 4.7 μs ts2 Setup time of SDA with respect to the rising edge of SCL 250 ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 μs Data hold time th1 Hold time of SCL with respect to the rising edge of SDA 4.0 μs th2 Hold time of SDA with respect to the falling edge of SCL 0 μs Pulse width twL SCL low period pulse width 4.7 μs twH SCL high period pulse width 4.0 ton SCL, SDA (input) rising time 1000 ns tof SCL, SDA (input) falling time 300 ns tbuf Interval between stop condition and start condition Input waveform conditions Bus free time μs μs 4.7 High-speed mode Parameter Symbol Conditions min typ 0 max unit SCL clock frequency fscl SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 400 kHz μs ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 μs Data hold time th1 Hold time of SCL with respect to the rising edge of SDA 0.6 μs th2 Hold time of SDA with respect to the falling edge of SCL 0 μs Pulse width twL SCL low period pulse width 1.3 μs twH SCL high period pulse width 0.6 ton SCL, SDA (input) rising time 300 ns tof SCL, SDA (input) falling time 300 ns tbuf Interval between stop condition and start condition Input waveform conditions Bus free time 1.3 μs μs No.A1625-4/8 LV8498CT 2 I C bus transmission method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 th3 SCL SDA Data transfer and acknowledgement response After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the receiving end releases SDA at the falling edge of the ninth SCL clock. M S B Start Slave address L S B W A C K M S B Data L S B A C K M S B SCL 2nd byte 1st byte A1 A2 A3 A4 A5 A6 A7 0 SDA L S B A C K M S B Data L S B PD X D9 D8 D7 D6 D5 D4 A C K M S B Data L S B A C K Stop SCL 3rd byte SDA D3 D2 D1 D0 X X X X 4th byte ST2 ST1 ST0TM2TM1TM0 X X T CARE No.A1625-5/8 LV8498CT The standard data transfer to this device consists of four bytes : the slave address of the first byte and the data of the second, third and four bytes. Slave address : 0110011(0) PD : Power-down The table below shows the format of the second , third and four bytes. 2nd byte 3rd byte Serial data bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Function PD × D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 × × × × 4th byte SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 ST2 ST1 ST0 TM2 TM1 TM0 x x PD : Power_down ( PD = 1 : standby mode and reset ) D0-D9 setting method Output current (mA) Current setting code D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0.147 2 0 0 0 0 0 0 0 0 1 0 0.293 3 0 0 0 0 0 0 0 0 1 1 0.586 1021 1 1 1 1 1 1 1 1 0 1 149.70 1022 1 1 1 1 1 1 1 1 1 0 149.85 1023 1 1 1 1 1 1 1 1 1 1 150 (design value) Current slope function operation image chart At VCM energing ON At VCM energing OFF current setting code IST IST TST TST No.A1625-6/8 LV8498CT TIM 000 001 010 011 100 101 110 111 STP 000 001 010 011 At current slope OFF 0.032 0.147 0.064 0.147 0.128 0.147 0.256 0.147 0.512 0.147 1.024 0.147 2.048 0.147 4.096 0.147 0.064 0.128 0.256 0.512 1.024 2.048 4.096 8.192 0.293 0.293 0.293 0.293 0.293 0.293 0.293 0.293 0.128 0.256 0.586 0.512 0.586 1.024 0.586 2.048 0.586 4.096 0.586 8.192 0.586 16.38 0.586 0.512 1.173 1.024 1.173 2.048 1.173 4.096 1.173 8.192 1.173 16.38 1.173 32.77 1.173 1.024 2.346 2.048 2.346 4.096 2.346 8.192 2.346 16.38 2.346 32.77 2.346 65.54 2.346 2.048 4.692 4.096 4.692 8.192 4.692 16.38 4.692 32.77 4.692 65.54 4.692 131.08 4.692 9.383 4.096 9.383 8.192 9.383 16.38 9.383 32.77 9.383 65.54 9.383 131.08 9.383 262.16 9.383 32.7 65.5 130.9 261.9 523.8 1047.6 2095.1 4190.2 0.586 100 0.256 1.173 101 0.512 2.346 110 1.024 4.692 111 FULL_CODE 2.048 Sweep time In the upper row in the above table each column , the lower is a current step value (IST:mA) , at the step time (Tst:msec). Relationship between the ENA pin input, I2C input data PD, and current setting 0 (code 0) This IC supports the following three modes of setting up the standby mode : 1) Setting the ENA pin low. 2) Setting the PD bit to 1 (high) with I2C input data. 3) Setting the output current to 0 with I2C input data. Execution of one of the steps 1) to 3) causes the output current to 0 and stops operation of the circuit. When the ENA pin is set low, the I2C data register is reset and the IC is reset to its default state (PD bit set to 0 and output current setting to code 0). When the ENA pin is to be used with pull_up to VCC, it is necessary to send code 0 once after VCC ON. No.A1625-7/8 LV8498CT ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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