LV8498CT
Bi-CMOS IC
For VCMs
Constant-current Driver IC
Application Note
http://onsemi.com
Overview
The LV8498CT is a constant current driver IC for voice coil motors that supports I2C control integrating a
digital/analog converter (DAC). It uses an ultraminiature WLP package and includes a current detection
resistor for constant current control, which makes the IC ideal for miniaturization of camera modules
intended for use in camera-equipped mobile phones. The output transistor has a low on-resistance of 1Ω
and the resistance of the built-in current detection resistor is 1Ω, which minimizes the voltage loss and helps
withstand voltage drop in VCC. The function is incorporated, which, by changing the current in a stepped
pattern while taking time at rise and fall of the output current, provides the current a slope, improving the
converging stability of the voice coil motor (current slope function).
Functions
• Constant current driver for voice coil motors.
• Constant current control enabled by DAC (10 bits).
• I2C bus control supported.
• Wide operating voltage range (2.2 to 5.0V).
• Built-in current detection resistor.
• 6-pin WLP package used (1.27 × 0.87 × 0.25mm).
• Built-in voltage drop protection circuit (VCC = 2V output off).
• Built-in thermal protection circuit.
• Low output block total-resistance of 2Ω helps withstand voltage drop in VCC. (Current detection resistance
+ output transistor on-resistance).
• Built-in VCM overshoot preventive function (current slope function).
Typical Applications
• Cell phone
• Pocket movie
Semiconductor Components Industries, LLC, 2013
December, 2013
1/18
LV8498CT Application Note
Package Dimensions
unit: mm (typ)
3390
B
0.4
A
0.235
0.33 MAX
0.22
0.4
1
2
1.27
3
0.87
Specified board : 40 × 40 × 1.6mm3
Single layer glass epoxy
0.35
0.3
0.2
0.18
0.1
0
--30 --20
0.08
SIDE VIEW
Pd max -- Ta
0.4
BOTTOM VIEW
Allowable power dissipation, Pd max -- W
SIDE VIEW
0.235
TOP VIEW
0
20
40
60
80
100
120
Ambient temperature, Ta -- °C
SANYO : WLP6K(1.27X0.87)
Recommended Soldering Footprint
(Unit:mm)
Reference symbol
WLP6K
e
0.40
b
0.22
Caution: The package dimension is a reference value, which is not a guaranteed value.
Figure 1. Pin Assignment
2/18
LV8498CT Application Note
VCC
ENA
ON/OFF
Bias
Reference
voltage
Voltage drop protection
&
thermal protection
RESET
VCM
SDA
SCL
I2C
IF
I2C
DECODE
DAC
10bit
current
setting
+
-
OUT
RF
Timing genaration
GND
Figure 2. Block Diagram
3/18
LV8498CT Application Note
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum supply voltage
VCC max
Output voltage
VOUT max
Input voltage
VIN max
Conditions
Ratings
Unit
5.5
V
VCC + 0.5
V
SCL, SDA, ENA
5.5
V
200
mA
With specified substrate *
350
mW
GND pin source current
IGND
Allowable power dissipation
Pd max
Operating temperature
Topr
-30 to +85
°C
Storage temperature
Tstg
-40 to +150
°C
* Specified substrate : 40mm × 40mm × 1.6mm, Single layer glass epoxy substrate
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage
under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may
be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Supply voltage
VCC
Maximum preset output current
IO
Input signal voltage
VIN
Conditions
Ratings
min
typ
Unit
max
2.2
5.0
150
-0.3
V
mA
VCC+0.3
V
Electrical Characteristics at Ta = 25°C, VCC = 2.8V
Parameter
Supply current
Symbol
Conditions
Ratings
min
typ
Unit
max
ICC0a
ENA = 0V, SCL=SDA=VCC
1
μA
ICC0b
ENA=SCL=SDA=VCC, PD = 1
1
μA
ICC0c
ENA=SCL=SDA=VCC, D0 to D9 = 0
1
μA
0.5
3
mA
0
1
μA
VCC+0.3
V
ICC1
ENA=SCL=SDA=VCC , D0 to D9 ≠ 0
Input current
IIN
SCL, SDA, ENA
High level input voltage
VIH
Applied to SCL, SDA and ENA pin.
Low level input voltage
VIL
Total resistance value of the output block
(built-in resistor + transistor on-resistance)
RTTL
-1
1.5
-0.3
VCC = 2.8V, IOUT = 80mA
2
0.5
V
3
Ω
±2
LSB
±1
LSB
DAC block
Resolution
10
bits
Relative accuracy
INL
Differential linearity
DNL
Full code current
Ifull
D0 to D9 = 1
150
mA
Error code current 0
Izero
D0 to D9 = 0
0
mA
Spark killer diode
Reverse current
IS (leak)
Forward voltage
VSF
IOUT=100mA
1
μA
1.3
V
4/18
LV8498CT Application Note
0.8
0.6
0.6
0.4
0.4
ICC1
0.2
0.8
0.2
ICC0
ICC1 [mA]
0.8
ICC0 [μA]
ICC1 [mA]
1
1
1
0
0
2
3
4
0.6
0.4
0.2
0
5
-50
50
100
Temp [deg C]
Figure 4. VCC supply current
vs Temparature (VCC=2.8V)
2.0 2.0
1.5 1.5
Ron [Ω]
Ron (Ω)
VCC [V]
Figure 3. VCC supply current
vs VCC Voltage
0
1.0 0.5 1.0
0.5
0.0
0.0 0
20
40
60
80
100
2
120
3
Iout (A)
4
5
VCC [V]
Figure 5. Output on Resistance
vs Output Current (VCC= 2.8V)
Figure 6. Output on Resistance
vs VCC Voltage (Iout= 80mA)
2.0
Ron [Ω]
1.5
1.0
0.5
0.0
-50
0
50
100
Temp [deg C]
160
140
120
100
80
60
40
20
0
Iout [mA]
Iout [mA]
Figure 7. Output on Resistance
vs Temparature (VCC=2.8V, Iout= 80mA)
0
200
400
600
800
1000
Code [DEC]
Figure 8. Output current
vs Setting code (VCC=2.8V)
1200
160
140
120
100
80
60
40
20
0
code1023
2
code512
3
code256
4
5
VCC [V]
Figure 9. Output current
vs VCC Voltage
5/18
Iout [mA]
LV8498CT Application Note
160
140
120
100
80
60
40
20
0
code1023
-50
code512
0
code256
50
100
Temp [deg C]
1.0
1.2
0.8
1
0.8
0.6
VD [V]
VoL SDA [V]
Figure 10. Output current
vs Temparature (VCC=2.8V)
0.4
0.6
0.4
0.2
0.2
0.0
0
0
2
4
6
8
ISDA [mA]
Figure 11. Saturation voltage of SDA
vs ISDA(VCC=2.8V)
10
VDu
VDd
0
20
40
60
80
100
IF [mA]
Figure 12. Diode Forward Voltage
vs Diode Forward Current
6/18
LV8498CT Application Note
Pin Functions
Pin No.
A1
Pin name
SCL
Pin Function
Equivalent circuit
This is the I2C serial clock input pin
VDD
Input high level : 1.5V to VCC-0.3V
Input low level : -0.3V to 0.5V
A1
GND
A2
ENA
This pin switches chip enable.
VDD
When low, standby mode and reset is performed at
the same time.
This pin is held high for normal use.
Do not set to OPEN under any circumstance.
Input high level : 1.5V to VCC-0.3V
Input low level : -0.3V to 0.5V
A2
GND
A3
GND
The logic and low level analog signals shall be
connected to this pin.
B3
OUT
This is an NMOS open drain output, and the voice coil
VCC
motor is connected between this pin and the VCC pin
for use.
B3
1Ω
B2
VCC
This pin is connected to the Power supply and
monitored by the LV8498.
The operation is inhibited when VCC is below the
minimum 2.0 V value by the Low Voltage Shut Down
function.
Refer to (2) on P.8 for details.
B1
SDA
This is the I2C serial data input pin
VDD
Input high level : 1.5V to VCC-0.3V
Input low level : -0.3V to 0.5V
B1
GND
7/18
LV8498CT Application Note
Operation Description
LV8498CT is a driver IC for auto focus (AF: VCM) via I2C interface.
It is a uni-polar type driver wherein actuator is connected between VCC and OUT and driven by sink current
from OUT.
As for the drive current, linear constant current is controlled by the internal current detection resistor and the
control circuit. Moreover, the current slope function shortens settling time of the actuator.
LV8498CT can drive actuator with coil resistance which satisfies the following relation:
RAF +RTTL < VCC / IAF
(RAF: Coil resistor of AF VCM, RTTL: OUT ON resistance, IAF: Drive current of AF VCM)
Where VCC=2.8V:
RAF < VCC / IAF- RTTL
< 2.8V/ 80mA- 3 Ω
< 32 Ω
Make sure to allow margin for coil resistor, VCC voltage and drive current based on the above relation.
(1) Function and setup for ENA pin
ENA is set to active mode at high level input and to standby mode at low level input. During standby mode,
I2C signal is not receivable even if VCC is impressed. Since all the circuits are turned off, current
consumption is zero.
ENA pin does not incorporate pull-up nor pull-down. Hence, ENA cannot be set to open. ENA can be set to
pull-up externally. In this case, it is recommended to transfer “All-zero” to the entire register data when
VCC is impressed.
(2) VCC Low Voltage Shut Down
The built-in comparator, associated with the band gap reference, continuously monitors the VCC input
while ENA is High.
When VCC drops 2.0V (typical) or lower, this IC generates power saving sequence to turn off the output.
However, this status is not the standby mode; therefore, current consumption is not quite zero.
(3) Output transistor operation mode
When the output transistor is ON, coil current flow through the VCM.
The output voltage is obtained as follows:
VSATOUT + 1Ω × Iout = RTTL × Iout
* VSATOUT: Saturation voltage of the output transistor
when it energizes Iout.
When the output transistor is OFF after energization, coil
current flows through upper Diode.
In this case, output voltage is:
VCC + VF
Do not exceed the absolute maximum ratings under no
circumstance.
VCC
OUT
Figure 13. Output transistor operation
8/18
LV8498CT Application Note
Serial Bus Communication Specifications
(1) I2C serial transfer timing conditions
twH
SCL
th1
twL
th2
tbuf
SDA
th1
ts2
ts1
ts3
Resend start condition
Start condition
ton
Stop condition
tof
Input waveform condition
Figure 14. I2C serial transfer timing Diagram
Standard mode
Parameter
SCL clock frequency
Data setup time
Data hold time
Pulse width
Input waveform conditions
Bus free time
symbol
fscl
Conditions
min
SCL clock frequency
typ
0
max
100
unit
kHz
μs
ts1
Setup time of SCL with respect to the falling edge of SDA
4.7
ts2
Setup time of SDA with respect to the rising edge of SCL
250
ns
ts3
Setup time of SCL with respect to the rising edge of SDA
4.0
μs
th1
Hold time of SCL with respect to the rising edge of SDA
4.0
μs
th2
Hold time of SDA with respect to the falling edge of SCL
0
μs
twL
SCL low period pulse width
4.7
μs
twH
SCL high period pulse width
4.0
ton
SCL, SDA (input) rising time
1000
ns
tof
SCL, SDA (input) falling time
300
ns
tbuf
Interval between stop condition and start condition
μs
μs
4.7
High-speed mode
Parameter
SCL clock frequency
Data setup time
Data hold time
Pulse width
Input waveform conditions
Bus free time
Symbol
fscl
Conditions
SCL clock frequency
min
typ
0
max
400
unit
kHz
μs
ts1
Setup time of SCL with respect to the falling edge of SDA
0.6
ts2
Setup time of SDA with respect to the rising edge of SCL
100
ns
ts3
Setup time of SCL with respect to the rising edge of SDA
0.6
μs
th1
Hold time of SCL with respect to the rising edge of SDA
0.6
μs
th2
Hold time of SDA with respect to the falling edge of SCL
0
μs
twL
SCL low period pulse width
1.3
μs
twH
SCL high period pulse width
0.6
ton
SCL, SDA (input) rising time
300
ns
tof
SCL, SDA (input) falling time
300
ns
tbuf
Interval between stop condition and start condition
1.3
μs
μs
9/18
LV8498CT Application Note
2
(2) I C bus transmission method
2-1) Start and stop conditions
The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram
below during a data transfer operation.
SCL
SDA
ts2
th2
Figure 15. The timing chart of the state of SDA
When data is not being transferred, both SCL and SDA are in the high level. The start condition is generated
and access is started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high
while SCL is high.
Start condition
Stop condition
SCL
SDA
th1
th3
2
Figure 16. I C Start and Stop conditions
10/18
LV8498CT Application Note
2-2) Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in
an I2C bus, a unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is
allocated to the 7-bit slave address and to the command (Write/Read) indicating the transfer direction of the
subsequent data. However, this IC is provided with only a write mode for receiving the data. Every time 8 bits
of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end.
Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending
end is released, and SDA is set to low at the receiving end, causing the ACK signal to be sent. When, after
the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the
receiving end releases SDA at the falling edge of the ninth SCL clock.
Figure 17. The chain of signals from Start to Stop
A set of data transferred to LV8498CT should bundle the following 4 data: the slave address of the first byte and
the data of the second, third and fourth bytes.
Slave address: 0110011(S7→S1)
The table below shows the format of the second, third and fourth bytes.
2nd byte
3rd byte
Serial data bits
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Function
PD
-
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
ST2
ST1
ST0
TM2
TM1
TM0
-
-
4th byte
11/18
LV8498CT Application Note
Serial Mode Setting
(1) AF mode setting
1-1) Setup for power down data
SD7 is in the 2nd byte to which power down data (PD) is allocated. (PD=0, Active. PD=1, Power down.)
Where PD=1, the IC does not operate even if a following data is configured.
Also when PD=1 is set during energization, the output current decreases according to the setting in 1-3)
Current slope Setting and eventually turns zero.
1-2) AF current DAC setting
AF drive current is configured by 10-bit DAC. See the chart below for the relation between setup data and
drive current.
AF DAC code
D9
D8
D7
D6
D5
D4
D3
D2
D1
Setting current [mA]
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0 (drive-OFF)
0.1466
2
0
0
0
0
0
0
0
1
0
0.293
3
0
0
0
0
0
0
0
1
1
0.440
1021
1
1
1
1
1
1
1
0
1
149.68
1022
1
1
1
1
1
1
1
1
0
149.83
1023
1
1
1
1
1
1
1
1
1
150
Note: When “AF DAC code” is 0, AF driver is OFF.
If other codes are selected, AF driver starts to drive at the same time as 4 bytes data are set.
Setting current is the theory value provided by following formula.
Setting current = {(Full code current)/1023} × (AF DAC code)
300
250
Stroke [μm]
200
150
100
sample_A
50
sample_B
0
0
20
40
60
80
100
Io[mA]
Figure 18. Io vs Lens stroke
The above graph shows the measurement result of lens stroke using Laser Displacement Sensor when 2
types of lens module are driven by LV8498CT. The measurement has been conducted with the 2 modules
placed horizontally.
The characteristics may vary depends on the usage AF-VCM and lens module. Therefore, make sure to
perform examination and adjustment thoroughly as needed.
12/18
LV8498CT Application Note
1-3) AF current slope Setting
The gradient of AF current slope is configured by the 2 parameters of step time and step current value. Since
each parameter uses 3 bits, 6 bits are used in total. 001000 sets the highest gradient whereas 111111 sets
the lowest gradient. 000XXX turns off current slope function and AF drive current changes to a setting value
step by step.
Since register data is the 4th byte of AF current DAC Setting, it needs to be set with AF current DAC Setting
simultaneously.
AF current slope setting STP (ST2, ST1, ST0) TIM (TM2, TM1, TM0)
TIM
STP
000
001
010
000
001
010
011
100
101
110
111
011
100
101
110
111
Current slope function OFF
0.032
0.064
0.128
0.256
0.512
1.024
2.048
4.096
0.1466
0.1466
0.1466
0.1466
0.1466
0.1466
0.1466
0.1466
0.064
0.128
0.256
0.512
1.024
2.048
4.096
8.192
0.293
0.293
0.293
0.293
0.293
0.293
0.293
0.293
0.128
0.256
0.512
1.024
2.048
4.096
8.192
16.38
0.586
0.586
0.586
0.586
0.586
0.586
0.586
0.586
0.256
0.512
1.024
2.048
4.096
8.192
16.38
32.77
1.173
1.173
1.173
1.173
1.173
1.173
1.173
1.173
0.512
1.024
2.048
4.096
8.192
16.38
32.77
65.54
2.345
2.345
2.345
2.345
2.345
2.345
2.345
2.345
1.024
2.048
4.096
8.192
16.38
32.77
65.54
131.08
4.691
4.691
4.691
4.691
4.691
4.691
4.691
4.691
2.048
4.096
8.192
16.38
32.77
65.54
131.08
262.16
9.382
9.382
9.382
9.382
9.382
9.382
9.382
9.382
In the above table,
Upper row of each field: Step time (Tst) [mSec]
Lower row of each field: Step current value (Ist) [mA]
Figure 19. Current slope function Image Diagram
13/18
LV8498CT Application Note
Current slope function: OFF
Current slope function: ON
(Step current= 0.782mA, Step time= 2.048mSec)
Lens Displacement
[50μm/div]
50μm→100μm
Width=10μm↓
Lens Displacement
0μm level
Output current
[20mA/div]
Output current
0mA level
Settling time: 402mSec
Settling time: 32mSec
Settling time: 402mSec
Settling time: 34mSec
100μm→50μm
Figure 20. The sample of Current slope function effect
The above figure is the comparison of the settling time with or without current slope function measured by
laser displacement sensor. Depends on the characteristics of VCM, an optimum gradient of slope variers.
Make sure to test with AF-VCM thoroughly and make an adjustment if necessary.
1-4) Relationship between the ENA pin input, I2C input data PD, and current setting 0 (code 0)
This IC supports the following three modes of setting up the standby mode:
1) Setting the ENA pin low.
2) Setting the PD bit to 1 (high) with I2C input data.
3) Setting the output current to 0 with I2C input data.
Execution of one of the steps 1) to 3) causes the output current to 0 and stops operation of the circuit.
When the ENA pin is set low, the I2C data register is reset and the IC is reset to its default state (PD bit set to
0 and output current setting to code 0).
14/18
LV8498CT Application Note
Typical Application Circuit
Figure 21. Typical Application Circuit
15/18
LV8498CT Application Note
Evaluation Board
40mm
“VCC”
Power Supply
40mm
C1:
VCC Bypass Capacitor
R1:
Pull-up Resistor
for terminal SDA
R2:
Pull-up Resistor
for terminal SCL
R3:
Pull-up Resistor
for terminal ENA
PC installed evaluation software
Figure 22. Evaluation Board overview
Bill of Materials for LV8498CT Evaluation Board
Designator
Quantity
C1
1
R1(*)
R2(*)
R3(**)
Description
VCC Bypass
Capacitor
Pull-up
Resistor for
terminal SDA
Pull-up
Resistor for
terminal SCL
Pull-up
Resistor for
terminal ENA
IC1
1
CNCT1
1
Motor Driver
Pin Header
Straight Type
TP1-TP5
5
Test Point
Manufacturer
Manufacturer Part
Number
Substitution
Allowed
Lead
Free
±10%
Murata
GRM188B31H104KA92*
Yes
Yes
1kΩ
1/10W
±5%
KOA
RK73B1JT**102J
Yes
Yes
1kΩ
1/10W
±5%
KOA
RK73B1JT**102J
Yes
Yes
100kΩ
1/10W
±5%
KOA
ON
semiconductor
RK73B1JT**104J
Yes
Yes
LV8498CT
No
Yes
HIROSE
DF1-6P-2.5DSA
MAC8
ST-1-3
Value
0.1µF,
50V
Tolerance
Footprint
2
(*) It is the part we recommend. If I C Master device does not have pull-up resistors for SDA and SCL lines, mount on the space.
(**) It is the part we recommend. If the ENA pin is to be used with pull-up. Refer to P.8.
16/18
LV8498CT Application Note
Evaluation Board circuit
B1
SDA
SCL
A1
B2
VCC
ENA
A2
B3
OUT
GND
A3
Space for resistors
0.1µF
Figure 23. Evaluation Board circuit schematic
Operation Guide
• Connect AF-VCM with OUT and VCC.
• Connect a power supply with VCC.
Connect GND line with GND pin.
• If you use the master device we provided, connect USB adapter with the evaluation board.
If you have the original master device, connect I2C lines with SDA pin and SCL pin.
Check if pull-up resistors have been connected to the lines. If not, mount R1 and R2 on the evaluation
board.
The USB adapter we provided has built-in resistors. Therefore, you do not need to mount any resistor.
• Confirm that ENA pin is not OPEN. And supply power.
After that, if the ENA pin is pull-down, input High signal to the pin.
If the pin is pull-up, transfer zero-code to all data and ENABLE “H”.
When you transfer ENABLE “L”, current flows from VCC to GND.
• If you have the original master device, refer to “Operation Description” from P.8 and create I2C program.
The points of attention to design applications
• VCC, GND and OUT where a large current flows are laid out fat and short as much as possible.
• VCC bypass capacitor should be mounted as near as possible to the IC.
• Do not exceed the absolute maximum ratings under no circumstance. The terminal OUT can exceed
VCC due to reversed voltage or regenerated current. Refer to P.8.
• SCL and other fast switching digital signals should be shielded from other parts of the board.
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LV8498CT Application Note
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