NB4N7132 D

NB4N7132
Link Replicator for Fibre
Channel, Gigabit Ethernet,
HDTV and SATA
Up to 1.5 Gb/s
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Description
The NB4N7132 is a high performance 3.3 V Serial Link Replicator
which provides the function of serial loop replication and serial
loopback control commonly required in Fibre Channel, GbE, HDTV
and SATA applications. Other popular applications include Host Bus
Adaptors for routing between internal and external connectors, and
hot−pluggable links between redundant switch fabric cards.
IN is sent to both OUT0 and OUT1; each output is enabled by OE0
and OE1 when HIGH. OUT0 can select either IN or IN1 via the
MUX0 pin. Likewise, OUT1 can select between IN or IN0 via the
MUX1 pin. Out can select between IN0 and IN1.
In Link Replicator applications, such as the Line Card to Switch
Card links, IN is transmitted to both OUT0 and OUT1 which either
IN0 or IN1 is selected at OUT. In Host Adapter applications, IN goes
to OUT0 (an internal connector) which returns data on IN0. IN0 is
looped to OUT1 (an external connector) which returns data on IN1
and then back to the SerDes on OUT.
The NB4N7132 is packaged in a 4.7 mm x 9.7 mm TSSOP−28.
MARKING DIAGRAM*
NB4N
7132G
ALYW
A
L
Y
W
G
Features
• Replicates Fibre Channel, Gigabit Ethernet, HDTV, and
•
•
•
•
•
•
•
•
28 Lead TSSOP
DT SUFFIX
CASE 948A
Serial ATA (SATA) Links
T11 Fibre Channel Complaint at 1.0625 Gb/s
No External Components Required
IEEE802.3z Gigabit Ethernet Compliant at 1.25 Gb/s
SMPTE−292M Compliant at 1.485 Gb/s
450 mW Maximum Power Dissipation
Operating Range: VCC = 3.135 V to 3.465 V
28−pin, 4.4 mm x 9.7 mm TSSOP Package
These are Pb−Free Devices
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
NB4N7132
LOOP0
TX
RX
LOOP1
Figure 1. Simplified Application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 1
1
Publication Order Number:
NB4N7132/D
NB4N7132
TYPICAL APPLICATIONS CIRCUIT
VDDP0
1
28 OUT0+
OE0
2
27 OUT0−
MUX
3
26 VDDP0
GND
4
25 GND
IN+
5
24 IN0+
OUT0+
IN−
6
23 IN0−
OUT0−
GND
7
OE1
8
21 OUT1+
VDD
9
20 OUT1−
VDDP
10
19 VDDP1
OUT1+
OUT+
11
18 IN1+
OUT1−
OUT−
12
17 IN1−
MUX1
VDDP
13
16 MUX0
GND
14
15 MUX1
IN0+
IN0−
IN+
IN−
OE0
0
1
0
OUT+
OUT−
MUX0
IN1+
IN1−
1
MUX
OE1
0
1
Figure 2. Simplified Block Diagram
NB4N7132
22 VDDP1
Figure 3. Pin Diagram for TSSOP−28
Table 1. OE, OUTPUT ENABLE FUNCTION
OEx*
Function
1
Outputs Enabled
0
Outputs Disabled OUTn+ = H, OUTn− = H
*Defaults to HIGH when left open
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
5, 6
24, 23
18, 17
IN+, IN−
IN0+, IN0−
IN1+, IN1−
LVPECL Input
LVPECL Input
LVPECL Input
11, 12
28, 27
21, 20
OUT+, OUT−
OUT0+, OUT0−
OUT1+, OUT1−
LVPECL Output
LVPECL Output
LVPECL Output
2
8
OE0
OE1
LVTTL Input
LVTTL Input
OE0/OE1 enables OUT0/OUT1 when HIGH. When LOW, OUTx are
powered down and both OUT+ and OUT− float HIGH.
3
MUX
LVTTL Input
Selects Source for OUT, Selects Either IN0 (LOW) or IN1 (HIGH); defaults
HIGH when left open.
15
MUX1
LVTTL Input
Selects Source for OUT1. Selects Either IN (HIGH) or IN0 (LOW); defaults
HIGH when left open.
16
MUX0
LVTTL Input
Selects Source for OUT0. Selects either IN (LOW) or IN1 (HIGH); defaults
HIGH when left open.
9
VDD
Power Supply
3.3 V Positive Supply Voltage for Digital Logic.
10, 13
1, 26
19, 22
VDDP
VDDP0
VDDP1
Power Supply
3.3 V supply for LVPECL output drivers. VDDP is for OUT, VDDP0 is for
OUT0, and VDDP1 is for OUT1.
4, 7, 14, 25
GND
Power Supply
Negative Supply Voltage, Connected to Ground
Non−inverted, Inverted, Differential Data Inputs internally biased to
Approximately 1.2 V.
Non−inverted, Inverted Differential Outputs.
All VDD, VDDPx and GND Pins must be externally connected to appropriate power supply to guarantee proper operation.
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NB4N7132
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pullup Resistor
ESD Protection
96 k
Human Body Model
Machine Model
Moisture Sensitivity (Note 1)
Flammability Rating
> 1 kV
> 100 V
Level 3
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
268 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Min
Max
Unit
VDD
Positive Power Supply
GND = 0 V
0.5
4.0
V
VINP
Input Voltage, PECL
GND = 0 V
−0.5
VDD + 0.5
V
VINT
Input Voltage, TTL
GND = 0 V
−0.5
VDD + 0.5
V
IOUT
Output HIGH current, PECL
−50
+50
mA
TC
Case temperature under bias
−55
+125
°C
TA
Operating Temperature Range
−40
+85
°C
Tstg
Storage Temperature Range
−65
+150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−28
76
60
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
(Note 2)
TSSOP−28
25
°C/W
Tsol
Wave Solder
265
°C
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB4N7132
Table 5. DC CHARACTERISTICS VDD = 3.30 V $5%, GND = 0 V; TA = −40°C to +85°C
Characteristic
Symbol
Min
Typ
3.14
Max
Unit
3.47
V
125
mA
450
mW
VDD
Power Supply Voltage, 3.30 V $5%
IDD
Power Supply Current (Outputs open)
PD
Power Dissipation; Outputs Open; VDD = VDDmax
VIN
Receiver Differential Voltage Amplitude; (IN, IN0, IN1), AC−Coupled,
Internally Biased to 1.2 V; Differential Measurement − (VINn+ − VINn−)
300
2600
VOUT50
Output Differential Voltage Swing, peak−peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 50 to VDD – 2.0 V
Differential Measurement − (VOUTn+ − VOUTn−)
1000
2200
VOUT75
Output Differential Voltage Swing, peak−peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 75 to VDD – 2.0 V
Differential Measurement − (VOUTn+ − VOUTn−)
105
mV
mV
mV
1200
2200
VDD + 0.5
LVCMOS/LVTTL INPUTS
VIH
Input HIGH Voltage, TTL
2.0
VIL
Input LOW Voltage, TTL
0
IIH
Input HIGH Current, TTL; VIN = 2.4 V
IIL
Input LOW Current, TTL; VIN = 0.5 V
−100
V
0.8
V
100
A
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS VDD = 3.3 V $5%, GND = 0 V −40°C to +85°C
Characteristic
Symbol
Min
fIN / OUT
Input / Output Frequency Range
tr/tf
Output rise and Fall Times (Note 3)
tPD
Propagation Delay, IN to OUT
TDJ
Deterministic Jitter Added to Serial Input Up to 1.5 Gb/s;
K28.5$ Pattern
Typ
Max
Unit
1.5
Gb/s
140
175
ps
0.375
4.0
ns
40
ps pk−pk
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measured 20% to 80%
IN+/−
IN0+/−
IN1+/−
OUT+/−
OUT0+/−
OUT1+/−
tpd
tpd
Figure 4. Timing Waveforms
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tJ
NB4N7132
0.01F
0.01F
TX+
R
0.01F
TX−
0.01F
O1+
I+
RT
I1+
RX+
RT
0.01F
I−
O+
O1−
0.01F
I1−
RT
O−
RX−
R
SerDes
NB4N7132
NB4N7132
0.01F
RX+
0.01F
O+
RT
I1+
0.01F
O1+
I+
RT
0.01F
0.01F
RX−
SerDes
O−
I1−
RT
R
0.01F
I−
O1−
TX+
R
TX−
“R” is 150 for both 100 differential or 150 differential traces.
“RT” matches the differential impedance of the link.
Figure 5. NB4N7132 Application Interface Example
IN+/IN− Input Functionality
OEx Output Enable
The differential inputs are internally biased to Y1.2 V. In
a typical application, the differential inputs are
capacitor−coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N7132 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
The NB4N7132 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in IDD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx− are set HIGH.
OUT+ / OUT− Outputs
Power Supply Bypass information
The OUT+ and OUT− outputs of the NB4N7132 are
designed to drive differential transmission lines with
nominally 50 or 75 characteristic impedance. These
differential output buffers utilize positive emitter coupled
logic (PECL) architecture, but they do not require DC output
load resistors, and will operate properly with or without the
resistors.
A clean power supply will optimize the performance of
the device. The NB4N7132 provides separate power supply
pins for the digital circuitry (VDD) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01 F to 0.1 F
on each VDD pin will help ensure a noise free VDD power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Resource Reference of Application Notes
AND8002
−
Marking and Date Codes
AND8009
−
ECLinPS Plus Spice I/O Model Kit
ORDERING INFORMATION
Package
Shipping†
NB4N7132DTG
TSSOP−28
(Pb−Free)
50 Units / Rail
NB4N7132DTR2G
TSSOP−28
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB4N7132
PACKAGE DIMENSIONS
28 LEAD TSSOP
DT SUFFIX
CASE 948AA−01
ISSUE O
e
28
PIN ONE
LOCATION
2X
0.20 C B A
15
ÇÇÇÇÇ
ÇÇÇÇÇ
1
B
DETAIL A
E1 E
14
A
0.05
A
D
0.10 C
DIM
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
R
R1
S
01
02
03
A
A2
A
SEATING
PLANE
C
28X
A1
b
0.10 C B A
02
c
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
S
H
(b)
c1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
R1
MILLIMETERS
MIN
MAX
−−−
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
9.60
9.80
6.40 BSC
4.30
4.50
0.65 BSC
0.45
0.75
1.00 REF
0.09
−−−
0.09
−−−
0.20
−−−
0_
8_
12 _REF
12 _REF
R
GAUGE PLANE
b1
SECTION A−A
L
(L1)
0.25
03
01
DETAIL A
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NB4N7132/D