IMD10AMT1G D

IMD10AMT1G
Dual Bias Resistor
Transistor
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias Resistor
Network
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• High Current: IC = 500 mA max
• This is a Pb−Free Device
(3)
MAXIMUM RATINGS (TA = 25°C)
Rating
(1)
R1
Symbol
Value
Unit
Collector−Base Voltage
V(BR)CBO
50
Vdc
Collector−Emitter Voltage
V(BR)CEO
50
Vdc
Emitter−Base Voltage
V(BR)EBO
5.0
Vdc
IC
500
mAdc
Collector Current − Continuous
Q1
Q2
R2
R1
(4)
(5)
(6)
SC−74
THERMAL CHARACTERISTICS
Characteristic
(2)
Symbol
Max
Unit
Power Dissipation*
PD
285
mW
Junction Temperature
TJ
150
°C
Storage Temperature
Tstg
−55 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
*Total for both Transistors.
MARKING
DIAGRAM
6
1
SC−74R
318AA
Style 21
D10 M
G
D10 = Specific Device Code
M = Date Code
G
= Pb−Free Package
ORDERING INFORMATION
Device
IMD10AMT1G
Package
Shipping†
SC−74R
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 1
Publication Order Number:
IMD10AMT1G/D
IMD10AMT1G
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted, common for Q1 and Q2, − minus sign for Q1(PNP) omitted)
Symbol
Min
Max
Unit
Collector−Base Breakdown Voltage
(IC = 50 mAdc, IE = 0 A)
V(BR)CBO
50
−
Vdc
Collector−Emitter Breakdown Voltage
(IC = 1.0 mAdc, IB = 0 A)
V(BR)CEO
50
−
Vdc
Emitter−Base Breakdown Voltage
(IE = 50 mAdc, IC = 0 A)
V(BR)EBO
5.0
−
Vdc
ICBO
−
100
nA
IEBO
−
−
1.0
0.5
mA
Collector−Emitter Cutoff Current
(VCE = 15 Vdc, IB = 0 A)
ICEO
−
500
nA
Collector−Emitter Cutoff Current
(VCE = 25 Vdc, IB = 0 A)
ICES
−
100
nA
68
100
−
600
VCE(sat)
−
0.3
Vdc
Output Voltage (on)
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW)
VOL
−
0.2
Vdc
Output Voltage (off)
(VCC = 5.0 V, VB = 0.25 V, RL = 1.0 kW)
VOL
4.9
−
Vdc
Input Resistor
Q1(PNP)
Q2(NPN)
R1
70
7.0
130
13
W
kW
Resistor Ratio
Q1(PNP)
Q2(NPN)
R1/R2
0.008
−
0.012
−
Characteristic
OFF CHARACTERISTICS
Collector−Base Cutoff Current
(VCB = 50 Vdc, IE = 0 A)
Emitter−Base Cutoff Current
(VEB = 6.0 Vdc, IC = 0 A)
Q1 (PNP)
Q2 (NPN)
ON CHARACTERISTICS (Note 1)
hFE
DC Current Gain
(VCE = 5.0 V, IC = 100 mA) Q1(PNP)
(VCE = 5.0 V, IC = 1.0 mA) Q2(NPN)
Collector−Emitter Saturation Voltage
(IC = 10 mA, IB = 1.0 mA)
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle < 2.0%.
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2
IMD10AMT1G
TYPICAL CHARACTERISTICS (NPN)
1000
IC/IB = 10
VCE, COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
hFE, DC CURRENT GAIN
10
VCE = 5 V
25°C
75°C
−25°C
100
10
25°C
0.1
75°C
−25°C
0.01
1
10
100
1
10
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 1. DC Current Gain
Figure 2. Collector−Emitter Saturation Voltage
100
1000
VO = 0.2 V
VO = 5 V
100
Vin, INPUT VOLTAGE (V)
IC, COLLECTOR CURRENT (mA)
1
75°C
10
25°C
1
−25°C
0.1
0.01
10
25°C
−25°C
1
75°C
0.1
0.001
1
2
3
1
4
10
Vin, INPUT VOLTAGE (V)
IC, COLLECTOR CURRENT (mA)
Figure 3. Output Current vs. Input Voltage
Figure 4. Input Voltage vs. Output Current
4
Cob, CAPACITANCE (pF)
0
3
2
1
0
0
10
20
30
40
VR, REVERSE BIAS VOLTAGE (V)
Figure 5. Output Capacitance
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3
50
100
IMD10AMT1G
TYPICAL CHARACTERISTICS (PNP)
1
1000
IC/IB = 10
VCE, COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
hFE, DC CURRENT GAIN
VCE = 5 V
100
75°C
25°C
−25°C
25°C
75°C
−25°C
0.01
10
1
10
100
1
1000
10
100
1000
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 6. DC Current Gain
Figure 7. Collector−Emitter Saturation Voltage
10
1000
75°C
25°C
100
VO = 0.2 V
VO = 5 V
Vin, INPUT VOLTAGE (V)
IC, COLLECTOR CURRENT (mA)
0.1
−25°C
10
1
0.1
0.01
25°C
1
−25°C
75°C
0.1
0.001
1
2
3
1
4
10
100
1000
Vin, INPUT VOLTAGE (V)
IC, COLLECTOR CURRENT (mA)
Figure 8. Output Current vs. Input Voltage
Figure 9. Input Voltage vs. Output Current
25
Cob, CAPACITANCE (pF)
0
20
15
10
5
0
0
10
20
30
40
VR, REVERSE BIAS VOLTAGE (V)
Figure 10. Output Capacitance
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4
50
IMD10AMT1G
PACKAGE DIMENSIONS
SC−74R
CASE 318AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
D
4
5
3
2
6
E
HE
1
DIM
A
A1
b
c
D
E
e
L
HE
q
b
e
q
c
A
0.05 (0.002)
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.37
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.015
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
STYLE 21:
PIN 1. COLLECTOR 1
2. EMITTER 2
3. BASE 2
4. COLLECTOR 2
5. EMITTER 1
6. BASE 1
SOLDERING FOOTPRINT*
2.4
0.094
0.95
0.037
1.9
0.074
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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IMD10AMT1G/D