INTERSIL KAD5512P

KAD5512P
Features
The KAD5512P is the low-power member of the
KAD5512 family of 12-bit analog-to-digital converters.
Designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process, the family
supports sampling rates of up to 250MSPS. The
KAD5512P is part of a pin-compatible portfolio of 10, 12
and 14-bit A/Ds with sample rates ranging from
125MSPS to 500MSPS.
• Half the Power of the Pin-Compatible KAD5512HP
Family
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of various
parameters such as gain and offset.
• Clock Phase Selection
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P is available in 72- and 48-contact
QFN packages with an exposed paddle. Operating from a
1.8V supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
Key Specifications
Applications*(see page 34)
• SNR = 66.1dBFS for fIN = 105MHz (-1dBFS)
• SFDR = 87dBc for fIN = 105MHz (-1dBFS)
• 1.5GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Programmable Gain, Offset and Skew Control
• Over-Range Indicator
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Total Power Consumption
- 267/219mW @ 250/125MSPS (SDR Mode)
- 234/189mW @ 250/125MSPS (DDR Mode)
• Broadband Communications
Related Literature*(see page 34)
• WiMAX and Microwave Receivers
• High-Performance Data Acquisition
• Communications Test Equipment
• See FN6805, KAD5512P-50, “12-Bit, 500MSPS A/D
Converter”
OVDD
AVDD
CLKDIV
• See FN6808, KAD5512HP, “High Performance 12-Bit,
250/210/170/125MSPS ADC”
0
CLKOUTP
CLOCK
GENERATION
CLKN
CLKOUTN
D[11:0]P
VINP
12-BIT
250 MSPS
ADC
SHA
VINN
VCM
1.25V
+
–
SPI
CONTROL
DIGITAL
ERROR
CORRECTION
D[11:0]N
LVDS/CMOS
DRIVERS
OUTFMT
ORP
ORN
OUTMODE
-20
AMPLITUDE (dBFS)
CLKP
-40
-60
-80
-100
1
OVSS
CSB
SCLK
SDIO
SDO
AVSS
NAPSLP
-120
0
October 1, 2010
FN6807.4
AIN = -1.0dBFS
SNR = 66.0dBFS
SFDR = 86.5dBc
SINAD = 65.9dBFS
20
40
60
80
100
120
FREQUENCY (MHz)
SINGLE-TONE SPECTRUM @ 105MHz (250MSPS)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008-2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
KAD5512P
Low Power 12-Bit, 250/210/170/125MSPS ADC
KAD5512P
Pin-Compatible Family
PACKAGE
RESOLUTION
SPEED
(MSPS)
Q48EP
Q72EP
KAD5514P-25/21/17/12
14
250/210/170/125
X
X
KAD5512P-50
12
500
KAD5512P-25/21/17/12
12
250/210/170/125
X
KAD5512HP-25/21/17/12
12
250/210/170/125
X
KAD5510P-50
10
500
Coming Soon
KAD5510P-25/21/17/12
10
250/210/170/125
MODEL
X
X
X
X
X
Pin Configuration
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D11P
D11N
D10P
D10N
D9P
D9N
OVDD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
OVSS
AVSS
KAD5512P
(72 LD QFN)
TOP VIEW
55
AVDD 1
54 D8P
DNC 2
53 D8N
DNC 3
52 D7P
DNC 4
51 D7N
DNC 5
50 D6P
AVDD 6
49 D6N
AVSS 7
48 CLKOUTP
AVSS 8
47 CLKOUTN
VINN 9
46 RLVDS
PAD
VINP 10
45 OVSS
AVSS 11
44 D5P
AVDD 12
43 D5N
DNC 13
42 D4P
DNC 14
41 D4N
VCM 15
40 D3P
CLKDIV 16
39 D3N
DNC 17
38 D2P
CONNECT THERMAL PAD TO AVSS
DNC 18
28
29
30
31
32
33
34
35
36
D0N
D0P
D1N
D1P
OVDD
NAPSLP
27
DNC
OUTMODE
26
DNC
CLKN
25
DNC
CLKP
24
DNC
23
OVDD
22
OVSS
21
RESETN
20
AVDD
19
AVDD
37 D2N
FIGURE 1. PIN CONFIGURATION
2
FN6807.4
October 1, 2010
KAD5512P
Pin Descriptions - 72 Ld QFN
LVDS
[LVCMOS] FUNCTION SDR MODE
PIN NUMBER
LVDS [LVCMOS] NAME
1, 6, 12, 19, 24,
71
AVDD
2-5, 13, 14, 17,
18, 28-31
DNC
Do Not Connect
7, 8, 11, 72
AVSS
Analog Ground
9, 10
VINN, VINP
15
VCM
16
CLKDIV
Tri-Level Clock Divider Control
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
23
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low, see page 19)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
32
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
DDR Logical Bits 1, 0
(LVDS)
33
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[LVCMOS Bit 0]
DDR Logical Bits 1, 0
(LVDS or CMOS)
34
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
NC in DDR
35
D1P
[D1]
LVDS Bit 1 Output True
[LVCMOS Bit 1]
NC in DDR
37
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
DDR Logical Bits 3,2
(LVDS)
38
D2P
[D2]
LVDS Bit 2 Output True
[LVCMOS Bit 2]
DDR Logical Bits 3,2
(LVDS or CMOS)
39
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
NC in DDR
40
D3P
[D3]
LVDS Bit 3 Output True
[LVCMOS Bit 3]
NC in DDR
41
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
DDR Logical Bits 5,4
(LVDS)
42
D4P
[D4]
LVDS Bit 4 Output True
[LVCMOS Bit 4]
DDR Logical Bits 5,4
(LVDS or CMOS)
43
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
NC in DDR
44
D5P
[D5]
LVDS Bit 5 Output True
[LVCMOS Bit 5]
NC in DDR
46
RLVDS
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
49
D6N
[NC]
3
DDR MODE COMMENTS
1.8V Analog Supply
Analog Input Negative, Positive
Common Mode Output
Tri-Level Output Mode Control (LVDS, LVCMOS)
LVDS Bias Resistor
(Connect to OVSS with a 10kΩ, 1% resistor)
LVDS Bit 6 Output Complement
[NC in LVCMOS]
DDR Logical Bits 7,6
(LVDS)
FN6807.4
October 1, 2010
KAD5512P
Pin Descriptions - 72 Ld QFN (Continued)
LVDS
[LVCMOS] FUNCTION SDR MODE
PIN NUMBER
LVDS [LVCMOS] NAME
DDR MODE COMMENTS
50
D6P
[D6]
LVDS Bit 6 Output True
[LVCMOS Bit 6]
DDR Logical Bits 7, 6
(LVDS or CMOS)
51
D7N
[NC]
LVDS Bit 7 Output Complement
[NC in LVCMOS]
NC in DDR
52
D7P
[D7]
LVDS Bit 7 Output True
[LVCMOS Bit 7]
NC in DDR
53
D8N
[NC]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
DDR Logical Bits 9, 8
(LVDS)
54
D8P
[D8]
LVDS Bit 8 Output True
[LVCMOS Bit 8]
DDR Logical Bits 9, 8
(LVDS or CMOS)
57
D9N
[NC]
LVDS Bit 9 Output Complement
[NC in LVCMOS]
NC in DDR
58
D9P
[D9]
LVDS Bit 9 Output True
[LVCMOS Bit 9]
NC in DDR
59
D10N
[NC]
LVDS Bit 10 Output Complement
[NC in LVCMOS]
DDR Logical Bits 11, 10
(LVDS)
60
D10P
[D10]
LVDS Bit 10 Output True
[LVCMOS Bit 10]
DDR Logical Bits 11, 10
(LVDS or CMOS)
61
D11N
[NC]
LVDS Bit 11 Output Complement
[NC in LVCMOS]
NC in DDR
62
D11P
[D11]
LVDS Bit 11 Output True
[LVCMOS Bit 11]
NC in DDR
63
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
64
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
66
SDO
SPI Serial Data Output
(4.7kΩ pull-up to OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
PAD
(Exposed Paddle)
AVSS
Tri-Level Output Data Format Control (Two’s
Comp., Gray Code, Offset Binary)
Analog Ground (Connect to a low thermal
impedance analog ground plane with multiple
vias)
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). SDR is the default state at power-up for
the 72 pin package.
4
FN6807.4
October 1, 2010
KAD5512P
Pin Configuration
AVSS
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D5P
D5N
OVDD
KAD5512P
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
AVDD 1
36 D4P
DNC
2
35 D4N
DNC
3
34 D3P
DNC
4
33 D3N
AVSS
5
32 CLKOUTP
VINN 6
31 CLKOUTN
PAD
VINP 7
AVSS
30 RLVDS
8
29 OVSS
AVDD 9
28 D2P
VCM 10
27 D2N
DNC 11
26 D1P
CONNECT THERMAL PAD TO AVSS
AVSS 12
20
RESETN
OVSS
OVDD
21
22
23
24
D0P
19
D0N
18
DNC
17
DNC
16
AVDD
CLKP
15
NAPSLP
14
CLKN
13
AVDD
25 D1N
FIGURE 2. PIN CONFIGURATION
5
FN6807.4
October 1, 2010
KAD5512P
Pin Descriptions - 48 Ld QFN
PIN NUMBER
LVDS [LVCMOS] NAME
1, 9, 13, 17, 47
AVDD
LVDS [LVCMOS] FUNCTION
1.8V Analog Supply
2-4, 11, 21, 22
DNC
Do Not Connect
5, 8, 12, 48
AVSS
Analog Ground
6, 7
VINN, VINP
10
VCM
14, 15
CLKP, CLKN
16
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
18
RESETN
Power On Reset (Active Low, see page 19)
Analog Input Negative, Positive
Common Mode Output
Clock Input True, Complement
19, 29, 42
OVSS
Output Ground
20, 37
OVDD
1.8V Output Supply
23
D0N
[NC]
LVDS DDR Logical Bits 1, 0 Output Complement
[NC in LVCMOS]
24
D0P
[D0]
LVDS DDR Logical Bits 1, 0 Output True
[CMOS DDR Logical Bits 1, 0 in LVCMOS]
25
D1N
[NC]
LVDS DDR Logical Bits 3, 2 Output Complement
[NC in LVCMOS]
26
D1P
[D1]
LVDS DDR Logical Bits 3, 2 Output True
[CMOS DDR Logical Bits 3, 2 in LVCMOS]
27
D2N
[NC]
LVDS DDR Logical Bits 5, 4 Output Complement
[NC in LVCMOS]
28
D2P
[D2]
LVDS DDR Logical Bits 5, 4 Output True
[CMOS DDR Logical Bits 5, 4 in LVCMOS]
30
RLVDS
31
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
32
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
33
D3N
[NC]
LVDS DDR Logical Bits 7, 6 Output Complement
[NC in LVCMOS]
34
D3P
[D3]
LVDS DDR Logical Bits 7, 6 Output True
[CMOS DDR Logical Bits 7, 6 in LVCMOS]
35
D4N
[NC]
LVDS DDR Logical Bits 9, 8 Output Complement
[NC in LVCMOS]
36
D4P
[D4]
LVDS DDR Logical Bits 9, 8 Output True
[CMOS DDR Logical Bits 9, 8 in LVCMOS]
38
D5N
[NC]
LVDS DDR Logical Bits 11, 10 Output Complement
[NC in LVCMOS]
39
D5P
[D5]
LVDS DDR Logical Bits 11, 10 Output True
[CMOS DDR Logical Bits 11, 10 in LVCMOS]
40
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
41
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
43
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
44
CSB
SPI Chip Select (active low)
45
SCLK
SPI Clock
46
SDIO
SPI Serial Data Input/Output
PAD
(Exposed Paddle)
AVSS
Analog Ground (Connect to a low thermal impedance analog
ground plane with multiple vias)
LVDS Bias Resistor (Connect to OVSS with a 10kΩ, 1% resistor)
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).
6
FN6807.4
October 1, 2010
KAD5512P
Ordering Information
PART NUMBER
(Note 3)
PART
MARKING
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
KAD5512P-25Q72 (Note 1)
KAD5512P-25 Q72EP-I
250
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512P-21Q72 (Note 1)
KAD5512P-21 Q72EP-I
210
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512P-17Q72 (Note 1)
KAD5512P-17 Q72EP-I
170
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512P-12Q72 (Note 1)
KAD5512P-12 Q72EP-I
125
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512P-25Q48 (Note 2)
KAD5512P-25 Q48EP-I
250
-40 to +85
48 Ld QFN
L48.7x7E
KAD5512P-21Q48 (Note 2)
KAD5512P-21 Q48EP-I
210
-40 to +85
48 Ld QFN
L48.7x7E
KAD5512P-17Q48 (Note 2)
KAD5512P-17 Q48EP-I
170
-40 to +85
48 Ld QFN
L48.7x7E
KAD5512P-12Q48 (Note 2)
KAD5512P-12 Q48EP-I
125
-40 to +85
48 Ld QFN
L48.7x7E
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for KAD5512P. For more information on MSL please
see techbrief TB363.
7
FN6807.4
October 1, 2010
KAD5512P
Table of Contents
Serial Peripheral Interface .............................. 24
Digital Specifications ...................................... 12
SPI Physical Interface ....................................
SPI Configuration ..........................................
Device Information ........................................
Indexed Device Configuration/Control ..............
Global Device Configuration/Control .................
Device Test...................................................
72 Pin/48 Pin Package Options ........................
SPI Memory Map ...........................................
Timing Diagrams ............................................. 13
Equivalent Circuits .......................................... 30
Switching Specifications .................................. 14
ADC Evaluation Platform ................................. 31
Typical Performance Curves ............................ 15
Layout Considerations..................................... 31
Absolute Maximum Ratings .............................. 9
Thermal Information ........................................ 9
Recommended Operating Conditions ................ 9
Electrical Specifications. ................................... 9
Theory of Operation......................................... 18
Functional Description.....................................
Power-On Calibration ......................................
User-Initiated Reset .......................................
Analog Input .................................................
VCM Output...................................................
Clock Input ...................................................
Jitter ............................................................
Voltage Reference ..........................................
Digital Outputs ..............................................
Over Range Indicator......................................
Power Dissipation...........................................
Nap/Sleep .....................................................
Data Format ..................................................
18
18
19
19
20
20
20
21
21
21
21
21
22
PCB Layout Example ......................................
Split Ground and Power Planes ........................
Clock Input Considerations .............................
Exposed Paddle .............................................
Bypass and Filtering.......................................
LVDS Outputs ...............................................
LVCMOS Outputs ...........................................
Unused Inputs ..............................................
24
24
25
25
26
27
27
28
31
31
31
31
31
31
31
31
General PowerPAD Design Considerations ...... 31
Definitions....................................................... 32
Revision History .............................................. 33
Products.......................................................... 34
Package Outline Drawing ............................... 35
Package Outline Drawing ............................... 36
8
FN6807.4
October 1, 2010
KAD5512P
Absolute Maximum Ratings
AVDD to AVSS . . . . . .
OVDD to OVSS. . . . . .
AVSS to OVSS . . . . . .
Analog Inputs to AVSS
Clock Inputs to AVSS .
Logic Input to AVSS . .
Logic Inputs to OVSS .
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Thermal Information
. . . . . . -0.4V to
. . . . . . -0.4V to
. . . . . . -0.3V to
-0.4V to AVDD +
-0.4V to AVDD +
-0.4V to OVDD +
-0.4V to OVDD +
2.1V
2.1V
0.3V
0.3V
0.3V
0.3V
0.3V
Thermal Resistance (Typical)
48 Ld QFN (Notes 4, 5) .
72 Ld QFN (Note 4, 5) .
Storage Temperature . . . .
Junction Temperature . . .
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θJA (°C/W) θJC (°C/W)
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25
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24
. . . . . -65°C to
............
0.5
0.5
+150°C
+150°C
Recommended Operating Conditions
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V
OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V
Temperature. . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS,
fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the
operating temperature range, -40°C to +85°C.
KAD5512P-25
(Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
KAD5512P-21
(Note 6)
MAX MIN
TYP
KAD5512P-17
(Note 6)
MAX MIN
TYP
KAD5512P-12
(Note 6)
MAX MIN
TYP
MAX UNITS
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog
Input Range
VFS
Differential
Input Resistance
RIN
Differential
1000
1000
1000
1000
Ω
Input
Capacitance
CIN
Differential
1.8
1.8
1.8
1.8
pF
Full Temp
90
90
90
90
ppm/°C
Full Scale Range
Temp. Drift
AVTC
Input Offset
Voltage
VOS
Gain Error
1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54
-10
EG
Common-Mode
Output Voltage
VCM
Common-Mode
Input Current
(per pin)
ICM
±2
10
-10
±0.6
435
535
±2
10
-10
±0.6
635
435
535
±2
10
-10
±0.6
635
435
535
±2
10
±0.6
635
435
535
VP-P
mV
%
635
mV
2.5
2.5
2.5
2.5
μA/
MSPS
Inputs Common
Mode Voltage
0.9
0.9
0.9
0.9
V
CLKP,CLKN Input
Swing
1.8
1.8
1.8
1.8
V
Clock Inputs
Power Requirements
1.8V Analog
Supply Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital
Supply Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
9
FN6807.4
October 1, 2010
KAD5512P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS,
fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
KAD5512P-25
(Note 6)
PARAMETER
SYMBOL
1.8V Analog
Supply Current
IAVDD
1.8V Digital
Supply Current
(SDR) (Note 7)
I
OVDD
1.8V Digital
Supply Current
(DDR) (Note 7)
Power Supply
Rejection Ratio
CONDITIONS
MIN
TYP
KAD5512P-21
(Note 6)
MAX MIN
TYP
KAD5512P-17
(Note 6)
MAX MIN
TYP
KAD5512P-12
(Note 6)
MAX MIN
TYP
MAX UNITS
90
96
83
89
77
82
69
74
mA
3mA LVDS
58
62
56
60
54
58
52
56
mA
I
OVDD
3mA LVDS
39
38
36
35
mA
PSRR
30MHz, 200mVP-P
signal on AVDD
-36
-36
-36
-36
dB
Total Power Dissipation
Normal Mode
(SDR)
PD
3mA LVDS
267
Normal Mode
(DDR)
PD
3mA LVDS
234
Nap Mode
PD
Sleep Mode
PD
286
252
271
237
219
253
219
204
235
189
mW
mW
84
95
80
91
78
88
74
84
mW
CSB at logic high
2
6
2
6
2
6
2
6
mW
Nap Mode
Wakeup Time
(Note 8)
Sample Clock
Running
1
1
1
1
µs
Sleep Mode
Wakeup Time
(Note 8)
Sample Clock
Running
1
1
1
1
ms
AC SPECIFICATIONS
Differential
Nonlinearity
DNL
-0.8
±0.3
0.8
-0.8
±0.3
0.8
-0.8
±0.3
0.8
-0.8
±0.3
0.8
LSB
Integral
Nonlinearity
INL
-2.0
±0.8
2.0
-2.0
±1.1
2.0
-2.0
±1.1
2.0
-2.5
±1.4
2.5
LSB
40
MSPS
Minimum
Conversion Rate
(Note 9)
fS MIN
Maximum
Conversion Rate
fS MAX
Signal-to-Noise
Ratio
SNR
40
250
fIN = 10MHz
40
210
40
170
125
MSPS
66.1
66.6
66.9
67.1
dBFS
fIN = 105MHz
64.0 66.1
64.5 66.6
65.0 66.9
65.2 67.1
dBFS
fIN = 190MHz
65.9
66.3
66.7
66.8
dBFS
fIN = 364MHz
65.4
65.7
66.1
66.1
dBFS
fIN = 695MHz
63.8
64.2
64.4
64.1
dBFS
fIN = 995MHz
62.6
62.4
62.7
62.4
dBFS
10
FN6807.4
October 1, 2010
KAD5512P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS,
fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
KAD5512P-25
(Note 6)
PARAMETER
Signal-to-Noise
and Distortion
Effective Number
of Bits
Spurious-Free
Dynamic Range
Intermodulation
Distortion
SYMBOL
SINAD
ENOB
SFDR
CONDITIONS
fIN = 10MHz
TYP
MAX MIN
TYP
KAD5512P-17
(Note 6)
MAX MIN
TYP
KAD5512P-12
(Note 6)
MAX MIN
TYP
MAX UNITS
65.3
65.6
65.8
66.3
dBFS
fIN = 105MHz
63.3 65.3
63.8 65.6
64.3 65.8
64.3 66.3
dBFS
fIN = 190MHz
64.6
65.2
65.5
65.6
dBFS
fIN = 364MHz
63.9
64.3
64.7
64.1
dBFS
fIN = 695MHz
56.9
57.2
57.9
57.4
dBFS
fIN = 995MHz
49.6
44.9
48.3
49.3
dBFS
fIN = 10MHz
10.6
10.6
10.6
10.7
Bits
fIN = 105MHz
10.3 10.6
10.4 10.6
10.5 10.6
10.5 10.7
Bits
fIN = 190MHz
10.4
10.5
10.6
10.6
Bits
fIN = 364MHz
10.3
10.4
10.5
10.4
Bits
fIN = 695MHz
9.2
9.2
9.3
9.2
Bits
fIN = 995MHz
7.9
7.2
7.7
7.9
Bits
83.0
81.4
78.8
79.6
dBc
86
dBc
fIN = 10MHz
fIN = 105MHz
IMD
MIN
KAD5512P-21
(Note 6)
70
87
70
86.2
70
84.4
70
fIN = 190MHz
79.4
80.5
81.8
82.0
dBc
fIN = 364MHz
76.1
76.1
78.2
71.8
dBc
fIN = 695MHz
60.6
61.4
61.6
61.6
dBc
fIN = 995MHz
50.7
46.4
49.2
50.3
dBc
fIN = 70MHz
-85.7
-92.1
-94.5
-95.1
dBFS
fIN = 170MHz
-97.1
-87.1
-91.6
-85.7
dBFS
10-12
10-12
10-12
1.5
1.5
1.5
Word Error Rate
WER
10-12
Full Power
Bandwidth
FPBW
1.5
GHz
NOTES:
6. Parameters with MIN and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C).
7. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on
each digital output.
8. See Nap /Sleep Mode description on page 21 for more details.
9. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 24 for more detail.
11
FN6807.4
October 1, 2010
KAD5512P
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
0
1
10
µA
-25
-12
-5
µA
INPUTS
Input Current High (SDIO, RESETN, CSB, SCLK)
IIH
VIN = 1.8V
Input Current Low (SDIO, RESETN, CSB, SCLK)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN, CSB, SCLK)
VIH
Input Voltage Low (SDIO, RESETN, CSB, SCLK)
VIL
Input Current High (OUTMODE, NAPSLP, CLKDIV,
OUTFMT) (Note 10)
IIH
15
Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT)
IIL
-40
Input Capacitance
CDI
1.17
V
.63
V
25
40
µA
25
-15
µA
3
pF
620
mVP-P
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
950
965
980
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
12
FN6807.4
October 1, 2010
KAD5512P
Timing Diagrams
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
CLKOUTN
CLKOUTP
tDC
tDC
tPD
D[10/8/6/4/2/0]P
ODD BITS
N-L
D[10/8/6/4/2/0]N
LATENCY = L CYCLES
EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS
N-L + 1
N-L + 1
N-L + 2
N-L + 2
N-L
EVEN BITS
N
tPD
D[11/0]P
D[11/0]N
DATA
N-L
FIGURE 3A. DDR
DATA
N-L + 1
DATA
N
FIGURE 3B. SDR
FIGURE 3. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 21)
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
LATENCY = L CYCLES
tCPD
CLKOUT
CLKOUT
tDC
tDC
tPD
D[10/8/6/4/2/0]
ODD BITS
N-L
LATENCY = L CYCLES
EVEN BITS ODD BITS
N-L
N-L + 1
EVEN BITS ODD BITS EVEN BITS
N-L + 1
N-L + 2
N-L + 2
FIGURE 4A. DDR
EVEN BITS
N
tPD
D[11/0]
DATA
N-L
DATA
N-L + 1
DATA
N
FIGURE 4B. SDR
FIGURE 4. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 21)
13
FN6807.4
October 1, 2010
KAD5512P
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
Output Clock to Data Propagation
Delay, LVDS Mode (Note 11)
Output Clock to Data Propagation
Delay, CMOS Mode (Note 11)
DDR Rising Edge
tDC
-260
-50
120
ps
DDR Falling Edge
tDC
-160
10
230
ps
SDR Falling Edge
tDC
-260
-40
230
ps
DDR Rising Edge
tDC
-220
-10
200
ps
DDR Falling Edge
tDC
-310
-90
110
ps
SDR Falling Edge
tDC
-310
-50
200
ps
Latency (Pipeline Delay)
Overvoltage Recovery
L
7.5
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 12, 13)
SCLK Period
Write Operation
t
CLK
16
cycles
(Note 12)
Read Operation
tCLK
66
cycles
SCLK Duty Cycle (tHI/tCLK or tLO/tCLK)
Read or Write
CSB↓ to SCLK↑ Setup Time
Read or Write
tS
1
cycles
CSB↑ after SCLK↑ Hold Time
Read or Write
tH
3
cycles
Data Valid to SCLK↑ Setup Time
Write
tDSW
1
cycles
Data Valid after SCLK↑ Hold Time
Write
tDHW
3
cycles
Data Valid after SCLK↓ Time
Read
tDVR
Data Invalid after SCLK↑ Time
Read
tDHR
3
cycles
Sleep Mode CSB↓ to SCLK↑ Setup
Time (Note 14)
Read or Write in Sleep Mode
tS
150
µs
25
50
75
16.5
%
cycles
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to
ground or AVDD depending on desired function.
11. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data
capture for most applications. Contact factory for more info if needed.
12. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps).
13. The SPI may operate asynchronously with respect to the ADC sample clock.
14. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal
mode CSB setup time (4ns min).
14
FN6807.4
October 1, 2010
KAD5512P
Typical Performance Curves
All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate
(per speed grade).
-50
85
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
SFDR @ 125MSPS
80
75
SNR @ 125MSPS
70
65
60
SNR @ 250MSPS
55
SFDR @ 250MSPS
-55
-60
0
200M
400M
600M
800M
HD2 @ 250MSPS
-70
-75
-80
-85
HD3 @ 125MSPS
-90
-95
-100
50
HD2 @ 125MSPS
-65
1G
HD3 @ 250MSPS
0
200M
-20
90
-30
SNR AND SFDR
HD2 & HD3 MAGNITUDE
100
SFDRFS (dBFS)
70
60
50
SNRFS (dBFS)
40
30
SFDR (dBc)
20
SNR (dBc)
10
0
-60
-50
-30
-20
-60
HD3 (dBc)
-70
HD2 (dBFS)
-80
-90
-100
-10
HD3 (dBFS)
-120
-60
0
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
FIGURE 7. SNR AND SFDR vs AIN
FIGURE 8. HD2 AND HD3 vs AIN
-60
90
HD2 AND HD3 MAGNITUDE (dBc)
95
SNR (dBFS) AND SFDR (dBc)
1G
-50
INPUT AMPLITUDE (dBFS)
SFDR
85
80
75
70
SNR
65
60
40
800M
HD2 (dBc)
-40
-110
-40
600M
FIGURE 6. HD2 AND HD3 vs fIN
FIGURE 5. SNR AND SFDR vs fIN
80
400M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
70
100
130
160
190
220
SAMPLE RATE (MSPS)
FIGURE 9. SNR AND SFDR vs fSAMPLE
15
250
-70
HD3
-80
-90
-100
HD2
-110
-120
40
70
100
130
160
190
220
250
SAMPLE RATE (MSPS)
FIGURE 10. HD2 AND HD3 vs fSAMPLE
FN6807.4
October 1, 2010
KAD5512P
Typical Performance Curves
All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate
(per speed grade). (Continued)
1.5
300
250
1.0
200
0.5
DNL (LSBs)
TOTAL POWER (mW)
SDR
150
DDR
100
-0.5
50
0
0
-1.0
40
70
100
130
160
190
220
-1.5
250
0
512
1024
1536
SAMPLE RATE (MSPS)
1.5
SNR (dBFS) & SFDR (dBc)
INL (LSBs)
3072
3584
4096
90
1.0
0.5
0
-0.5
-1.0
0
512
1024
1536
2048
2560
3072
3584
85
SFDR
80
75
70
65
SNR
60
55
50
300
4096
400
CODE
500
600
800
FIGURE 14. SNR AND SFDR vs VCM
270000
0
AIN = -1.0dBFS
SNR = 66.0dBFS
SFDR = 82.5dBc
SINAD = 65.9dBFS
240000
-20
AMPLITUDE (dBFS)
210000
180000
150000
120000
90000
60000
-40
-60
-80
-100
30000
0
2050
700
INPUT COMMON MODE (mV)
FIGURE 13. INTEGRAL NONLINEARITY
NUMBER OF HITS
2560
FIGURE 12. DIFFERENTIAL NONLINEARITY
FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS MODE
-1.5
2048
CODE
2051
2052
2053
2054
2055
2056
CODE
FIGURE 15. NOISE HISTOGRAM
16
2057
2058
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 16. SINGLE-TONE SPECTRUM @ 10MHz
FN6807.4
October 1, 2010
KAD5512P
Typical Performance Curves
All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate
(per speed grade). (Continued)
0
AIN = -1.0dBFS
SNR = 65.7dBFS
SFDR = 79.2dBc
SINAD = 65.4dBFS
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
0
AIN = -1.0dBFS
SNR = 66.0dBFS
SFDR = 86.5dBc
SINAD = 65.9dBFS
-40
-60
-80
-40
-60
-80
-100
-100
-120
0
20
40
60
80
100
120
-120
0
20
FIGURE 17. SINGLE-TONE SPECTRUM @ 105MHz
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
-40
-60
-80
100
120
AIN = -1.0dBFS
SNR = 61.6dBFS
SFDR = 49.8dBc
SINAD = 49.8dBFS
-40
-60
-80
-100
-100
0
20
40
60
80
100
-120
0
120
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 19. SINGLE-TONE SPECTRUM @ 495MHz
FIGURE 20. SINGLE-TONE SPECTRUM @ 995MHz
0
0
IMD = -85.7dBFS
IMD = -97.1dBFS
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
80
0
AIN = -1.0dBFS
SNR = 64.4dBFS
SFDR = 68.8dBc
SINAD = 62.6dBFS
-20
-40
-60
-80
-40
-60
-80
-100
-100
-120
60
FIGURE 18. SINGLE-TONE SPECTRUM @ 190MHz
0
-120
40
FREQUENCY (MHz)
FREQUENCY (MHz)
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 21. TWO-TONE SPECTRUM @ 70MHz
17
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 22. TWO-TONE SPECTRUM @ 170MHz
FN6807.4
October 1, 2010
KAD5512P
Theory of Operation
A user-initiated reset can subsequently be invoked in the
event that the previously mentioned conditions cannot
be met at power-up.
Functional Description
The KAD5512P is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 23). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted
to a unit of charge. Proprietary charge-domain techniques
are used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for
each input value. The converter pipeline requires six
samples to produce a result. Digital error correction is also
applied, resulting in a total latency of seven and one half
clock cycles. This is evident to the user as a time lag
between the start of a conversion and the data being
available on the digital outputs.
The SDO pin requires an external 4.7kΩ pull-up to OVDD.
If the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
Power-On Calibration
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 24. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output
returns to normal operation at that time, so it is important
that the analog input be within the converter’s full-scale
range to observe the transition. If the input is in an overrange condition, the OR pin will stay high, and it will not be
possible to detect the end of the calibration cycle.
The ADC performs a self-calibration at start-up. An
internal power-on-reset (POR) circuit detects the supply
voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold.
The following conditions must be adhered to for the
power-on calibration to execute successfully:
• A frequency-stable conversion clock must be applied
to the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled
up or down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
After the power supply has stabilized, the internal POR
releases RESETN and an internal pull-up pulls it high
starting the calibration sequence. When the RESETN pin
is driven by external logic, it should be connected to an
open-drain output with open-state leakage of less than
0.5mA to assure exit from the reset state. A driver that
can be switched from logic low to high impedance can
also be used to drive RESETN provided the high
impedance state leakage is less than 0.5mA and the
logic voltages are the same.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 250MSPS
the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
• SPI communications must not be attempted
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 23. ADC CORE BLOCK DIAGRAM
18
FN6807.4
October 1, 2010
KAD5512P
CLKN
CLKP
RESETN
CALIBRATION
BEGINS
ORP
CALIBRATION
COMPLETE
SNR CHANGE (dBfs)
3
CALIBRATION
TIME
CAL DONE AT
+85°C
2
1
0
-1
-2
-3
-4
-40
CLKOUTP
CAL DONE AT
+25°C
CAL DONE AT
-40°C
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 24. CALIBRATION TIMING
FIGURE 25. SNR PERFORMANCE vs TEMPERATURE
15
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with less than 0.5mA
open-state leakage is recommended so the internal high
impedance pull-up to OVDD can assure exit from the reset
state. As is the case during power-on reset, the SDO,
RESETN and DNC pins must be in the proper state for the
calibration to successfully execute.
The performance of the KAD5512P changes with
variations in temperature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the ADC under the environmental conditions
at which it will operate.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less than
75MSPS will typically result in an SNR change of less than
0.5dBFS and an SFDR change of less than 3dBc.
Figures 25 and 26 show the effect of temperature on
SNR and SFDR performance with calibration performed
at -40°C, +25°C, and +85°C. Each plot shows the
variation of SNR/SFDR across temperature after a single
calibration at -40°C, +25°C and +85°C. Best
performance is typically achieved by a user-initiated
calibration at the operating conditions, as stated earlier.
However, it can be seen that performance drift with
temperature is not a very strong function of the
temperature at which the calibration is performed. Fullrated performance will be achieved after power-up
calibration regardless of the operating conditions.
SFDR CHANGE (dBc)
User-Initiated Reset
CAL DONE AT
-40°C
10
5
0
-5
CAL DONE AT
+85°C
-10
-15
-40
-15
10
35
TEMPERATURE (°C)
CAL DONE AT
+25°C
60
85
FIGURE 26. SFDR PERFORMANCE vs TEMPERATURE
Analog Input
The ADC core contains a fully differential input
(VINP/VINN) to the sample and hold amplifier (SHA). The
ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 27.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 28 through 30. An RF transformer will
give the best noise and distortion performance for
wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 28 and 29.
1.8
1.4
1.0
0.6
INN
0.725V
INP
VCM
0.535V
0.2
FIGURE 27. ANALOG INPUT RANGE
19
FN6807.4
October 1, 2010
KAD5512P
This dual transformer scheme is used to improve commonmode rejection, which keeps the common-mode level of
the input matched to VCM. The value of the shunt resistor
should be determined based on the desired load
impedance. The differential input resistance of the
KAD5512P is 1000Ω.
ADT1-1WT
ADT1-1WT
1000pF
KAD5512P
0.1µF
FIGURE 28. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADTL1-12
ADTL1-12
0.1µF
KAD5512P
1000pF
The SHA design uses a switched capacitor input stage
(see Figure 43), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance
will result in faster settling and improved performance.
Therefore a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
348Ω
69.8Ω
The clock input circuit is a differential pair (see
Figure 44). Driving these inputs with a high level (up to
1.8VPP on each input) sine or square wave will provide
the lowest jitter performance. A transformer with 4:1
impedance ratio will provide increased drive levels.
The recommended drive circuit is shown in Figure 31. A
duty range of 40% to 60% is acceptable. The clock can
be driven single-ended, but this will reduce the edge rate
and may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC coupling.
200pF
TC4-1W
CM
217Ω
200pF
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series
with the clock input. The divider can be used in the 2x
mode with a sample clock equal to twice the desired
sample rate. This allows the use of the Phase Slip
feature, which enables synchronization of multiple ADCs.
TABLE 1. CLKDIV PIN SETTINGS
KAD5512P
25Ω
69.8Ω
348Ω
0.1µF
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in Figure 30, can be
used in applications that require DC-coupling. In this
configuration, the amplifier will typically dominate the
achievable SNR and distortion performance.
The current spikes from the SHA will try to force the
analog input pins toward ground. In cases where the
input pins are biased with more than 50Ω in series from
VCM care must be taken to make sure the input common
mode range is not violated. The provided ICM value
(250µA/MHz * 250MHz = 625µA at 250MSPS) may be
20
Ω
200O
CLKN
VCM
100Ω
CLKP
1000pF
200pF
25Ω
100Ω
49.9Ω
The VCM output is buffered with a series output
impedance of 20Ω. It can easily drive a typical ADC
driver’s 10kΩ common mode control pin. If an external
buffer is not used the voltage drop across the internal
20Ω impedance must be considered when calculating the
expected DC bias voltage at the analog input pins.
VCM
FIGURE 29. TRANSMISSION-LINE TRANSFORMER
INPUT FOR HIGH IF APPLICATIONS
0.22µF
VCM Output
Clock Input
VCM
1000pF
used to calculate the expected voltage drop across any
series resistance.
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 24.
A delay-locked loop (DLL) generates internal clock
signals for various stages within the charge pipeline. If
the frequency of the input clock changes, the DLL may
take up to 52µs to regain lock at 250MSPS. The lock time
is inversely proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly impacts
the achievable SNR performance. The theoretical
relationship between clock jitter (tJ) and SNR is shown in
Equation 1 and is illustrated in Figure 32.
FN6807.4
October 1, 2010
KAD5512P
1
SNR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
(EQ. 1)
IN J
100
TABLE 2. OUTMODE PIN SETTINGS
95
tj = 0.1ps
90
14 BITS
SNR (dB)
85
80
tj = 1ps
75
12 BITS
70
tj = 10ps
65
60
10 BITS
tj = 100ps
55
50
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
1
10
100
INPUT FREQUENCY (MHz)
1000
FIGURE 32. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved
if clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal
aperture jitter is the uncertainty in the sampling instant
shown in Figure 3. The internal aperture jitter combines
with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or
single data rate (SDR) formats. The even numbered data
output pins are active in DDR mode in the 72 pin
package option. When CLKOUT is low the MSB and all
odd logical bits are output, while on the high phase the
LSB and all even logical bits are presented (this is true in
both the 72 pin and 48 pin package options). Figures 3
and 4 show the timing relationships for LVDS/CMOS and
DDR/SDR modes.
The 48-QFN package option contains six LVDS data
output pin pairs, and therefore can only support DDR
mode.
Additionally, the drive current for LVDS mode can be set
to a nominal 3mA or a power-saving 2mA. The lower
current setting can be used in designs where the receiver
is in close physical proximity to the ADC. The applicability
of this setting is dependent upon the PCB layout,
therefore the user should experiment to determine if
performance degradation is observed.
21
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details
on this are contained in “Serial Peripheral Interface” on
page 24.
An external resistor creates the bias for the LVDS drivers.
A 10kΩ, 1% resistor must be connected from the RLVDS
pin to OVSS.
Over Range Indicator
The over range (OR) bit is asserted when the output
code reaches positive full-scale (e.g. 0xFFF in offset
binary mode). The output code does not wrap around
during an over-range condition. The OR bit is updated at
the sample rate.
Power Dissipation
The power dissipated by the KAD5512P is primarily
dependent on the sample rate and the output modes:
LVDS vs. CMOS and DDR vs SDR. There is a static bias in
the analog supply, while the remaining power dissipation
is linearly related to the sample rate. The output supply
dissipation is approximately constant in LVDS mode, but
linearly related to the clock frequency in CMOS mode.
Figures 36 and 37 illustrate these relationships.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required.
Two power saving modes are available: Nap, and Sleep.
Nap mode reduces power dissipation to less than 95mW
and recovers to normal operation in approximately 1µs.
Sleep mode reduces power dissipation to less than 6mW
but requires approximately 1ms to recover from a sleep
command.
Wake-up time from sleep mode is dependent on the state
of CSB; in a typical application CSB would be held high
during sleep, requiring a user to wait 150µs max after
CSB is asserted (brought low) prior to writing ‘001x’ to
SPI Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
FN6807.4
October 1, 2010
KAD5512P
In an application where CSB was kept low in sleep
mode, the 150µs CSB setup time is not required as the
SPI registers are powered on when CSB is low, the chip
power dissipation increases by ~ 15mW in this case.
The 1ms wake-up time after the write of a ‘001x’ to
register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional
SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input
clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. Recovery
time from Nap mode will increase if the clock is stopped,
since the internal DLL can take up to 52µs to regain lock
at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
Offset binary coding maps the most negative input voltage
to code 0x000 (all zeros) and the most positive input to
0xFFF (all ones). Two’s complement coding simply
complements the MSB of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current
bit position and the next most significant bit. Figure 33
shows this operation.
BINARY
11
10
9
••••
1
0
••••
GRAY CODE
11
10
••••
9
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 34.
GRAY CODE
11
10
9
The power-down mode can also be controlled through
the SPI port, which overrides the NAPSLP pin setting.
Details on this are contained in “Serial Peripheral
Interface” on page 24. This is an indexed function when
controlled from the SPI, but a global function when
driven from the pin.
••••
1
0
••••
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format
is selected via the OUTFMT pin as shown in Table 4.
••••
TABLE 4. OUTFMT PIN SETTINGS
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
The data format can also be controlled through the SPI
port, which overrides the OUTFMT pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 24.
BINARY
11
10
9
••••
1
0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats
is shown in Table 5.
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT VOLTAGE
OFFSET BINARY
TWO’S COMPLEMENT
GRAY CODE
–Full Scale
000 00 000 00 00
100 00 000 00 00
000 00 000 00 00
–Full Scale + 1LSB
000 00 000 00 01
100 00 000 00 01
000 00 000 00 01
Mid–Scale
100 00 000 00 00
000 00 000 00 00
110 00 000 00 00
+Full Scale – 1LSB
111 11 111 11 10
011 11 111 11 10
100 00 000 00 01
+Full Scale
111 11 111 11 11
011 11 111 111 1
100 00 000 00 00
22
FN6807.4
October 1, 2010
KAD5512P
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1D
0
D3
D4
D5
D6
D7
FIGURE 35. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D1
D0
D2
FIGURE 36. LSB-FIRST ADDRESSING
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 37. SPI WRITE
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tDHR
tDVR
tLO
SCLK
WRITING A READ COMMAND
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
READING DATA (3 WIRE MODE)
A0
D7
D6
SDO
D3
D2
D1 D0
(4 WIRE MODE)
D7
D3
D2
D1 D0
SPI READ
FIGURE 38. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 39. 2-BYTE TRANSFER
23
FN6807.4
October 1, 2010
KAD5512P
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 40. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to
facilitate configuration of the device and to optimize
performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) serial data output (SDO), and serial
data input/output (SDIO). The maximum SCLK rate is
equal to the ADC sample rate (fSAMPLE) divided by 16
for write operations and fSAMPLE divided by 66 for
reads. At fSAMPLE = 250MHz, maximum SCLK is
15.63MHz for writing and 3.79MHz for read operations.
There is no minimum SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there
may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values
within defined registers are reserved and should not be
selected. Setting any reserved register or value may
produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for
the data transfer. By default, all data is presented on the
serial data input/output (SDIO) pin in three-wire mode.
The state of the SDIO pin is set automatically in the
communication protocol (described below). A dedicated
serial data output pin (SDO) can be activated by setting
0x00[7] high to allow operation in four-wire mode.
SDO should always be connected to OVDD with a 4.7kΩ
resistor even if not used. If the 4.7kΩ resistor is not
present the ADC will not exit the reset state.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5512P functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four-wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire
mode). If multiple slave devices are selected for reading
at the same time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
24
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data
can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by
setting 0x00[6] high. Figures 35 and 36 show the
appropriate bit ordering for the MSB-first and LSB-first
modes, respectively. In MSB-first mode the address is
incremented for multi-byte transfers, while in LSB-first
mode it’s decremented.
In the default mode, the MSB is R/W, which determines if
the data is to be read (active high) or written. The next
two bits, W1 and W0, determine the number of data
bytes to be read or written (see Table 6). The lower 13
bits contain the first address for the data transfer. This
relationship is illustrated in Figure 37, and timing values
are given in “Switching Specifications” on page 14.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read
from the ADC (based on the R/W bit status). The data
transfer will continue as long as CSB remains low and
SCLK is active. Stalling of the CSB pin is allowed at any
byte boundary (instruction/address or data) if the
number of bytes being transferred is three or less. For
transfers of four bytes or more, CSB is allowed stall in
the middle of the instruction/address bytes or before the
first data byte. If CSB transitions to a high state after
that point the state machine will reset and terminate the
data transfer.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 39 and 40 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for
a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit
order can be selected as MSB to LSB (MSB first) or LSB to
MSB (LSB first) to accommodate various microcontrollers.
FN6807.4
October 1, 2010
KAD5512P
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret
serial data as arriving in LSB to MSB order.
Bit 5 Soft Reset
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
TABLE 7. OFFSET ADJUSTMENTS
Setting this bit high resets all SPI registers to default
values.
Bit 4 Reserved
This bit should always be set high.
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
–Full Scale (0x00) -133LSB (-47mV)
-5LSB (-1.75mV)
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB
(+47mV)
+5LSB (+1.75mV)
ADDRESS 0X02: BURST_END
Nominal Step Size 1.04LSB (0.37mV)
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redundant
addressing. In 3-wire SPI mode the burst is ended by
pulling the CSB pin high. If the device is operated in 2wire mode the CSB pin is not available. In that case,
setting the burst_end address determines the end of the
transfer. During a write operation, the user must be
cautious to transmit the correct number of bytes based
on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of
the burst data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed
on a per-converter basis. This register determines which
converter is being addressed for an Indexed command. It
is important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Therefore Bit 0 must be set high in order to
execute any Indexed commands. Error code ‘AD’ is
returned if any indexed register is read from without
properly setting device_index_A.
0.04LSB
(0.014mV)
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Gain of the ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit
adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment
range of ±4.2% (‘0011’ =~ -4.2% and
‘1100’ =~ +4.2%). It is recommended to use one of
the coarse gain settings (-4.2%, -2.8%, -1.4%, 0,
1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 23h and 24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
ADDRESS 0X21: OFFSET_FINE
Mid–Scale (0x80)
0.00%
0.00%
The input offset of the ADC core can be adjusted in fine
and coarse steps. Both adjustments are made via an 8bit word as detailed in Table 7.
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X20: OFFSET_COARSE AND
25
FN6807.4
October 1, 2010
KAD5512P
ADDRESS 0X25: MODES
CLK = CLKP – CLKN
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation or sleep modes (refer to “Nap/Sleep” on
page 21). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
TABLE 10. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
CLK
1.00ns
CLK÷4
4.00ns
CLK÷4
SLIP ONCE
CLK÷4
SLIP TWICE
FIGURE 41. PHASE SLIP: CLK÷4 MODE, fCLOCK =
1000MHz
ADDRESS 0X72: CLOCK_DIVIDE
SEQUENCE
REGISTER
VALUE
The KAD5512P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default,
the tri-level CLKDIV pin selects the divisor (refer to “VCM
Output” on page 20). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
1
0x10
0x01
TABLE 11. CLOCK DIVIDER SELECTION
2
0x25
0x02
3
0x10
0x02
4
0x25
0x02
Nap mode must be entered by executing the following
sequence:
Return to Normal operation as follows:
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
2
0x25
0x01
3
0x10
0x02
4
0x25
0x01
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to
determine the synchronization of the incoming and
divided clock phases. This is particularly important when
multiple ADCs are used in a time-interleaved system.
The phase slip feature allows the rising edge of the
divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 41. Execution
of a phase_slip command is accomplished by first writing
a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit
0 at address 71h (32 sclk cycles).
26
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 21). This functionality can be overridden and
controlled through the SPI, as shown in Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 22). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
TABLE 12. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
FN6807.4
October 1, 2010
KAD5512P
TABLE 13. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 17.
TABLE 15. OUTPUT TEST MODES
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default)
or slow.
Internal clock signals are generated by a delay-locked
loop (DLL), which has a finite operating range. Table 14
shows the allowable sample rate ranges for the slow and
fast settings.
TABLE 14. DLL RANGES
.
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
fS MAX
MSPS
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
of setting these options is different from the other
registers.
VALUE
0xC0[3:0]
OUTPUT TEST MODE
0000
Off
0001
Midscale
WORD 1
WORD 2
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1 user_patt2
ADDRESS 0XC2: USER_PATT1_LSB AND
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB AND
ADDRESS 0XC5: USER_PATT2_MSB
READ
OUTPUT_MODE_B
0x74
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
READ
CONFIG_STATUS
0x75
WRITE TO
0x74
DESIRED
VALUE
FIGURE 42. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in
Figure 42. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The KAD5512 can produce preset or user defined
patterns on the digital outputs to facilitate in-site testing.
A static word can be placed on the output bus, or two
different words can alternate. In the alternate mode, the
values defined as Word 1 and Word 2 (as shown in
Table 15) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
27
72 Pin/48 Pin Package Options
The KAD5512 is available in both 72 pin and 48 pin
packages. The 48 pin package option supports LVDS DDR
only. A reduced set of pin selectable functions are
available in the 48 pin package due to the reduced
pinout; (OUTMODE, OUTFMT, and CLKDIV pins are not
available). Table 16 shows the default state for these
functions for the 48 pin package. Note that these
functions are available through the SPI, allowing a user
to set these modes as they desire, offering the same
flexibility as the 72 pin package option. DC and AC
performance of the ADC is equivalent for both package
options.
TABLE 16. 48 PIN SPI - ADDRESSABLE FUNCTIONS
FUNCTION
DESCRIPTION
DEFAULT STATE
CLKDIV
Clock Divider
Divide by 1
OUTMODE
Output Driver
Mode
LVDS, 3mA (DDR)
OUTFMT
Data Coding
Two’s Complement
FN6807.4
October 1, 2010
KAD5512P
SPI Memory Map
Indexed Device Config/Control
Info
SPI Config
TABLE 17. SPI MEMORY MAP
Indexed/
Global
00h
G
00h
G
Chip ID #
Read only
G
Chip Version #
Read only
G
00h
I
Coarse Offset
cal. value
I
Fine Offset
cal. value
I
cal. value
I
Medium Gain
cal. value
I
Fine Gain
cal. value
I
00h
NOT
affected by
Soft Reset
I
00h
G
00h
NOT
affected by
Soft Reset
G
00h
Output Format [2:0]
NOT
000 = Pin Control
001 = Twos Complement affected by
Soft Reset
010 = Gray Code
100 = Offset Binary
other codes = reserved
G
Parameter
Name
Bit 7
(MSB)
00
port_config
SDO
Active
01
reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
reserved
Reserved
08
chip_id
09
chip_version
10
device_index_A
11-1F
reserved
Reserved
20
offset_coarse
21
offset_fine
22
gain_coarse
23
gain_medium
24
gain_fine
25
modes
26-5F
reserved
Reserved
60-6F
reserved
Reserved
70
reserved
Reserved
71
phase_slip
Bit 6
Bit 5
LSB First
Soft
Reset
Bit 4
Bit 3
Bit 1
Bit 0
(LSB)
Mirror Mirror
(bit5) (bit6)
Mirror
(bit7)
Bit 2
Reserved
Reserved
ADC00
Coarse Gain
Reserved
Power-Down Mode
[2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
other codes = reserved
Reserved
72
Global Device Config/Control
Def.
Value
(Hex)
Addr
(Hex)
clock_divide
Next
Clock
Edge
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
73
output_mode_A
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
74
output_mode_B
DLL
Range
0 = fast
1 = slow
DDR
Enable
(Note
15)
00h
NOT
affected by
Soft Reset
G
75
config_status
XOR
Result
XOR
Result
Read Only
G
76-BF
reserved
Reserved
28
FN6807.4
October 1, 2010
KAD5512P
TABLE 17. SPI MEMORY MAP (Continued)
Parameter
Name
C0
test_io
Device Test
Addr
(Hex)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Output Test Mode [3:0]
User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = Reserved
6 = Reserved
Def.
Value
(Hex)
Indexed/
Global
00h
G
00h
G
7 = One/Zero
Word
Toggle
8 = User Input
9-15 = Reserved
C1
Reserved
Reserved
C2
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
Reserved
Reserved
NOTE:
15. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal
pull-up.
29
FN6807.4
October 1, 2010
KAD5512P
Equivalent Circuits
AVDD
TO
CLOCKPHASE
GENERATION
AVDD
CLKP
AVDD
CSAMP
1.6pF
TO
CHARGE
PIPELINE
Φ
F3
INP
Φ2
F
Φ1
F
Ω
1000O
CSAMP
1.6pF
AVDD
TO
CHARGE
PIPELINE
Φ3
F
INN
Φ2
F
Φ1
F
AVDD
11kO
Ω
CLKN
FIGURE 44. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
Ω
75kO
AVDD
TO
SENSE
LOGIC
Ω
75kO
Ω
280O
INPUT
Ω
18kO
AVDD 11kO
Ω
FIGURE 43. ANALOG INPUTS
AVDD
Ω
18kO
OVDD
OVDD
OVDD
20kΩ
INPUT
TO
LOGIC
280Ω
Ω
75kO
Ω
75kO
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
FIGURE 46. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
D[11:0]P
OVDD
OVDD
OVDD
D[11:0]N
DATA
DATA
DATA
D[11:0]
2mA OR
3mA
FIGURE 47. LVDS OUTPUTS
30
FIGURE 48. CMOS OUTPUTS
FN6807.4
October 1, 2010
KAD5512P
Equivalent Circuits
(Continued)
AVDD
VCM
0.535V
+
–
FIGURE 49. VCM_OUT OUTPUT
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be
used to evaluate any of the KADxxxxx ADC family. The
platform consists of a FPGA based data capture
motherboard and a family of ADC daughtercards. This
USB based platform allows a user to quickly evaluate the
ADC’s performance at a user’s specific application
frequency requirements. More information is available at:
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
PCB Layout Example
For an example application circuit and PCB layout, please
refer to the evaluation board documentation provided in
the web product folder at:
http://www.intersil.com/products/partsearch.asp?txtpro
dnr=kad5512p
There are separate evaluation boards for the 48-lead and
72-lead packages.
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex
board designs benefit from isolating the analog and
digital sections. Analog supply and ground planes should
be laid out under signal and clock inputs. Locate the
digital planes under outputs and logic pins. Grounds
should be joined under the chip.
Clock Input Considerations
to device pins. Longer traces will increase inductance,
resulting in diminished dynamic performance and
accuracy. Make sure that connections to ground are
direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO) which
will not be operated do not require connection to ensure
optimal ADC performance. These inputs can be left
floating if they are not used. The SDO output must be
connected to OVDD with a 4.7kΩ resistor or the ADC will
not exit the reset state. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT, CLKDIV) accept a floating input as a
valid state, and therefore should be biased according to
the desired functionality.
General PowerPAD Design
Considerations
The following figure is a generic illustration of how to use
vias to remove heat from a QFN package with an
exposed thermal pad. A specific example can be found in
the evaluation board PCB layout previously referenced.
Use matched transmission lines to the transformer inputs
for the analog input and clock signals. Locate transformers
and terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a
large copper plane using numerous vias for optimal
thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close
31
FIGURE 50. PCB VIA PATTERN
Filling the exposed thermal pad area with vias provides
optimum heat transfer to the PCB’s internal plane(s). Vias
should be evenly distributed from edge-to-edge on the
exposed pad to maintain a constant temperature across the
entire pad. Setting the center-to-center spacing of the vias
FN6807.4
October 1, 2010
KAD5512P
at three times the via pad radius will provide good heat
transfer for high power devices. The vias below the
KAD5512P may be spaced further apart as shown on the
evaluation board since it is a low-power device. The via
diameter should be small but not too small to allow solder
wicking during reflow. PCB fabrication and assembly
companies can provide specific guidelines based on the
layer stack and assembly process.
Least Significant Bit (LSB) is the bit that has the
smallest value or weight in a digital word. Its value in
terms of input voltage is VFS/(2N-1) where N is the
resolution in bits.
Connect all vias under the KAD5512P to AVSS. It is
important to maximize the heat transfer by avoiding
the use of “thermal relief” patterns when connecting
the vias to the internal AVSS plane(s).
Most Significant Bit (MSB) is the bit that has the
largest value or weight.
Definitions
Analog Input Bandwidth is the analog input frequency
at which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
line determined by a least squares curve fit of that
transfer function, measured in units of LSBs.
Missing Codes are output codes that are skipped and
will never appear at the ADC output. These codes cannot
be reached with any input value.
Pipeline Delay is the number of clock cycles between
the initiation of a conversion and the appearance at the
output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of
the observed magnitude of a spur in the ADC FFT, caused
by an AC signal superimposed on the power supply
voltage.
Aperture Delay or Sampling Delay is the time
required after the rise of the clock input for the sampling
switch to open, at which time the signal is held for
conversion.
Signal to Noise-and-Distortion (SINAD) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one half the clock frequency,
including harmonics but excluding DC.
Aperture Jitter is the RMS variation in aperture delay
for a set of samples.
Signal-to-Noise Ratio (without Harmonics) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling
frequency, excluding harmonics and DC.
Clock Duty Cycle is the ratio of the time the clock wave
is at logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of
any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method
of specifying Signal to Noise-and-Distortion Ratio (SINAD).
In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the
voltages that cause the lowest and highest code
transitions to the full-scale voltage less 2 LSB. It is
typically expressed in percent.
SNR and SINAD are either given in units of dB when the
power of the fundamental is used as the reference, or
dBFS (dB to full scale) when the converter’s full-scale
input power is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of
the RMS signal amplitude to the RMS value of the largest
spurious spectral component. The largest spurious
spectral component may or may not be a harmonic.
Integral Non-Linearity (INL) is the maximum
deviation of the ADC’s transfer function from a best fit
32
FN6807.4
October 1, 2010
KAD5512P
Revision History
DATE
REVISION
7/30/08
Rev 1
12/5/08
CHANGE
Initial Release of Production Data sheet
FN6807.0 Converted to intersil template. Assigned file number FN6807. Rev 0 - first release (as preliminary data
sheet) with new file number.
12/23/08
FN6807.1 P1; revised Key Specs
P2; added Part Marking column to Order Info
P4; moved Thermal Resistance to Thermal Info table and added Theta JA Note 3 per packaging
P4-6; revisions throughout spec tables. Removed note from Elec Specs (Nap Mode must be invoked
using SPI.) Added notes 9 and 10 to Switching Specs.
P9; revised function for Pin 22 OUTMODE, Pin 23 NAPSLP and Pin 70 OUTFMT
P11; revised function for Pin 16 NAPSLP
P13-15; Performance curves revised throughout
P17; User Initiated Reset - revised 2nd sentence of 1st paragraph
P19; Nap/Sleep - revised 1st and 2nd sentences of 2nd paragraph
P23; Address 0x24: Gain_Fine; added 2 sentences to end of 1st paragraph.
Revised Table 8
P22; Serial Peripheral Interface- 1st paragraph; revised 2nd and 4th sentences.
P24; removed Figure (PHASE SLIP: CLK÷2 MODE, fCLOCK = 500MHz)
Address 0x71: Phase_slip; added sentence to end of paragraph
P27; revised Fig 45
P27; Table 16; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
2/25/09
FN6807.2 Changed “odd” bits N in Figure 1A - DDR to “even” bits N, Replaced POD L48.7x7E due to changed
dimension from “9.80 sq” to “6.80” sq. in land pattern
4/23/2009 FN6807.3 1) Added nap mode, sleep mode wake up times to spec table
2) Added CSB, SCLK Setup time specs for nap, sleep modes
3) Added section showing 72pin/48pin package feature differences and default state for clkdiv, outmode,
outfmt page 27
4) Changed SPI setup time specs wording in spec table
5) Added ‘Reserved’ to SPI memory map at address 25H
6) Renumbered Notes
7) Added test platform link on page 31
8) Added ddr enable Note15 for 48 pin/72 pin options
9) Changed pin description table for 72/48 pin option, added DDR notes
10) Changed multi device note in spi physical interface section to show 3-wire application.page 24
11) Updated digital output section for ddr operation page 21
12) Change to fig 25 and fig 26 and description in text
13) Added connect note for thermal pad
14) Formatted Figures 25 and 26 with Intersil Standards
08/19/09
15) Updated Sinad 10MHz SINAD typical (170Msps)
16) Updated sleep mode Power spec
17) Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing
specs.
18) Updated SPI timing diagrams, Figures 37, 38
19) Updated wakeup time description in “Nap/Sleep” on page 21.
20) Removed calibration note in spec table
21) Updated fig 46 label)
22) Updated cal paragraph in user initiated reset section per DC.
33
FN6807.4
October 1, 2010
KAD5512P
Revision History (Continued)
DATE
08/18/10
REVISION
CHANGE
FN6807.4 Throughout: Converted to new Intersil Data sheet Template.
Added “Related Literature*(see page 34)” on page 1.
Added Note 3 to “Ordering Information” on page 7 (“For Moisture Sensitivity Level (MSL), please see
device information page for KAD5512P. For more information on MSL please see techbrief TB363.”)
Added Tjc for both 72 & 48 Ld QFNs to “Thermal Information” on page 9.
Added Note 5 to page 9 (“For θJC, the “case temp” location is the center of the exposed metal pad on
the package underside.”)
Added standard over temperature verbiage to common conditions of “Electrical Specifications” table on
page 9 ("Boldface limits apply..") Bolded applicable MIN MAX columns.
Added “Products” on page 34.
Changed the full power bandwidth (analog input bandwidth) from 1.3GHz to 1.5GHz in “Features”on
page 1 and in “Full Power Bandwidth” on page 11.
Added the CSB and SCLK pins to the pin list for the IIH, IIL, VIH and VIL specs in the “INPUTS” section
of the “Digital Specifications” table on page 12.
Clarified the sections describing the RESETN external driver requirements in “Power-On Calibration” on
page 18 and “User-Initiated Reset” on page 19.
Added PAD connection information to “Pin Description” tables and pin configurations.
Added “Recommended Operating Conditions” on page 9.
Added typical “ICM” on page 9 for KAD5512P-21 along with descriptive text in the “Analog Input” section
on page 20.
Added “VCM Output” on page 20.
Added a note to “SPI Physical Interface” on page 24 and “Unused Inputs” on page 31 indicating the
4.7kΩ resistor required from SDO to OVDD.
Added a link to the evaluation boards in the web product folder in “PCB Layout Example” on page 31.
Added “General PowerPAD Design Considerations” on page 31.
8/25/10
Added “SINGLE-TONE SPECTRUM @ 105MHz (250MSPS)” on page 1 (same as Figure 17 from “Typical
Performance Curves”)
Moved “Pin-Compatible Family” from page 1 to page 2. Also, added “Coming Soon” to pre-release
devices and added “Package” columns.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: KAD5512P
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
34
FN6807.4
October 1, 2010
KAD5512P
Package Outline Drawing
L48.7x7E
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 2/09
7.00
PIN 1
INDEX AREA
PIN 1
INDEX AREA
4X 5.50
A
6
B
37
6
48
1
36
44X 0.50
Exp. DAP
5.60 Sq.
7.00
(4X)
12
25
0.15
24
13
48X 0.25
48X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
0.10 C
C
0.08 C
SEATING PLANE
SIDE VIEW
44X 0.50
6.80 Sq
C
48X 0.25
0. 2 REF
5
5.60 Sq
0. 00 MIN.
0. 05 MAX.
DETAIL "X"
48X 0.60
NOTES:
TYPICAL RECOMMENDED LAND PATTERN
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
35
Connect Exp. DAP (PAD) to AVSS with multiple vias to a low
thermal impedance plane
FN6807.4
October 1, 2010
KAD5512P
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
10.00
PIN 1
INDEX AREA
A
4X 8.50
B
55
6
72
1
54
68X 0.50
Exp. DAP
6.00 Sq.
10.00
(4X)
PIN 1
INDEX AREA
6
18
37
0.15
36
19
72X 0.24
72X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
0.10 C
C
0.08 C
SEATING PLANE
68X 0.50
SIDE VIEW
72X 0.24
9.80 Sq
C
0. 2 REF
5
6.00 Sq
0. 00 MIN.
0. 05 MAX.
DETAIL "X"
72X 0.60
NOTES:
1.
TYPICAL RECOMMENDED LAND PATTERN
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Connect Exp. DAP (PAD) to AVSS with multiple vias to a low
thermal impedance plane
36
FN6807.4
October 1, 2010