14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter AD9649 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 45 mW at 20 MSPS 87 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.35 LSB Serial port control options Offset binary, gray code, or twos complement data format Integer 1, 2, or 4 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out (DCO) with programmable clock and data alignment AVDD APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR GND SDIO SCLK CSB RBIAS DRVDD VCM PROGRAMMING DATA VIN+ ADC CORE VIN– CMOS OUTPUT BUFFER SPI VREF OR D13 (MSB) D0 (LSB) DCO SENSE AD9649 DIVIDE BY 1, 2, 4 MODE CONTROLS PDWN CLK+ CLK– DFS MODE 08539-001 REF SELECT Figure 1. PRODUCT HIGHLIGHTS 1. 2. 3. 4. The AD9649 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO, data output (D13 to D0) timing and offset adjustments, and voltage reference modes. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9629 12-bit ADC and the AD9609 10-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9649 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 21 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 22 Revision History ............................................................................... 2 Timing ......................................................................................... 22 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 23 Specifications..................................................................................... 4 Built-In Self-Test (BIST) ............................................................ 23 DC Specifications ......................................................................... 4 Output Test Modes ..................................................................... 23 AC Specifications.......................................................................... 5 Serial Port Interface (SPI) .............................................................. 24 Digital Specifications ................................................................... 6 Configuration Using the SPI ..................................................... 24 Switching Specifications .............................................................. 7 Hardware Interface..................................................................... 25 Timing Specifications .................................................................. 8 Configuration Without the SPI ................................................ 25 Absolute Maximum Ratings............................................................ 9 SPI Accessible Features .............................................................. 25 Thermal Characteristics .............................................................. 9 Memory Map .................................................................................. 26 ESD Caution .................................................................................. 9 Reading the Memory Map Register Table............................... 26 Pin Configuration and Function Descriptions ........................... 10 Open Locations .......................................................................... 26 Typical Performance Characteristics ........................................... 11 Default Values ............................................................................. 26 AD9649-80 .................................................................................. 11 Memory Map Register Table ..................................................... 27 AD9649-65 .................................................................................. 13 Memory Map Register Descriptions ........................................ 29 AD9649-40 .................................................................................. 14 Applications Information .............................................................. 30 AD9649-20 .................................................................................. 15 Design Guidelines ...................................................................... 30 Equivalent Circuits ......................................................................... 16 Outline Dimensions ....................................................................... 31 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 31 Analog Input Considerations.................................................... 17 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD9649 GENERAL DESCRIPTION The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip voltage reference. deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in The AD9649 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles. Rev. 0 | Page 3 of 32 AD9649 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 3 Input Common-Mode Voltage Input Common-Mode Range REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD2 IDRVDD2 (1.8 V) IDRVDD2 (3.3 V) POWER CONSUMPTION DC Input 2 Sine Wave Input (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power Temp Full Full Full Full Full 25°C Full 25°C AD9649-20/AD9649-40 Min Typ Max 14 −0.40 Full Full Full Guaranteed +0.05 +0.50 −1.5 ±0.50 ±0.25 ±1.30 ±0.50 Min 14 AD9649-65 Typ Max Guaranteed −0.40 +0.05 +0.50 −1.5 +0.55 ±0.3 ±1.30 ±0.50 ±2 0.984 Min 14 AD9649-80 Typ Max Guaranteed −0.40 +0.05 +0.50 −1.5 ±0.65 ±0.35 ±1.75 ±0.60 ±2 0.996 2 1.008 0.984 0.996 2 ±2 1.008 0.984 0.996 2 Unit Bits % FSR % FSR LSB LSB LSB LSB ppm/°C 1.008 V mV 25°C 0.98 0.98 0.98 LSB rms Full Full Full Full Full 2 6 0.9 2 6 0.9 2 6 0.9 V p-p pF V V kΩ Full Full 0.5 1.3 0.5 7.5 1.7 1.7 1.3 0.5 7.5 1.8 1.9 3.6 Full Full Full 25.0/31.3 1.6/2.9 3.0/5.3 27.3/33.7 Full Full Full Full Full 45.2/57.2 47.9/61.6 54.9/73.8 34/34 0.5 51.8/65.8 1 1.7 1.7 1.8 1.9 3.6 41.0 4.7 8.4 44.0 75.2 82.3 101.5 34 0.5 1.7 1.7 87.5 Measured with 1.0 V external reference. Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and ground. 4 Standby power is measured with a dc input and the CLK+, CLK− active. 2 Rev. 0 | Page 4 of 32 1.3 7.5 1.8 1.9 3.6 V V 47.0 5.6 10.2 50.0 mA mA mA 86.8 94.7 118.3 34 0.5 100 mW mW mW mW mW AD9649 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz TWO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) ANALOG INPUT BANDWIDTH 1 Temp 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C AD9649-20/AD9649-40 Min Typ Max Min 74.7 74.4 AD9649-65 Typ Max Min 74.5 74.3 73.1 AD9649-80 Typ Max 74.3 74.1 dBFS dBFS dBFS dBFS dBFS dBFS 73.6 73.7 73.7 73.6 72.7 71.5 71.5 71.5 74.6 74.3 74.4 74.2 74.1 74.0 Unit 70.0 70.0 70.0 dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 12.0 12.0 11.9 11.3 12.0 12.0 11.9 11.3 12.0 12.0 11.9 11.3 Bits Bits Bits Bits 25°C 25°C Full 25°C Full 25°C −95 −95 −95 −95 −93 −93 dBc dBc dBc dBc dBc dBc 25°C 25°C Full 25°C Full 25°C 73.0 73.5 73.6 73.6 73.5 72.6 −82 −83 −94 −94 −92 −80 −80 −80 95 94 95 94 93 93 −82 82 dBc dBc dBc dBc dBc dBc 83 93 93 92 82 80 80 80 25°C 25°C Full 25°C Full 25°C −100 −100 −100 −100 −100 −100 25°C 25°C −100 −100 −100 −95 −95 −95 dBc dBc dBc dBc dBc dBc 90 700 90 700 90 700 dBc MHz −90 −90 −90 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 5 of 32 AD9649 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (CSB)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (IOH) IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage (IOL) IOL = 1.6 mA IOL = 50 μA DRVDD = 1.8 V High Level Output Voltage (IOH) IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage (IOL) IOL = 1.6 mA IOL = 50 μA 1 2 Temp Full Full Full Full Full Full Full AD9649-20/AD9649-40/AD9649-65/AD9649-80 Min Typ Max CMOS/LVDS/LVPECL 0.9 0.2 GND − 0.3 −10 −10 8 Full Full Full Full Full Full 1.2 0 −50 −10 Full Full Full Full Full Full 1.2 0 −10 40 Full Full 3.29 3.25 V V μA μA kΩ pF DRVDD + 0.3 0.8 +10 135 V V μA μA kΩ pF 26 2 V V 0.2 0.05 1.79 1.75 Full Full Internal 30 kΩ pull-down. Internal 30 kΩ pull-up. Rev. 0 | Page 6 of 32 V V p-p V μA μA kΩ pF DRVDD + 0.3 0.8 −75 +10 30 2 Full Full Full Full 10 4 3.6 AVDD + 0.2 +10 +10 12 Unit V V V V 0.2 0.05 V V AD9649 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Period, Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) Wake-Up Time 2 Standby OUT-OF-RANGE RECOVERY TIME 2 Full Full Full AD9649-20/AD9649-40 Min Typ Max 80/160 20/40 Min AD9649-65 Typ Max AD9649-80 Typ Max Full Full 25.0/12.5 1.0 0.1 7.69 1.0 0.1 6.25 1.0 0.1 Full Full Full Full Full Full Full 3 3 0.1 8 350 600/400 2 3 3 0.1 8 350 300 2 3 3 0.1 8 350 260 2 ns ns ns Cycles μs ns Cycles 50/25 3 15.38 320 80 Unit MHz MSPS ns ns ns ps rms 3 260 65 Min 3 12.5 Conversion rate is the clock rate after the CLK divider. Wake-up time is dependent on the value of the decoupling capacitors. N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCO tSKEW DATA N–8 N–7 N–6 tPD Figure 2. CMOS Output Data Timing Rev. 0 | Page 7 of 32 N–5 N–4 08539-002 1 Temp AD9649 TIMING SPECIFICATIONS Table 5. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Conditions Min Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Rev. 0 | Page 8 of 32 Typ Max Unit AD9649 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter AVDD to AGND1 DRVDD to AGND1 VIN+, VIN− to AGND1 CLK+, CLK− to AGND1 VREF to AGND1 SENSE to AGND1 VCM to AGND1 RBIAS to AGND1 CSB to AGND1 SCLK/DFS to AGND1 SDIO/PDWN to AGND1 MODE/OR to AGND1 D0 through D13 to AGND1 DCO to AGND1 Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) 1 Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −40°C to +85°C 150°C −65°C to +150°C AGND refers to the analog ground of the customer’s PCB. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The exposed paddle is the only ground connection for the chip and must be soldered to the analog ground plane of the user’s PCB. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Package Type 32-Lead LFCSP 5 mm × 5 mm Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 37.1 32.4 29.1 θJC1, 3 3.1 θJB1, 4 20.7 ΨJT1,2 0.3 0.5 0.8 Unit °C/W °C/W °C/W 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 3 Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. ESD CAUTION Rev. 0 | Page 9 of 32 AD9649 32 31 30 29 28 27 26 25 AVDD VIN+ VIN– AVDD RBIAS VCM SENSE VREF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9649 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AVDD MODE/OR DCO D13 (MSB) D12 D11 D10 D9 D2 D3 D4 D5 DRVDD D6 D7 D8 08539-003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK+ CLK– AVDD CSB SCLK/DFS SDIO/PDWN D0 (LSB) D1 NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND PLANE OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND MAXIMIZE THE HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 0 (EP) Mnemonic GND 1, 2 3, 24, 29, 32 4 5 CLK+, CLK− AVDD CSB SCLK/DFS 6 SDIO/PDWN 7 to 12, 14 to 21 13 22 23 D0 (LSB) to D13 (MSB) DRVDD DCO MODE/OR 25 26 27 28 30, 31 VREF SENSE VCM RBIAS VIN−, VIN+ Description Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog ground of the customer’s PCB to ensure proper functionality and maximize the heat dissipation, noise, and mechanical strength benefits. Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 1.8 V Supply Pin for the ADC CORE Domain. SPI Chip Select. Active low enable, 30 kΩ internal pull-up. SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down. See Table 14 for details. ADC Digital Outputs. 1.8 V to 3.3 V Supply Pin for Output Driver Domain. Data Clock Digital Output. Chip Mode Select Input in SPI Mode (MODE). Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100). Chip stand-by (SPI Register 0x08, Bits[7:5] = 101). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111). In non-SPI mode, the pin operates only as an out-of-range (OR) digital output. 1.0 V Voltage Reference Input/Output. See Table 10. Reference Mode Selection. See Table 10. Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. ADC Analog Inputs. Rev. 0 | Page 10 of 32 AD9649 TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 0 80MSPS 9.7MHz @ –1dBFS SNR = 73.4dB (74.4dBFS) SFDR = 94.4dBc –15 –15 –30 AMPLITUDE (dBFS) –45 –60 –75 –90 3 2 –105 5 6 4 –60 –75 –90 3 2 5 –105 –120 6 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 08539-033 –120 4 36 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 Figure 4. AD9649-80 Single-Tone FFT with fIN = 9.7 MHz Figure 7. AD9649-80 Single-Tone FFT with fIN = 30.5 MHz 0 0 80MSPS 70.3MHz @ –1dBFS SNR = 72.1dB (73.1dBFS) SFDR = 93.5dBc –15 –15 –30 80MSPS 200MHz @ –1dBFS SNR = 70.5dB (71.5dBFS) SFDR = 80.2dBc –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –45 08539-034 AMPLITUDE (dBFS) –30 80MSPS 30.5MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 93.6dBc –45 –60 –75 –90 2 –60 –75 2 3 –90 3 6 –105 –45 4 5 –105 4 6 5 –120 12 16 20 24 28 FREQUENCY (MHz) 32 36 –120 4 8 12 32 36 Figure 5. AD9649-80 Single-Tone FFT with fIN = 70.3 MHz Figure 8. AD9649-80 Single-Tone FFT with fIN = 200 MHz 0 0 –15 80MSPS 30.5MHz @ –7dBFS 32.5MHz @ –7dBFS SFDR = 89.5dBc (96.5dBFS) –20 SFDR/IMD3 (dBc/dBFS) –30 AMPLITUDE (dBFS) 16 20 24 28 FREQUENCY (MHz) –45 –60 –75 –90 2F1 + F2 2F2 + F1 F1 + F2 F2 – F1 08539-036 8 08539-062 4 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) 2F1 – F2 2F2 – F1 –100 –105 IMD3 (dBFS) 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 08539-200 4 –120 –90 Figure 6. AD9649-80 Two-Tone FFT with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz –78 –66 –54 –42 –30 INPUT AMPLITUDE (dBFS) –18 –6 08539-054 –120 Figure 9. AD9649-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz Rev. 0 | Page 11 of 32 AD9649 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 120 100 SFDR (dBc) 90 SFDRFS 100 70 SNR (dBFS) SNR/SFDR (dBFS) SNR/SFDR (dBFS/dBc) 80 60 50 40 80 SNRFS 60 SFDR 40 30 SNR 20 20 0 50 100 150 INPUT FREQUENCY (MHz) 200 0 –90 08539-057 0 –80 –60 –40 INPUT AMPLITUDE (dBFS) –20 0 08539-061 10 Figure 13. AD9649-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 10. AD9649-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 450,000 120 400,000 SFDR (dBc) 100 SNR (dBFS) 80 NUMBER OF HITS SNR/SFDR (dBFS/dBc) 350,000 60 40 300,000 250,000 200,000 150,000 100,000 20 20 30 40 50 60 SAMPLE RATE (MSPS) 70 80 0 08539-055 0 10 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 OUTPUT CODE 08539-048 50,000 Figure 14. AD9649-80 Grounded Input Histogram Figure 11. AD9649-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 2.0 0.5 0.4 1.5 0.3 1.0 INL ERROR (LSB) 0.1 0 –0.1 –0.2 0.5 0 –0.5 –1.0 –0.3 –0.4 –0.5 0 2048 4096 –2.0 0 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE Figure 12. AD9649-80 DNL Error with fIN = 9.7 MHz 2048 4096 6144 8192 10,240 12,288 14,336 16,384 OUTPUT CODE Figure 15. AD9649-80 INL with fIN = 9.7 MHz Rev. 0 | Page 12 of 32 08539-037 –1.5 08539-038 DNL ERROR (LSB) 0.2 AD9649 AD9649-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 120 65MSPS 9.7MHz @ –1dBFS SNR = 73.5dB (74.5dBFS) SFDR = 97.7dBc –15 SFDRFS 100 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –30 –45 –60 –75 80 SNRFS 60 SFDR 40 –90 SNR 5 6 –105 2 4 3 20 6 9 12 15 18 21 FREQUENCY (MHz) 24 27 0 –90 08539-030 3 30 Figure 16. AD9649-65 Single-Tone FFT with fIN = 9.7 MHz 90 SNR/SFDR (dBFS/dBc) –45 –60 –75 –90 2 3 –105 4 5 SFDR (dBc) 70 SNR (dBFS) 60 50 40 30 20 6 10 –120 6 9 12 15 18 21 FREQUENCY (MHz) 24 27 30 0 08539-032 3 0 65MSPS 30.5MHz @ –1dBFS SNR = 73.3dB (74.3dBFS) SFDR = 99.3dBc –30 –45 –60 –75 –90 3 5 2 6 4 6 9 12 15 18 21 FREQUENCY (MHz) 24 27 30 08539-031 –120 3 100 150 INPUT FREQUENCY (MHz) 200 Figure 20. AD9649-65 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 17. AD9649-65 Single-Tone FFT with fIN = 70.3 MHz –105 50 Figure 18. AD9649-65 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 13 of 32 08539-056 AMPLITUDE (dBFS) 0 80 –30 AMPLITUDE (dBFS) –20 100 65MSPS 70.3MHz @ –1dBFS SNR = 72.6dB (73.6dBFS) SFDR = 94.1dBc –15 –15 –60 –40 INPUT AMPLITUDE (dBFS) Figure 19.AD9649-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 0 –80 08539-060 –120 AD9649 AD9649-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 –15 120 40MSPS 9.7MHz @ –1dBFS SNR = 73.5dB (74.5dBFS) SFDR = 95.4dBc SFDRFS 100 SNR/SFDR (dBFS) AMPLITUDE (dB) –30 –45 –60 –75 –90 –105 80 SNRFS 60 SFDR 40 SNR 4 5 3 2 6 20 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 Figure 21. AD9649-40 Single-Tone FFT with fIN = 9.7 MHz 0 –15 0 –90 08539-028 2 40MSPS 30.5MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 95.7dBc –60 –75 –90 5 3 2 6 –120 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 08539-029 AMPLITUDE (dBFS) –45 4 –60 –40 INPUT AMPLITUDE (dBFS) –20 0 Figure 23. AD9649-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz –30 –105 –80 08539-059 –120 Figure 22. AD9649-40 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 14 of 32 AD9649 AD9649-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, unless otherwise noted. 0 –15 120 20MSPS 9.7MHz @ –1dBFS SNR = 73.5dBFS (74.5dBFS) SFDR = 97.2dBc SFDR (dBFS) 100 SNR/SFDR (dBc/dBFS) AMPLITUDE (dBFS) –30 –45 –60 –75 –90 –105 2 4 5 3 6 SNR (dBFS) 80 60 SFDR (dBc) 40 SNR (dBc) 20 0 –100 08539-024 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 FREQUENCY (MHz) Figure 24. AD9649-20 Single-Tone FFT with fIN = 9.7 MHz 20MSPS 30.5MHz @ –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 98.1dBc –45 –60 –75 –90 2 4 6 5 3 –120 950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50 FREQUENCY (MHz) 08539-026 AMPLITUDE (dBFS) –30 –105 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 Figure 26. AD9649-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 –15 –90 08539-058 –120 Figure 25. AD9649-20 Single-Tone FFT with fIN = 30.5 MHz Rev. 0 | Page 15 of 32 AD9649 EQUIVALENT CIRCUITS DRVDD AVDD 08539-039 08539-042 VIN± Figure 31. Equivalent D0 to D13 and OR Digital Output Circuit Figure 27. Equivalent Analog Input Circuit DRVDD AVDD SCLK/DFS, MODE, SDIO/PDWN VREF 30kΩ 08539-047 7.5kΩ 350Ω 08539-043 375Ω Figure 32. Equivalent SCLK/DFS, MODE and SDIO/PDWN Input Circuit Figure 28. Equivalent VREF Circuit AVDD DRVDD AVDD 375Ω SENSE 30kΩ 350Ω 08539-045 08539-046 CSB Figure 29. Equivalent SENSE Circuit CLK+ Figure 33. Equivalent CSB Input Circuit 5Ω 15kΩ 0.9V AVDD 15kΩ CLK– 5Ω 375Ω 08539-044 08539-040 RBIAS AND VCM Figure 34. Equivalent RBIAS, VCM Circuit Figure 30. Equivalent Clock Input Circuit Rev. 0 | Page 16 of 32 AD9649 THEORY OF OPERATION Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9649 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide an external dc bias. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 36 and Figure 37. 100 The output staging block aligns the data, corrects errors, and passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. SFDR (dBc) SNR/SFDR (dBFS/dBc) 90 ANALOG INPUT CONSIDERATIONS The analog input to the AD9649 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. 80 SNR (dBFS) 70 60 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 INPUT COMMON-MODE VOLTAGE (V) 1.2 1.3 08539-049 The AD9649 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample, whereas the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Figure 36. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 32.1 MHz, fS = 80 MSPS H CPAR 100 H VIN+ CSAMPLE S S S SFDR (dBc) 90 SNR/SFDR (dBFS/dBc) CSAMPLE VIN– H 08539-006 H CPAR Figure 35. Switched-Capacitor Input Circuit The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 35). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within onehalf of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at 80 SNR (dBFS) 70 60 50 0.5 0.6 0.7 0.8 0.9 1.0 1.1 INPUT COMMON-MODE VOLTAGE (V) 1.2 1.3 08539-050 S Figure 37. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 10.3 MHz, fS = 20 MSPS An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Rev. 0 | Page 17 of 32 AD9649 Differential Input Configurations the true SNR performance of the AD9649. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 41). Optimum performance is achieved while driving the AD9649 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 42. See the AD8352 data sheet for more information. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9649 (see Figure 38), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 33Ω VIN– 76.8Ω AVDD 90Ω 10pF 120Ω ADC 33Ω VCM VIN+ Table 9. Example RC Network 08539-007 ADA4938-2 200Ω For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 39. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. A single-ended input can provide adequate performance in costsensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 40 shows a typical single-ended input configuration. VIN+ 49.9Ω ADC C R VCM 08539-008 VIN– 0.1µF 10µF AVDD 1kΩ Figure 39. Differential Transformer-Coupled Configuration 1V p-p The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. 49.9Ω 0.1µF R VIN+ 1kΩ AVDD ADC C 1kΩ R VIN– 10µF At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve 0.1µF 1kΩ Figure 40. Single-Ended Input Configuration 0.1µF 0.1µF C Differential (pF) 22 Open Single-Ended Input Configuration R R VIN+ 2V p-p 25Ω PA S S P ADC C 0.1µF 25Ω 0.1µF R VCM VIN– Figure 41. Differential Double Balun Input Configuration VCC 0.1µF 0Ω ANALOG INPUT 16 1 8, 13 11 2 CD RD RG 3 5 0.1µF 0Ω R VIN+ 200Ω 10 ADC C AD8352 4 ANALOG INPUT 0.1µF 0.1µF 0.1µF 200Ω R VIN– 14 0.1µF 0.1µF Figure 42. Differential Input Configuration Using the AD8352 Rev. 0 | Page 18 of 32 VCM 08539-011 2V p-p R Series (Ω Each) 33 125 Frequency Range (MHz) 0 to 70 70 to 200 Figure 38. Differential Input Configuration Using the ADA4938-2 08539-010 0.1µF 08539-009 200Ω VIN In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. AD9649 0 Internal Reference Connection A comparator within the AD9649 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 43), setting VREF to 1.0 V. –0.5 –1.0 INTERNAL VREF = 0.996V –1.5 –2.0 –2.5 –3.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 08539-014 A stable and accurate 1.0 V voltage reference is built into the AD9649. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference. REFERENCE VOLTAGE ERROR (%) VOLTAGE REFERENCE Figure 44. VREF Accuracy vs. Load Current VIN+ 4 VIN– 3 2 ADC CORE VREF ERROR (mV) VREF ERROR (mV) 1 VREF 1.0µF 0.1µF SELECT LOGIC SENSE 0 –1 –2 –3 –4 0.5V –6 –40 Figure 43. Internal Reference Configuration If the internal reference of the AD9649 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 shows how the internal reference voltage is affected by loading. External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 45 shows the typical drift characteristics of the internal reference in 1.0 V mode. –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 45. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 28). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. Table 10. Reference Configuration Summary Selected Mode Fixed Internal Reference Fixed External Reference SENSE Voltage (V) AGND to 0.2 AVDD 08539-052 ADC 08539-012 –5 Resulting VREF (V) 1.0 internal 1.0 applied to external VREF pin Rev. 0 | Page 19 of 32 Resulting Differential Span (V p-p) 2.0 2.0 AD9649 CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9649 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 46) and require no external bias. AVDD 0.9V If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 49. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. CLK– 0.1µF 0.1µF CLOCK INPUT 2pF 08539-016 2pF CLK+ 0.1µF AD951x PECL DRIVER CLOCK INPUT Clock Input Options 240Ω 50kΩ Figure 47 and Figure 48 show two preferred methods for clocking the AD9649. The CLK inputs support up to 4× the rated sample rate when using the internal clock divider feature. A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer or an RF balun. A third option is to ac couple a differential LVDS signal to the sample clock input pins as shown in Figure 50. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 0.1µF 0.1µF CLOCK INPUT CLK+ 0.1µF AD951x LVDS DRIVER CLOCK INPUT XFMR 0.1µF ADC 0.1µF CLK– 08539-017 SCHOTTKY DIODES: HSMS2822 0.1µF ADC 0.1µF 08539-020 50kΩ Figure 50. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate) CLK+ 100Ω 50Ω 100Ω CLK– 50kΩ Mini-Circuits® ADT1-1WT, 1:1 Z 0.1µF 240Ω Figure 49. Differential PECL Sample Clock (Up to 4× Rated Sample Rate) The AD9649 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of great concern, as described in the Jitter Considerations section. CLOCK INPUT ADC 0.1µF CLK– 50kΩ Figure 46. Equivalent Clock Input Circuit 100Ω 08539-019 CLK+ This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9649 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. Figure 47. Transformer-Coupled Differential Clock (3 MHz to 200 MHz) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 51). VCC 0.1µF CLOCK INPUT CLK+ 50Ω 50Ω 1 ADC 0.1µF 1nF 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω 1kΩ ADC CLK– CLK– 08539-018 SCHOTTKY DIODES: HSMS2822 CLK+ 0.1µF 150Ω Figure 48. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate) RESISTOR IS OPTIONAL. Figure 51. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) The RF balun configuration is recommended for clock frequencies between 80 MHz and 320 MHz, and the RF transformer is recommended for clock frequencies from 3 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9649 to ~0.8 V p-p differential. Input Clock Divider The AD9649 contains an input clock divider with the ability to divide the input clock by integer values of 1, 2, or 4. Rev. 0 | Page 20 of 32 08539-021 1nF CLOCK INPUT 0.1µF AD9649 Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 50% duty cycle clock with ±5% tolerance is required to maintain optimum dynamic performance, as shown in Figure 52. Jitter on the rising edge of the clock input can also impact dynamic performance and should be minimized, as discussed in the Jitter Considerations section of this datasheet. 80 75 70 supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. For more information, see the AN-501 Application Note and the AN-756 Application Note, which are available on www.analog.com. POWER DISSIPATION AND STANDBY MODE As shown in Figure 54, the analog core power dissipated by the AD9649 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit. IDRVDD = VDRVDD × CLOAD × fCLK × N 60 where N is the number of output bits (15, in the case of the AD9649). 55 This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits that are switching, which is determined by the sample rate and the characteristics of the analog input signal. 50 40 10 20 30 40 50 60 POSITIVE DUTY CYCLE (%) 70 80 08539-053 45 Figure 52. SNR vs. Clock Duty Cycle Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 54 was taken using the same operating conditions as those used for the Typical Performance Characteristics, with a 5 pF load on each output driver. 85 SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ] 80 ANALOG CORE POWER (mW) In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 53. 80 75 0.05ps 70 65 55 50 60 1.5ps 3.0ps 45 1 10 2.0ps 2.5ps 100 FREQUENCY (MHz) AD9649-20 20 30 40 50 60 CLOCK RATE (MSPS) 70 80 Figure 54. Analog Core Power vs. Clock Rate 1.0ps 50 AD9649-40 45 35 10 55 AD9649-65 60 40 0.5ps AD9649-80 70 65 1k 08539-022 SNR (dBFS) 0.2ps 75 08539-051 SNR (dBFS) The maximum DRVDD current (IDRVDD) can be calculated as 65 Figure 53. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9649. To avoid modulating the clock signal with digital noise, keep power In SPI mode, the AD9649 can be placed in power-down mode directly via the SPI port or by using the programmable external MODE pin. In non-SPI mode, power-down is achieved by asserting the PDWN pin high. In this state, the ADC typically dissipates 500 μW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin (or the MODE pin in SPI mode) low returns the AD9649 to normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Rev. 0 | Page 21 of 32 AD9649 Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. Digital Output Enable Function (OEB) When using the SPI interface, the data outputs and DCO can be independently three-stated by using the programmable external MODE pin. The OEB function of the MODE pin is enabled via Bits[6:5] of Register 0x08. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details. If the MODE pin is configured to operate in traditional OEB mode and the MODE pin is low, the output data drivers and DCOs are enabled. If the MODE pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that the MODE pin is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. DIGITAL OUTPUTS TIMING The AD9649 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families. Output data can also be multiplexed onto a single output bus to reduce the total number of traces required. The AD9649 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The CMOS output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 11). As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9649. These transients may degrade converter dynamic performance. The lowest typical conversion rate of the AD9649 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD9649 provides a data clock output (DCO) signal that is intended for capturing the data in an external register. The CMOS data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 for a graphical timing description. Table 11. SCLK/DFS and SDIO/PDWN Mode Selection (External Pin Mode) Voltage at Pin GND SCLK/DFS Offset binary (default) DRVDD Twos complement SDIO/PDWN Normal operation (default) Outputs disabled Table 12. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) < −VREF − 0.5 LSB = −VREF =0 = +VREF − 1.0 LSB > +VREF − 0.5 LSB Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Rev. 0 | Page 22 of 32 Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 OR 1 0 0 0 1 AD9649 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9649 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as facilitate board-level debugging. Also included is a built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9649. Various output test options are also provided to place predictable values on the outputs of the AD9649. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9649 signal path. Perform the BIST test after a reset to ensure that the part is in a known state. During the BIST test, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. When the BIST sequence is complete, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying that the test passed. If the BIST test failed, Bit 0 of Register 0x24 is cleared. The outputs are connected during this test so that the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST, enabling Bit 0 (BIST enable) of Register 0x0E and resetting the PN sequence generator, Bit 2 (BIST init) of Register 0x0E. Upon completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. The user must then rely on verifying the output data. OUTPUT TEST MODES The output test options are described in Table 16 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 23 of 32 AD9649 SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 55 and Table 5. The AD9649 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits, as shown in Figure 55. Three pins define the SPI of this ADC: the SCLK (SCLK/DFS, the SDIO (SDIO/PDWN), and the CSB (see Table 13). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/ output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) is an active-low control that enables or disables the read and write cycles. All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Table 13. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active-low control that gates the read and write cycles. tHIGH tDS tS tDH Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 55. Serial Port Interface Timing Diagram Rev. 0 | Page 24 of 32 D4 D3 D2 D1 D0 DON’T CARE 08539-023 SCLK DON’T CARE AD9649 HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9649. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. For detailed information about one method for SPI configuration, refer to the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9649 to prevent these signals from transitioning at the converter inputs during critical sampling periods. The SDIO/PDWN and SCLK/DFS pins serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9649. CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the power-down and output data format feature control. In this mode, connect the CSB chip select to DRVDD, which disables the serial port interface. Table 14. Mode Selection Pin SDIO/PDWN SCLK/DFS External Voltage DRVDD AGND (default) DRVDD AGND (default) Configuration Chip power-down mode Normal operation (default) Twos complement enabled Offset binary enabled SPI ACCESSIBLE FEATURES Table 15 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9649 part-specific features are described in detail in Table 16. Table 15. Features Accessible Using the SPI Feature Modes Offset Adjust Test Mode Output Mode Output Phase Output Delay Rev. 0 | Page 25 of 32 Description Allows the user to set either power-down mode or standby mode Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay AD9649 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) contains eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device transfer registers (Address 0xFF); the program registers, including setup, control, and test (Address 0x08 to Address 0x2A); and the digital feature control registers (Address 0x101). After the AD9649 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 16). Table 16 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x2A, the OR/MODE select register, has a hexadecimal default value of 0x01. This means that in Address 0x2A, Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE setting. The default value results in the programmable external MODE/OR pin (Pin 23) functioning as an out-of-range digital output. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x101, is documented in the Memory Map Register Descriptions section that follows Table 16. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x2A). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Rev. 0 | Page 26 of 32 AD9649 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Addr. (Hex) Register Name Chip configuration registers 0x00 SPI port configuration 0x01 Chip ID 0x02 Chip grade Device transfer registers 0xFF Transfer Program registers 0x08 Modes (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 LSB first Soft reset 1 1 Soft reset Bit 1 (LSB) Bit 0 Def. Value (Hex) Default Notes/ Comments LSB first 0 0x18 The nibbles are mirrored so that LSB or MSB first mode registers correctly, regardless of shift mode. Unique chip ID used to differentiate devices; read only. Unique speed grade ID used to differentiate devices; read only. 8-bit chip ID, Bits[7:0] AD9649 = 0x6F Open Speed grade ID, Bits[6:4] (identify device variants of chip ID) 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Open Open External Pin 23 MODE input enable External Pin 23 function when high 00 = full power-down 01 = standby 10 = normal mode, output disabled 11 = normal mode, output enabled Open Open Open Read only Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave. Open Open Open 00 = chip run 01 = full power-down 10 = standby 11 = chip wide digital reset 0x00 Determines various generic modes of chip operation. 0x00 The divide ratio is the value + 1. 0x00 When set, the test data is placed on the output pins in place of normal data. 0x00 When Bit 0 is set, the built-in selftest function is initiated. Device offset trim. 0x0B Clock divide 0x0D Test mode User test mode 00 = single 01 = alternate 10 = single once 11 = alternate once Reset PN long gen Reset PN short gen 0x0E BIST enable Open Open Open 0x10 Offset adjust Open Read only Clock divider, Bits[2:0] Clock divide ratio 000 = divide-by-1 001 = divide-by-2 011 = divide-by-4 Output test mode, Bits[3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1/0 word toggle 1000 = user input 1001 = 1/0 bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency Open BIST init Open BIST enable 8-bit device offset adjustment, Bits[7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) Rev. 0 | Page 27 of 32 0x00 AD9649 Def. Value (Hex) Default Notes/ Comments 0x00 Configures the outputs and the format of the data. 0x22 Determines CMOS output drive strength properties. 0x00 On devices that use global clock divide, determines which phase of the divider output is used to supply the output clock; internal latching is unaffected. 0x00 Sets the fine output delay of the output clock but does not change internal timing. B6 00 = offset binary 01 = twos complement 10 = gray code 11 = offset binary 1.8 V data 3.3 V data 1.8 V DCO drive strength drive strength drive strength 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 01 = 2 stripes (default) 01 = 2 stripes 10 = 3 stripes 01 = 2 stripes 10 = 3 stripes (default) 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes Open Open Open Input clock phase adjust, Bits[2:0] (Value is number of input clock cycles of phase delay) 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles Enable Open DCO/data delay, Bits[2:0] data 000 = 0.56 ns delay 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns B5 B4 B3 B2 B1 B0 0x00 B15 B14 B13 B12 B11 B10 B9 B8 0x00 USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x24 BIST signature LSB 0x2A OR/MODE select User-defined Pattern 1 LSB. User-defined Pattern 1 MSB. User-defined Pattern 2 LSB. User-defined Pattern 2 MSB. Least significant byte of BIST signature, read only. Selects I/O functionality in conjunction with Address 0x08 for MODE (input) or OR (output) on External Pin 23. Addr. (Hex) (MSB) Bit 7 Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS Open Output disable Open Output invert 0x15 Output adjust 0x16 Output phase 3.3 V DCO drive strength 00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes Open DCO output polarity 0= normal 1 = inv 0x17 Output delay Enable DCO delay Open 0x19 USER_PATT1_LSB B7 0x1A USER_PATT1_MSB 0x1B Bit 1 (LSB) Bit 0 BIST signature, Bits[7:0] Open Digital feature control register 0x101 USR2 1 0x00 Open Open Open Open Open Open 0= MODE 1 = OR (default) 0x01 Open Open Open Enable GCLK detect Run GCLK Open Disable SDIO pulldown 0x88 Rev. 0 | Page 28 of 32 Enables internal oscillator for clock rates of <5 MHz. AD9649 MEMORY MAP REGISTER DESCRIPTIONS Bit 2—Run GCLK For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Bit 2 enables the GCLK oscillator. For some applications with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector. USR2 (Register 0x101) Bit 0—Disable SDIO Pull-Down Bit 3—Enable GCLK Detect Bit 0 can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. Normally set high, Bit 3 enables a circuit that detects encode rates below ~5 MSPS. When a low encode rate is detected, an internal oscillator, GCLK, is enabled, ensuring the proper operation of several circuits. If set low, the detector is disabled. Rev. 0 | Page 29 of 32 AD9649 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting the design and layout of the AD9649 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9649, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD supply must be used, the AVDD and DRVDD domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. Encode Clock For optimum dynamic performance, use a low jitter encode clock source with a 50% duty cycle (±5%) to clock the AD9649. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 39. A single PCB ground plane should be sufficient when using the AD9649. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. RBIAS Exposed Paddle Thermal Heat Sink Recommendations Reference Decoupling The exposed paddle (Pin 0) is the only ground connection for the AD9649; therefore, it must be connected to analog ground (AGND) on the customer’s PCB. To achieve the best electrical and thermal performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the AD9649 exposed paddle, Pin 0. Externally decouple the VREF pin to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. The AD9649 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9649 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 30 of 32 AD9649 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 17 16 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 EXPOSED PAD (BOTTOM VIEW) 3.65 3.50 SQ 3.35 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 32 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 100608-A TOP VIEW 1.00 0.85 0.80 PIN 1 INDICATOR 25 24 Figure 56. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-4) Dimensions shown in millimeters ORDERING GUIDE Model AD9649BCPZ-80 1, 2 AD9649BCPZRL7-801, 2 AD9649BCPZ-651, 2 AD9649BCPZRL7-651, 2 AD9649BCPZ-401, 2 AD9649BCPZRL7-401, 2 AD9649BCPZ-201, 2 AD9649BCPZRL7-201, 2 AD9649-80EBZ1 AD9649-65EBZ1 AD9649-40EBZ1 AD9649-20EBZ1 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. Rev. 0 | Page 31 of 32 Package Option CP-32-4 CP-32-4 CP-32-4 CP-32-4 CP-32-4 CP-32-4 CP-32-4 CP-32-4 AD9649 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08539-0-10/09(0) Rev. 0 | Page 32 of 32