MC100EPT24 D

MC100EPT24
3.3V LVTTL/LVCMOS to
Differential LVECL Translator
Description
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a −3.3 V, +3.3 V and ground are required. The small outline
8−lead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
8
350 ps Typical Propagation Delay
Maximum Input Clock Frequency > 1.0 GHz Typical
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 3.0 V to 3.6 V;
VEE = −3.6 V to −3.0 V; GND = 0 V
PNP LVTTL Input for Minimal Loading
Q Output will Default HIGH with Input Open
Pb−Free Packages are Available
1
SOIC−8
D SUFFIX
CASE 751
KPT24
ALYW
G
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
KA24
ALYWG
G
DFN8
MN SUFFIX
CASE 506AA
3U MG
G
•
•
•
MARKING DIAGRAMS*
8
Features
•
•
•
•
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1
A
L
Y
W
M
G
4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 9
1
Publication Order Number:
MC100EPT24/D
MC100EPT24
Table 1. PIN DESCRIPTION
VEE
D
1
2
8
LVTTL
VCC
7
PIN
Q
LVECL
NC
NC
3
Q
6
4
5
FUNCTION
Q, Q
Differential LVECL Outputs
D
LVTTL Input
VCC
Positive Supply
GND
Ground
VEE
Negative Supply
NC
No Connect
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect to
the most negative supply (GND) or
leave unconnected, floating open.
GND
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
181 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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MC100EPT24
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
Parameter
GND = 0 V
Condition 1
VEE = −3.3V
Condition 2
3.8
V
VEE
Negative Power Supply
GND = 0 V
VCC = 3.3V
−3.8
V
VIN
Input Voltage
GND = 0 V
VI v VCC
0 to VCC
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
Pb
Pb−Free
(Note 2)
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. LVTTL INPUT DC CHARACTERISTICS VCC = 3.3 V, VEE = −3.6 V to −3.0 V, GND = 0.0 V; TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
20
mA
IIH
Input HIGH Current
VIN = 2.7 V
IIHH
Input HIGH Current HIGH Voltage
VCC = VIN = 3.8 V
100
mA
IIL
Input LOW Current
VIN = 0.5 V
−0.6
mA
VIK
Input Clamp Voltage
IIN = −18 mA
−1.0
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. NECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, VEE = −3.3 V, GND = 0.0 V (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
VOH
Output HIGH Voltage (Note 4)
-1145
−1020
-895
-1145
−1020
-895
-1145
−1030
-895
mV
VOL
Output LOW Voltage (Note 4)
-1945
−1820
-1695
-1945
−1820
-1695
-1945
−1820
-1695
mV
ICC
Positive Power Supply Current
2.0
4.0
2.0
4.0
2.0
4.0
mA
IEE
Negative Power Supply Current
30
38
30
38
30
38
mA
20
20
20
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Output levels will vary 1:1 with GND. VEE can vary ± 0.3 V.
4. Outputs are terminated through a 50 W resistor to GND − 2 V.
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3
MC100EPT24
Table 6. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 5)
−40°C
Min
Characteristic
Symbol
fmax
Maximum Input Clock Frequency (Figure 2)
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 6)
tJITTER
RMS Random Clock Jitter (Figure 2)
tr
tf
Output Rise/Fall Times
(20% − 80%) @ 50 MHz
Typ
25°C
Max
Min
>1
300
Q, Q
70
Typ
85°C
Max
Min
Typ
>1
500
800
0.2
<1
125
170
300
80
Max
>1
530
800
0.2
<1
130
180
300
100
Unit
GHz
560
800
ps
0.2
<1
ps
150
200
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
RMS RANDOM CLOCK JITTER (ps)
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V.
6. Specifications for standard TTL input signal.
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
2
200
(JITTER)
100
1
0
100
300
500
700
900
1100
1300
INPUT CLOCK FREQUENCY (MHz)
Figure 2. Output Voltage Amplitude (VOUTpp)/RMS Jitter
vs. Input Clock Frequency at Ambient Temperature
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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4
MC100EPT24
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC100EPT24DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EPT24DR2
SOIC−8
2500 / Tape & Reel
MC100EPT24DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT24DT
TSSOP−8
100 Units / Rail
MC100EPT24DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EPT24DTR2
TSSOP−8
2500 / Tape & Reel
MC100EPT24DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT24MNR4
DFN8
1000 / Tape & Reel
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC100EPT24D
MC100EPT24MNR4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100EPT24
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100EPT24
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
V
S
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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7
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EPT24
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
TOP VIEW
0.08 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
(A3)
SIDE VIEW
A1
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100EPT24/D