MC100EPT24 LVTTL/LVCMOS to Differential LVECL Translator The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3V, +3.3V and ground are required. The small outline 8–lead SOIC package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium. The EPT24 is available in the 100E standard and is compatible with ECL 100K logic levels. • • • • • • • • • • • 350ps Typical Propagation Delay Maximum Frequency > 1.0GHz Differential ECL Outputs Small Outline SOIC Package PNP LVTTL Inputs for Minimal Loading Flow Through Pinouts Q Output will default HIGH with inputs open ESD Protection: 4000 KV HBM, 200 V MM Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 Transistor Count = 181 devices http://onsemi.com 8 1 SO–8 D SUFFIX CASE 751 MARKING DIAGRAM 8 A L Y W KPT24 ALYW = Assembly Location = Wafer Lot = Year = Work Week 1 *For additional information, see Application Note AND8002/D PIN DESCRIPTION VEE 1 8 VCC LVTTL D 2 7 Q LVECL NC 3 6 Q NC 4 5 GND PIN FUNCTION Q, Q Differential LVECL Outputs D LVTTL Input VCC Positive Supply GND Ground VEE Negative Supply ORDERING INFORMATION Device Figure 1. 8–Lead Pinout (Top View) and Logic Diagram Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 1 1 Package Shipping MC100EPT24D SOIC 98 Units/Rail MC100EPT24DR2 SOIC 2500 Tape & Reel Publication Order Number: MC100EPT24/D MC100EPT24 MAXIMUM RATINGS* Value Unit VEE Symbol Power Supply (VCC = 0V) Parameter –3.8 to 0 VDC VCC Power Supply (VEE = 0V) 3.8 to 0 VDC VI Input Voltage (VCC = 0V, VI not more negative than VEE) –3.8 to 0 VDC VI Input Voltage (VEE = 0V, VI not more positive than VCC) 3.8 to 0 VDC Iout Output Current 50 100 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature –65 to +150 °C θJA Thermal Resistance (Junction–to–Ambient) 190 130 °C/W θJC Thermal Resistance (Junction–to–Case) 41 to 44 ± 5% °C/W Tsol Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C Continuous Surge Still Air 500lfpm * Maximum Ratings are those values beyond which damage to the device may occur. LVTTL INPUT DC CHARACTERISTICS (VCC = 3.3V ±0.3V; GND = 0V; TA = –40°C to +85°C) Symbol Characteristic Min Typ Max Unit 20 µA IIH Input HIGH Current (Vin = 2.7V) IIHH Input HIGH Current MAX (Vin = 6.0V) 100 µA IIL Input LOW Current (Vin = 0.5V) –0.6 mA VIK Input Clamp Voltage (Iin = –18mA) –1.2 V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 V 0.8 V Max Unit LVECL OUTPUT DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; VEE = –3.3V ± 0.3V; GND = 0V) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ VOH Output HIGH Voltage (Note 1.) -1135 –1020 -885 -1135 –1020 -885 -1135 –1030 -885 mV VOL Output LOW Voltage (Note 1.) -1935 –1750 -1685 -1935 –1770 -1685 -1925 –1790 -1685 mV ICC Power Supply Current 2.0 4.0 2.0 4.0 2.0 4.0 mA 30 38 20 30 38 mA Max Min Max Unit IEE Power Supply Current 20 30 38 20 1. Output levels will vary 1:1 with GND; Outputs loaded through 50W to GND – 2.0V. AC CHARACTERISTICS (VCC = 3.3V ± 0.3V; VEE = –3.3V ± 0.3V; GND = 0V) –40°C Symbol Characteristic Min fmax Maximum Toggle Frequency (Note 2.) 1.0 tPLH, tPHL Propagation Delay to Output Differential (Note 3.) 300 tJITTER Cycle–to–Cycle Jitter Typ 25°C Max Min Typ 85°C 1.0 500 800 300 TBD 1.0 530 800 300 TBD tr Output Rise/Fall Times Q, Q 70 125 170 80 130 tf (20% – 80%) 2. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only. 3. TTL input of 0V to 3V. http://onsemi.com 2 Typ GHz 560 800 TBD 180 100 150 ps ps 200 ps MC100EPT24 PACKAGE DIMENSIONS SO–8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751–06 ISSUE T D A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 5 0.25 H E M B M 1 4 h B e X 45 _ q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S DIM A A1 B C D E e H h L q http://onsemi.com 3 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ MC100EPT24 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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