NLSV4T240E D

NLSV4T240E
4-Bit Dual-Supply Inverting
Level Translator
The NLSV4T240E is a 4−bit configurable dual−supply voltage
level translator. The input An and output Bn ports are designed to track
two different power supply rails, VCCA and VCCB respectively. Both
supply rails are configurable from 0.9 V to 4.5 V allowing universal
low−voltage translation from the input An to the output Bn port.
The NLSV4T240E is similar to the NLSV4T240; however, it has
enhanced power−off characteristics.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
UQFN12
MU SUFFIX
CASE 523AE
1
Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V
High−Speed w/ Balanced Propagation Delay
Inputs and Outputs have OVT Protection to 4.5 V
Non−preferential VCCA and VCCB Sequencing
Outputs at 3−State until Active VCC is Reached
Power−Off Protection
Outputs Switch to 3−State with VCCB at GND
Ultra−Small Packaging: 1.7 mm x 2.0 mm UQFN12
This is a Pb−Free Device
AEMG
G
AE = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
14
SOIC−14
D SUFFIX
CASE 751A
14
1
4T240EG
AWLYWW
1
14
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
14
1
Important Information
TSSOP−14
DT SUFFIX
CASE 948G
1
• ESD Protection for All Pins:
SV4T
240E
ALYWG
G
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
HBM (Human Body Model) > 6000 V
MM (Machine Model) > 300 V
ORDERING INFORMATION
Device
Package
Shipping†
NLSV4T240EMUTAG
UQFN12
(Pb−Free)
3000/Tape &
Reel
NLSV4T240EDR2G
SO−14
(Pb−Free)
2500/Tape &
Reel
NLSV4T240EDTR2G TSSOP14
(Pb−Free)
2500/Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 4
1
Publication Order Number:
NLSV4T240E/D
NLSV4T240E
OE
VCCA
1
A1
11
VCCB
2
10
B1
A2
3
9
B2
A3
4
8
B3
A4
5
7
B4
12
6
GND
(Top View)
OE VCCB B1
B2
B3
NC
B4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCCA
A1
A2
A3
A4
NC
GND
Figure 1. Pin Assignments
VCCA
VCCB
A1
B1
A2
B2
A3
B3
A4
B4
OE
Figure 2. Logic Diagram
TRUTH TABLE
PIN ASSIGNMENT
Pin
Inputs
Function
Outputs
OE
An
Bn
Output Port DC Power Supply
L
L
H
GND
Ground
L
H
L
An
Input Port
H
X
3−State
Bn
Output Port
OE
Output Enable
VCCA
Input Port DC Power Supply
VCCB
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2
NLSV4T240E
MAXIMUM RATINGS
Symbol
Rating
VCCA, VCCB
VI
Value
DC Supply Voltage
An
−0.5 to +5.5
V
OE
−0.5 to +5.5
V
(Power Down)
Bn
−0.5 to +5.5
(Active Mode)
Bn
−0.5 to +5.5
(Tri−State Mode)
Bn
−0.5 to +5.5
Control Input
VO
Unit
V
DC Input Voltage
VC
Condition
−0.5 to +5.5
DC Output Voltage
VCCA = VCCB = 0
V
V
V
IIK
DC Input Diode Current
−20
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
IO
DC Output Source/Sink Current
±50
mA
ICCA, ICCB
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCCA, VCCB
Positive DC Supply Voltage
VI
Bus Input Voltage
VC
Control Input
VIO
Bus Output Voltage
TA
Dt / DV
Min
Max
Unit
0.9
4.5
V
GND
4.5
V
OE
GND
4.5
V
(Power Down Mode)
Bn
GND
4.5
V
(Active Mode)
Bn
GND
VCCB
V
(Tri−State Mode)
Bn
GND
4.5
V
−40
+85
°C
0
10
nS
Operating Temperature Range
Input Transition Rise or Rate
VI, from 30% to 70% of VCC; VCC = 3.3 V ±0.3 V
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
VIH
VIL
Parameter
Test Conditions
Input HIGH Voltage
(An, OE)
Input LOW Voltage
(An, OE)
VCCA (V)
VCCB (V)
Min
Max
Unit
3.6 – 4.5
0.9 – 4.5
2.7
−
V
2.7 – 3.6
2.0
−
2.3 – 2.7
1.7
−
1.4 − 2.3
0.75 * VCCA
−
0.9 – 1.4
0.9 * VCCA
−
3.6 – 4.5
−
0.8
−
0.8
2.3 – 2.7
−
0.7
1.4 − 2.3
−
0.35 * VCCA
0.9 – 1.4
−
0.1 * VCCA
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3
0.9 – 4.5
2.7 – 3.6
V
NLSV4T240E
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
VOH
Parameter
Output HIGH Voltage
Test Conditions
VCCA (V)
VCCB (V)
Min
IOH = −100 mA; VI = VIH
0.9 – 4.5
0.9 – 4.5
VCCB – 0.2
−
IOH = −0.5 mA; VI = VIH
0.9
0.9
0.75 * VCCB
−
IOH = −2 mA; VI = VIH
1.4
1.4
1.05
−
IOH = −6 mA; VI = VIH
1.65
1.65
1.25
−
2.3
2.3
2.0
−
2.3
2.3
1.8
−
2.7
2.7
2.2
−
2.3
2.3
1.7
−
3.0
3.0
2.4
−
IOH = −24 mA; VI = VIH
3.0
3.0
2.2
−
IOL = 100 mA; VI = VIL
0.9 – 4.5
0.9 – 4.5
−
0.2
IOL = 0.5 mA; VI = VIH
1.1
1.1
−
0.3
IOL = 2 mA; VI = VIH
1.4
1.4
−
0.35
IOL = 6 mA; VI = VIL
1.65
1.65
−
0.3
IOL = 12 mA; VI = VIL
2.3
2.3
−
0.4
2.7
2.7
−
0.4
2.3
2.3
−
0.6
3.0
3.0
−
0.4
3.0
3.0
−
0.55
IOH = −12 mA; VI = VIH
IOH = −18 mA; VI = VIH
VOL
Output LOW Voltage
IOL = 18 mA; VI = VIL
IOL = 24 mA; VI = VIL
II
Max
Unit
V
V
Input Leakage Current
VI = VCCA or GND
0.9 – 4.5
0.9 – 4.5
−1.0
1.0
mA
IOFF
Power−Off Leakage Current
OE = 0 V
0
0.9 – 4.5
0.9 – 4.5
0
−1.0
−1.0
1.0
1.0
mA
ICCA
Quiescent Supply Current
VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5
0.9 − 4.5
−
2.0
mA
ICCB
Quiescent Supply Current
VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5
0.9 − 4.5
−
2.0
mA
ICCA + ICCB Quiescent Supply Current
VI = VCCA or GND;
IO = 0, VCCA = VCCB
0.9 – 4.5
0.9 – 4.5
−
4.0
mA
DICCA
Increase in ICC per Input Voltage,
Other Inputs at VCCA or GND
VI = VCCA – 0.6 V;
VI = VCCA or GND
4.5
3.6
4.5
3.6
−
10
5.0
mA
DICCB
Increase in ICC per Input Voltage,
Other Inputs at VCCA or GND
VI = VCCA – 0.6 V;
VI = VCCA or GND
4.5
3.6
4.5
3.6
−
10
5.0
mA
I/O Tri−State Output Leakage
Current (TA = 25°C, OE = VCCA)
VO = 0 V
4.5
4.5
−
1.0
mA
VO = 4.5 V
4.5
4.5
−
10
VO = 0 to 4.5 V
2.5
3.5
−
105
3.0
3.75
−
110
3.3
3.0
−
75
3.75
1.5
−
10
IOZ
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4
NLSV4T240E
TOTAL STATIC POWER CONSUMPTION (ICCA + ICCB)
−405C to +855C
VCCB (V)
4.5
VCCA (V)
Min
3.3
Max
Min
2.8
Max
Min
1.8
Max
Min
0.9
Max
Min
Max
Unit
4.5
2
2
2
2
< 1.5
mA
3.3
2
2
2
2
< 1.5
mA
2.8
<2
<1
<1
< 0.5
< 0.5
mA
1.8
<1
<1
< 0.5
< 0.5
< 0.5
mA
0.9
< 0.5
< 0.5
< 0.5
< 0.5
< 0.5
mA
NOTE:
Connect ground before applying supply voltage VCCA or VCCB. This device is designed with the feature that the power−up
sequence of VCCA and VCCB will not damage the IC.
AC ELECTRICAL CHARACTERISTICS
−405C to +855C
VCCB (V)
4.5
Symbol
tPLH,
tPHL
(Note 1)
tPZH,
tPZL
(Note 1)
tPHZ,
tPLZ
(Note 1)
tOSHL,
tOSLH
(Note 1)
Min
3.3
Max
Min
2.8
Max
Min
1.8
Max
Max
Unit
3.7
4.0
nS
4.0
4.3
3.9
4.2
4.5
4.0
4.2
4.5
4.8
4.3
4.5
4.8
5.0
4.4
4.8
5.2
5.7
6.2
4.7
5.1
5.5
6.0
6.5
2.8
4.9
5.3
5.7
6.2
6.7
1.8
5.2
5.6
6.0
6.5
7.0
1.5
5.5
5.9
6.3
6.8
7.3
Output
Disable,
4.5
4.4
4.8
5.2
5.7
6.2
3.3
4.7
5.1
5.5
6.0
6.5
OE to Bn
2.8
4.9
5.3
5.7
6.2
6.7
1.8
5.2
5.6
6.0
6.5
7.0
1.5
5.5
5.9
6.3
6.8
7.3
4.1
0.15
0.15
0.15
0.15
0.15
3.6
0.15
0.15
0.15
0.15
0.15
2.8
0.15
0.15
0.15
0.15
0.15
1.8
0.15
0.15
0.15
0.15
0.15
1.2
0.15
0.15
0.15
0.15
0.15
Parameter
VCCA (V)
Propagation
Delay,
4.5
3.0
3.2
3.4
3.6
3.3
3.5
3.7
An to Bn
2.8
3.5
3.7
1.8
3.8
1.5
4.1
Output
Enable,
4.5
3.3
OE to Bn
Output to
Output Skew,
Data to Output
Min
1.5
Max
Min
nS
nS
nS
1. Propagation delays defined per Figures 3 and 4.
CAPACITANCE
Symbol
Parameter
Test Conditions
Typ (Note 2)
Unit
CIN
Control Pin Input Capacitance
VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B
3.5
pF
CI/O
I/O Pin Input Capacitance
VCCA = VCCB = 3.3 V, VI = 0 V or VCCA/B
5.0
pF
CPD
Power Dissipation Capacitance
VCCA = VCCB = 3.3 V, VI = 0 V or VCCA, f = 10 MHz
20
pF
2. Typical values are at TA = +25°C.
3. CPD is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from:
ICC(operating) ^ CPD x VCC x fIN x NSW where ICC = ICCA + ICCB and NSW = total number of outputs switching.
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5
NLSV4T240E
VCC
Pulse
Generator
RL
DUT
CL
VCCO x 2
OPEN
GND
RL
Figure 3. AC (Propagation Delay) Test Circuit
Test
Switch
tPLH, tPHL
OPEN
tPLZ, tPZL
VCCO x 2
tPHZ, tPZH
GND
CL = 15 pF or equivalent (includes probe and jig capacitance)
RL = 2 kW or equivalent
ZOUT of pulse generator = 50 W
VIH
Input (An)
Vm
Vm
tPHL
tPLH
Output (Bn)
Vm
0V
VOH
Vm
VOL
Waveform 1 − Propagation Delays
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VIH
OEn
Vm
Vm
tPZH
0V
tPHZ
Output (Bn)
VOH
VY
Vm
≈0V
tPZL
tPLZ
≈ VCC
Vm
Output (Bn)
VX
VOL
Waveform 2 − Output Enable and Disable Times
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC (Propagation Delay) Test Circuit Waveforms
VCC
Symbol
3.0 V – 4.5 V
2.3 V − 2.7 V
1.65 V − 1.95 V
1.4 V − 1.6 V
0.9 V − 1.3 V
VmA
VCCA/2
VCCA/2
VCCA/2
VCCA/2
VCCA/2
VmB
VCCB/2
VCCB/2
VCCB/2
VCCB/2
VCCB/2
VX
VOL x 0.1
VOL x 0.1
VOL x 0.1
VOL x 0.1
VOL x 0.1
VY
VOH x 0.9
VOH x 0.9
VOH x 0.9
VOH x 0.9
VOH x 0.9
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6
NLSV4T240E
APPLICATIONS INFORMATION
(CL = 50 pF, RL = 2 kW, Rpull−up = 50 kW, test circuit shown in Figure 3)
Figure 5. Typical Tri−State Output
(CL = 50 pF, RL = R, RPull−up = 2 kW, test circuit shown in Figure 3)
Figure 6. Typical Tri−State Output
Figure 6 shows that the output may have a ‘shelf’ or a short
duration where the slope of the waveform is equal to zero if
no load resistance is connected to ground. The
NLSX4T240E was created from the NLSX4T240 to
minimize the ‘shelf’ of the waveform during the disable
time.
Typical tri−state output waveforms of the NLSX4T240E
are shown in Figures 5 and 6. The shape of the output
waveform during a tri−state condition corresponding to the
disable time (tPHZ, tpLZ) depends on the configuration of the
pull−up circuit. Figure 5 shows a smooth monotonically
increasing exponentially waveform because a 2 kW
resistance is connected between the output and ground.
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7
NLSV4T240E
PACKAGE DIMENSIONS
UQFN12 1.7x2.0, 0.4P
CASE 523AE−01
ISSUE A
ÉÉ
ÉÉ
ÉÉ
D
PIN 1 REFERENCE
2X
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH 0.03
MAX ON BOTTOM SURFACE OF
TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
A B
L1
DETAIL A
E
NOTE 5
TOP VIEW
DIM
A
A1
A3
b
D
E
e
K
L
L1
L2
DETAIL B
A
0.05 C
12X
0.05 C
A1
A3
8X
C
SIDE VIEW
SEATING
PLANE
K
5
7
DETAIL A
MOUNTING FOOTPRINT
SOLDERMASK DEFINED
e
1
12X
DETAIL B
OPTIONAL
CONSTRUCTION
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.70 BSC
2.00 BSC
0.40 BSC
0.20
---0.45
0.55
0.00
0.03
0.15 REF
11
L
L2
BOTTOM VIEW
2.00
12X
b
0.10
M
C A B
0.05
M
C
1
NOTE 3
0.32
2.30
0.40
PITCH
11X
0.22
12X
0.69
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
NLSV4T240E
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
7
1
G
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
−T−
SEATING
PLANE
M
S
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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9
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
NLSV4T240E
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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