CAT874 D

CAT874
Smart Phone Battery Switch
Controller
Description
CAT874 is a switch controller designed to start/shut−off smart
phones with the push button input or by phone microcontroller unit.
CAT874 monitors two inputs and outputs an active high output after
PWR_ON input has been active (logic low) for a factory preset
minimum time. Releasing input from its active state before the
minimum timeout period resets the internal timer and must return to
being active before the timer will restart with a fresh count down. The
output remains high until the next PWR_ON high−to−low or VCHG
low−to−high transition.
CAT874’s push pull output is capable of sinking up to 3 mA of
current.
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ULLGA−6
UL SUFFIX
CASE 613AF
Features
MARKING DIAGRAM
Operate on 1.8 V to 5.5 V Power Supplies
Ultra Low Quiescent Current: 100 nA (typical)
Schmitt Trigger Inputs
Small mLLGA−6 Package: 1.45 x 1.0 x 0.4 mm
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
X
= Specific Device Code
= ( = CAT874)
= Date Code
M
“P” written at 180° clockwise rotation
Typical Applications
•
•
•
•
XM
P
•
•
•
•
•
Mobile Phones
PDAs
MP3 Players
Personal Navigation Devices
PIN CONNECTIONS
PWR ON
1
VDD
VCHG
OUT
NIC
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 1
1
Publication Order Number:
CAT874/D
CAT874
Figure 2. Functional Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
PWR_ON
Power ON, CMOS input.
2
VCHG
Charger IN, CMOS input.
3
NIC
No Internal Connection. A voltage or signal applied to this pin will have no effect on device operation.
4
GND
System Ground.
5
OUT
Drive Output. Active−high push−pull output.
6
VDD
Positive Power Supply.
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage Range
VDD
−0.3 to 6
V
Output Voltage Range
VOUT
−0.3 to 6 or (VDD + 0.3), whichever is lower
V
Input Voltage; PWR_ON, VCHG
VIN
−0.3 to 6 or (VDD + 0.3), whichever is lower
V
Maximum Junction Temperature
TJ(max)
150
°C
Output Current; OUT
IOUT
10
mA
Storage Temperature Range
TSTG
−65 to 150
°C
ESD Capability, Human Body Model (Note 1)
ESDHBM
2
kV
ESD Capability, Machine Model (Note 2)
ESDMM
150
V
TSLD
260
°C
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
Max
Unit
Input Voltage; VDD
VDD
1.8
5.5
V
Input Voltage; PWR_ON, VCHG
VIN
0
VDD
V
Output Current; OUT
IOUT
0
3
mA
Ambient Temperature
TA
−40
85
°C
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CAT874
Table 4. ELECTRICAL OPERATING CHARACTERISTICS
(VDD = 1.8 V to 5.5 V. For typical values TA = 25°C, for min/max values TA = −40°C to +85°C unless otherwise noted.)
Parameter
Test Conditions
Symbol
Min
VDD
1.8
Typ
Max
Unit
5.5
V
1000
nA
50
mA
POWER
VDD Supply Voltage
Quiescent Supply Current
PWR_ON = VDD, VCHG = 0 V
Operating Supply Current
PWR_ON = 0 V, VCHG = 0 V
Measured during setup period.
Measurement includes current
through internal 200 kW pull−up
resistor on PWR_ON
IDD
100
LOGIC INPUTS AND OUTPUTS
Input Voltage; HIGH
PWR_ON, VCHG
VIH
Input Voltage; LOW
PWR_ON, VCHG
VIL
Hysteresis
0.7 x VDD
V
0.25 x VDD
VHYS
250
V
mV
Input Current VCHG
VCHG = 0 V; VDD = 5 V
(internal pull−down)
IIL1
50
300
Input Current VCHG
VCHG = 5 V; VDD = 5 V
(internal pull−down)
IIH1
25
mA
Input Current PWR_ON
PWR_ON = 0 V; VDD = 5 V
(internal 200 kW pull−up resistor)
IIL2
25
mA
Input Current PWR_ON
PWR_ON = 5 V; VDD = 5 V
(internal 200 kW pull−up resistor)
IIH2
50
Output Voltage; HIGH
ISOURCE = −0.1 mA, VDD = 1.8 V
VOH
Output Voltage; LOW
ISINK = 3 mA, VDD = 1.8 V
VOL
300
VDD − 0.2
nA
nA
V
0.1
0.4
V
8.00
9.44
s
TIMING
Input Delay PWR_ON
tlow_delay
TA = 25°C
TA = −40°C to +85°C
6.56
6.00
10.00
TEST MODE (VDD = 5 V, TA = 25°C) (Note 3)
tST
Start TEST Window
35
ms
Test Mode Delay
PWR_ON = 0 V, VCHG → 7
cycles, delay measured after 8th
rising edge of VCHG clock pulse
tD
250
ms
Test Mode Clock Frequency
Clock applied to VCHG
ftm
1
MHz
PWR_ON Test Mode Clock Setup
Time
Measured from PWR_ON falling
edge to first falling edge of VCHG
tP
VCHG Input Voltage; LOW
VCHG, Test Mode Operation
1
ms
VIL_TM
VCHG Pulse Width
tpw
3. “Test Mode” parameters are not tested in production.
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3
0.2 x VDD
500
V
ns
CAT874
TIMING WAVEFORMS
H
VBAT
L
H
VCHG
L
H
PWRON
L
H
OUT
L
<8s
8s
if PWRON is
LOW for less
than 8s, OUT
remains LOW
tlow_delay
8s
After a H−to−L
transition on
PWRON, OUT
goes LOW
8s
After a L−to−H
transition on
VCHG, OUT
goes LOW
8s
VBAT goes
LOW & VCHG
is low the circuit
powers down
if PWRON is
LOW for more
than 8s, OUT
goes HIGH
A L−to−H transition
on VCHG if VBAT
is LOW causes a
power−on and OUT
remains LOW
Figure 3. Timing Waveforms
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4
8s
After a H−to−L
transition on VCHG
if VBAT is HIGH,
OUT remains
unchanged
A L−to−H transition
on VCHG if VBAT
is HIGH causes
nothing if OUT is
already LOW
CAT874
SYSTEM DESCRIPTION AND APPLICATIONS INFORMATION
General
When PWR_ON goes low, an internal timing cycle is
initiated. If it goes high before the countdown timer has
concluded its cycle, the timer will reset and will restart from
the beginning when PWR_ON returns to being low.
CAT874 is designed for the manual switching of
microprocessors and microcontrollers. To prevent
accidental resets, CAT874 requires PWR_ON input be held
low for a prescribed period before an Active high output is
issued to the system processor.
Output (OUT)
CAT874 provides an active−high push pull output. This
output will sink up to 3 mA.
PWR_ON and VCHG Inputs
PWR_ON and VCHG are Schmitt trigger CMOS inputs.
PWR_ON must go low and stay low for a predetermined
period (tLOW_DELAY) to generate an Active high on the
output.
VCHG is a standard CMOS input with internal pull down
resistor 200 kW to keep the input low when charger is not
plugged in and PWR_ON is also a CMOS input with an
internal 200 kW pull−up resistor, thus PWR_ON can be left
floating.
Delay Timer Testing:
A user test mode is provided to reduce the system test time
after the CAT874 is mounted on the board. Instead of
waiting tLOW_DELAY for the output to go active.
The user brings PWR_ON low, and sends seven positive
edges on the VCHG pin in a window of time tST. After a delay
tD, the device output will change state from low to high, and
will return to the low state only when there is a high−to−low
transition on PWR_ON.
PWR_ON
V_CHG
1
OUT
2
3
4
5
6
7
8
tP
tST
tD
Figure 4. TOC Mode
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CAT874
APPLICATION INFORMATION
Output Operation
An external resistor 1M should be used OUT, to discharge
the output when both sources turn off.
System with Two Different Power Supply Voltages
When both VCHG and VBAT are present, the following
application can be adapted. Schottky diodes D1 and D2 can
be used to isolate the two sources. The higher source will
supply the VDD power.
If VCHG is not present then drop across D2 should be low
enough to turn off Q1. If both VCHG and VBAT are present,
the timing waveforms should be used as shown in Figure 4.
Operation with Low VDD Voltage and Brownout
Condition
The CAT874 requires a minimum supply voltage VDD of
1.8 V to guarantee the normal operation within the
specification. To prevent small VDD supply glitch, a small
ceramic capacitor can be added between the VDD pin and
GND.
D2
D1
VCHG
VBAT
Battery
0.1 mF
NTLUS3A18P2
VDD
PWR_ON
PWR_ON
OUT
VCHG
Q1
P−MOS
CAT874
1 MW
GND
D3
NTLUS3A18P2
Q2
P−MOS
DRV
PWR_ON
V_SYS
PMU
Figure 5. Application Schematic in Dual Supply System
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CAT874
PACKAGE DIMENSIONS
ULLGA6, 1.45x1.0, 0.5P
CASE 613AF−01
ISSUE A
PIN ONE
REFERENCE
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
4. A MAXIMUM OF 0.05 PULL BACK OF THE
PLATED TERMINAL FROM THE EDGE OF THE
PACKAGE IS ALLOWED.
A
B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
E
DIM
A
A1
b
D
E
e
L
L1
TOP VIEW
0.10 C
0.05 C
MILLIMETERS
MIN
MAX
−−−
0.40
0.00
0.05
0.15
0.25
1.45 BSC
1.00 BSC
0.50 BSC
0.25
0.35
0.30
0.40
A
6X
0.05 C
SEATING
PLANE
SIDE VIEW
MOUNTING FOOTPRINT
SOLDERMASK DEFINED*
C
A1
5X
6X
0.49
e
5X
L
0.30
NOTE 4
3
1
L1
1.24
6
4
BOTTOM VIEW
6X
0.53
b
0.10 C A B
0.05 C
1
0.50
PITCH
PKG
OUTLINE
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Table 5. ORDERING INFORMATION
Timeout (s)
8
Marking
P
Device
CAT874−80ULGT3
M
“P” written at 180° clockwise rotation
Package
Shipping (Note 4)
mLLGA−6
3,000 / Tape & Reel
4. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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Sales Representative
CAT874/D