Ordering number : ENA1899A LV5710GP Bi-CMOS LSI Power Supply for Charge Pump for Camera Sensor http://onsemi.com Overview The LV5710GP is power supply for charge pump for camera sensor. Functions Regulating the 5V input by boosting it three-fold with the charge pump to the specified voltage. Output voltage variable with external resistor. Soft start function incorporated, which reduces the rush current at start of charge pump. Timer-latch type short-circuit protective function incorporated. VCT20 3x3, 0.5P Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Allowable power dissipation Symbol Conditions Ratings VDD max Pd max with specified substrate * Unit 6.0 V 0.55 W Operating temperature Topr 20 to +80 C Storage temperature Tstg 40 to +125 C * : Specified substrate : 114.3mm76.1mm1.6mm, glass epoxy board Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ratings at Ta = 25C Ratings Parameter Symbol Conditions Unit min Supply voltage VDD Input “H” voltage VINH Input “L” voltage VINL typ max 4.5 5.5 V EN pin 1.5 VDD V EN pin 0.1 0.4 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ORDERING INFORMATION See detailed ordering and shipping information on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2014 August, 2014 80614HK/D0810SY 20101125-S00002 No.A1899-1/7 LV5710GP Electrical Characteristics at Ta = 25°C, VDD = 5V, IOUT = 30mA, S0 = L, S1 = L, Unless otherwise specified Ratings Parameter Symbol Conditions Unit min Circuit current drain IDD1 EN = L IDD2 EN = H No load typ Output load current IO ave At VOUT = 12V setting Reference voltage VREF VDD = 4.5 to 5.5V 1.285 Ta = 20°C to +80°C, Design value 1.279 Output voltage at OFF VOFF Protective circuit masking time Tmask 50 After capacitive discharge max 1 A 12 18 mA 30 mA 1.305 1.325 1.331 V V 0 50 mV 18 33 ms 35 50 65 mA 82.5 87.5 92.5 % 10 ms 30 40 mV 40 50 A 1 A 300 mA 2.3 MHz Masking time from detection of short-circuit to IC OFF Short-circuit protective current Ilim Short-circuit protective voltage SS end time Vlim TSSEND Time from EN = H to regulator SS OFF Ta = 20°C to +80°C Design value RO load regulation RO Input pin current Iin Load 1mA 30mA Pins EN 30 S0 and S1 pins Power efficiency Peff CP+regulator Rush current Irush No load Oscillation frequency f clk 70 1.4 1.8 % Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Pd max -- Ta Allowable power dissipation, Pd max – W 0.8 Mounted on a substrate : 114.3×76.1×1.6mm3 glass epoxy 0.6 0.55 0.4 0.25 0.2 0 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C No.A1899-2/7 LV5710GP Package Dimensions unit : mm VCT20 3x3, 0.5P CASE 601AB ISSUE A SOLDERING FOOTPRINT* 2.70 (Unit: mm) GENERIC MARKING DIAGRAM* XXXXXX YDD 2.70 XXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data *This information is generic. Please refer to device data sheet for actual part marking. 0.70 0.20 0.30 0.50 NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb- Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. No.A1899-3/7 LV5710GP NC RO FB EN SVDD 20 19 18 17 16 Pin Assignment S1 CPO 1 15 NC 2 14 TEST C2P 3 13 S0 NC 4 12 C1P 5 11 6 7 8 9 10 PVDD NC C2M C1M PGND LV5710GP SGND NC Top view Pin Function Pin No. Name 1 CPO 2 NC 3 C2P 4 NC 5 C1P 6 PVDD Function Boost voltage output (6VDD or 5VDD) Boost capacitor connection pin (charge transfer side) Boost capacitor connection pin (charge transfer side) Power system VDD pin 7 NC 8 C2M Boost capacitor connection pin (driver side) 9 C1M Boost capacitor connection pin (driver side) 10 PGND 11 NC 12 SGND Power GND pin for the charge pump Small signal system GND pin 13 S0 14 TEST Charge pump frequency changeover pin Test pin (open or short-circuited to GND) 15 S1 Charge pump frequency changeover pin 16 SVDD 17 EN System enable pin (Hi active) 18 FB Regulator FB pin 19 RO Regulator output pin 20 NC Small signal system VDD pin No.A1899-4/7 LV5710GP Block Diagram RO PVDD 1μF FB PGND + - 4.7μF vref CPO 1μF SVDD bandgap voltage reference 1μF Timing Control Step-Up Circuit C2P SGND C1P 2bit MUX S0 0.22μF S1 Divider EN 2MHz OSC C1M C2M active Sequence Control Block Equivalent Circuit Diagram PVDD VIN = 4.5V to 5.5V M1 M2 M3 C1P + - +3VIN CPO C2P VIN + - 2VIN Vref 3VIN + VOUT RO C1M CLK FB C2M No.A1899-5/7 LV5710GP Output Voltage Setting Method The output voltage of IC-incorporated LDO can be determined as follows : VH = R1+R2 R2 VREF For example, to set the output voltage to 12V, set the resistance Value to R1 = 1070k/R2 = 130k. CPO RO R1 VREF = 1.3V FB R2 Short-circuit Protective Operation The RO output pin has the short-circuit protective function. The over-current detector circuit outputs the detection signal when the output current of 50mA (typ) or more flows or when the output voltage drops below 87.5% (typ). When this detection signal is output continuously for 18ms (typ) or more, IC determines that there is over-current and stops the output. To reset from the stop state, set the EN pin to “L”, then set the EN pin to “H” again. CPO RO + Output voltage FB detection comparator 0.875 × VREF Short-circuit + detection signal - Output current detection comparator VREF Equivalent circuit of the over-current detection circuit Selecting the Frequency According to the logic of S0 and S1, the charge pump operation frequency can be changed. In the case of light load, the reactive power can be reduced by decreasing the operating frequency. S0 S1 L L CP operating frequency 1MHz H L 500kHz L H 250kHz H H 125kHz No.A1899-6/7 LV5710GP Startup sequence Set EN = H after setting VDD = 4.5V or more Stop with EN = L or for overcurrent protection Never allow VDD to decrease below 4.5V till EN = L is established VDD EN Charge pump output CPO Regulator output RO S0 Frequency selection Do not allow the signal to change Frequency selection Do not allow the signal to change Frequency selection S1 Frequency selection Do not allow the signal to change Frequency selection Do not allow the signal to change Frequency selection * CP clock 1MHz * CP clock 500kHz * CP clock 250kHz * CP clock 125kHz * IC internal signal Start at 1MHz Steady operation SS end 10ms (max) Start at 1MHz Steady operation SS end 10ms (max) EN Pin and VDD The sequence operation is made at startup. However, startup is not made when the internal circuit has not been reset. To reset the internal circuit, keep the EN pin to “L” till VDD becomes 4.5V or more. Note that VDD and EN pin cannot be short-circuited for this purpose. ORDERING INFORMATION Device LV5710GP-TE-L-H Package VCT20 3x3, 0.5P (Pb-Free / Halogen Free) Shipping (Qty / Packing) 2000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. 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