INTERSIL ISL90460

ISL90460
®
Single Volatile 32-Tap XDCP™
Data Sheet
October 7, 2005
FN8225.3
Digitally Controlled Potentiometer (XDCP)
Features
The Intersil ISL90460 is a digitally controlled potentiometer
(XDCP). Configured as a variable resistor, the device
consists of a resistor array, wiper switches, a control section,
and volatile memory. The wiper position is controlled by a
2-pin Up/Down interface.
• Volatile Solid-State Potentiometer
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS and U/D inputs.
• 32 Wiper Tap Points
The device can be used in a wide variety of applications
including:
• Available RTOTAL Values = 10kΩ, 50kΩ, 100kΩ
• LCD contrast control
• Parameter and bias adjustments
• Packages
- 5 Ld SC-70, SOT-23
• Industrial and automotive control
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
Pinout
• 2-pin UP/DN Interface
• DCP Terminal Voltage, 2.7V to 5.5V
• Tempco 35ppm/°C Typical
• Low Power CMOS
- Active current 25µA max.
- Supply current 0.3µA
• Temp Range -40°C to +85°C
ISL90460
(5 LD SOT-23, SC-70)
TOP VIEW
• Laser Diode driver biasing
• Gain control and offset adjustment
RH
VDD
GND
CS
U/D
Ordering Information
PART NUMBER
PART MARKING
RTOTAL (K)
TEMP RANGE (°C)
10
-40 to +85
PACKAGE (Tape and Reel)
AJM
ISL90460WIE527Z-TK (See Note)
DDY
-40 to +85
5 Ld SC-70 (Pb-free)
P5.049
ISL90460WIH527-TK
AJV
-40 to +85
5 Ld SOT-23
P5.046
ISL90460WIH527Z -TK (See Note) DDZ
50
5 Ld SC-70
PKG. DWG. #
ISL90460WIE527-TK
P5.049
-40 to +85
5 Ld SOT-23 (Pb-free)
P5.046
-40 to +85
5 Ld SC-70
P5.049
ISL90460UIE527-TK
AJN
ISL90460UIE527Z-TK (See Note)
DDW
-40 to +85
5 Ld SC-70 (Pb-free)
P5.049
ISL90460UIH527-TK
AJX
-40 to +85
5 Ld SOT-23
P5.046
ISL90460UIH527Z -TK (See Note)
DDX
ISL90460TIE527-TK
AJO
ISL90460TIE527Z-TK (See Note)
ISL90460TIH527-TK
ISL90460TIH527Z-TK (See Note)
-40 to +85
5 Ld SOT-23 (Pb-free)
P5.046
-40 to +85
5 Ld SC-70
P5.049
DDU
-40 to +85
5 Ld SC-70 (Pb-free)
P5.049
AJW
-40 to +85
5 Ld SOT-23
P5.046
DDV
-40 to +85
5 Ld SOT-23 (Pb-free)
P5.046
100
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL90460
Block Diagram
Pin Descriptions
VCC
SOT-23/SC-70
5-PIN
SYMBOL
1
VDD
Supply voltage
2
GND
Ground
3
U/D
Up - Down
AND
4
CS
Chip select
MEMORY
5
RH
High terminal/Wiper terminal
UP/DOWN
RH
(U/D)
CONTROL
DEVICE SELECT
DESCRIPTION
(CS)
GND (GROUND)
GENERAL
2
FN8225.3
October 7, 2005
ISL90460
Absolute Maximum Ratings
Recommended Operating Conditions
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, U/D and VCC with Respect to GND . . . . -1V to +7V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mW
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Potentiometer Specifications Over recommended operating conditions unless otherwise stated
SYMBOL
RTOT
VR
MIN
TYP
(Note 4)
MAX
UNIT
W version
8
10
12
kΩ
U version
40
50
60
kΩ
T version
80
100
120
kΩ
VCC
V
PARAMETER
End to end resistance
CONDITIONS
RH, RL terminal voltages
Noise
0
Ref: 1kHz
RW
Wiper Resistance
IW
Wiper Current
Resolution
dBV
600
Ω
1
Absolute linearity (Note 1)
RH(n)(actual) - RH(n)(expected)
Relative linearity (Note 2)
RH(n+1) - [RH(n)+MI]
RTOTAL temperature coefficient
CH/CL/CW
-120
Potentiometer capacitances
See equivalent circuit
0.6
mA
32
Taps
±1
MI
(Note 3)
±0.5
MI
(Note 3)
±35
ppm/°C
10/10/25
pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (RH(n)(actual) - RH(n)(expected)) = ±1 Ml Maximum.
n = 1 .. 29 only.
2. Relative linearity is a measure of the error in step size between taps = RH(n+1) - [RH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only.
3. 1 Ml = Minimum Increment = RTOT/31.
4. Typical values are for TA = 25°C and nominal supply voltage.
Equivalent Circuit
RTOTAL
RL
RH
CW
CH
CL
RW
3
FN8225.3
FN8225.2
October
June 6,
7, 2005
ISL90460
DC Electrical Specifications
SYMBOL
Over recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
MAX
UNIT
25
µA
1
µA
ICC
VCC active current (Increment)
CS = 0V, U/D = fclock = 1MHz and
VCC = 3V
ISB
Standby supply current
CS = VCC, U/D = VSS or VCC = 3V
ILI
CS input leakage current
VIN = VSS to VCC
±1
µA
ILI
U/D input leakage current
VIN = VSS to VCC
±1
µA
VIH
CS, U/D input HIGH voltage
VIL
CS, U/D input LOW voltage
CIN
CS, U/D input capacitance
Timing Specifications
0.3
VCC x 0.7
V
VCC x 0.3
VCC = 3V, VIN = VSS, TA = 25°C,
f = 1MHz
V
10
pF
Over recommended operating conditions unless otherwise specified) (Figures 1 and 2)
SYMBOL
PARAMETER
MIN
TYP (Note 4)
MAX
UNIT
tCU
U/D to CS setup
25
ns
tCI
CS to U/D setup
50
ns
tIC
CS to U/D hold
25
ns
tlL
U/D LOW period
300
ns
tlH
U/D HIGH period
300
ns
fTOGGLE
Up/Down toggle rate
1
MHz
tSETTLE
Output settling time
1
µs
CS
tCU
tIC
tIL
U/D
tCI
tIH
tSETTLE
RH
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM, INCREMENT
4
FN8225.3
October 7, 2005
ISL90460
CS
tCU
tIC
tIH
U/D
tCI
tIL
tSETTLE
RH
FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM, DECREMENT
Pin Descriptions
Principles of Operation
RH
There are two sections of the ISL90460: the input control,
counter and decode section; and the resistor array. The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a single
electronic switch connecting a point on the resistor array to
the wiper output. The resistor array is comprised of 31
individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the connection at that point to the wiper. The wiper
is connected to the RH terminal, forming a variable resistor
from RH to GND.
The ISL90460 contains a digital potentiometer connected as
a rheostat or variable resistor. The wiper and one terminal of
the digital potentiometer is tied to the RH pin, and the other
terminal of the potentiometer is tied to the ground pin (GND).
The resistance from the RH pin to ground will vary with the
potentiometer setting; at the highest setting, the resistance
will be the maximum (Rtot), at the lowest setting it will be a
minimum.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in volatile memory when CS
is returned HIGH. When CS is high, the device is placed in
low power standby mode.
The direction of the wiper movement is defined when the
device is selected. If during CS transition from High to Low
the U/D input is LOW, the wiper will move down on each
rising edge of U/D toggling. Similarly, the wiper will move up
on each rising edge of U/D toggling if, during CS transition
from High to Low, the U/D input is High.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
If the wiper is moved several positions, multiple taps are
connected to the wiper for tSETTLE (U/D to RH change). The
2-terminal resistance value for the device can temporarily
change by a significant amount if the wiper is moved several
positions.
5
FN8225.3
FN8225.2
October
June 6,
7, 2005
ISL90460
Small Outline Transistor Plastic Packages (SOT23-5)
P5.064
D
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES
5
SYMBOL
4
E
CL
1
2
CL
3
e
E1
b
CL
α
0.20 (0.008) M
C
C
CL
A
A2
SEATING
PLANE
A1
-C-
WITH
b
PLATING
b1
c
c1
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.036
0.057
0.90
1.45
-
A1
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.012
0.020
0.30
0.50
-
b1
0.012
0.018
0.30
0.45
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0374 Ref
0.95 Ref
-
e1
0.0748 Ref
1.90 Ref
-
L
0.10 (0.004) C
MIN
0.014
0.022
0.35
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
5
5
4
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.10
0.25
α
0o
8o
0o
8o
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
4X θ1
VIEW C
6
FN8225.3
October 7, 2005
ISL90460
Small Outline Transistor Plastic Packages (SC70-5)
P5.049
D
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES
5
SYMBOL
4
E
CL
1
2
CL
3
e
E1
b
CL
0.20 (0.008) M
C
C
CL
A
A2
SEATING
PLANE
A1
-C-
PLATING
b1
0.043
0.80
1.10
-
0.004
0.00
0.10
-
A2
0.031
0.039
0.80
1.00
-
b
0.006
0.012
0.15
0.30
-
b1
0.006
0.010
0.15
0.25
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.009
0.08
0.20
6
D
0.073
0.085
1.85
2.15
3
E
0.071
0.094
1.80
2.40
-
E1
0.045
0.053
1.15
1.35
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0512 Ref
1.30 Ref
-
L2
c1
NOTES
0.031
0.010
0.018
0.017 Ref.
0.26
0.46
4
0.420 Ref.
0.006 BSC
0o
N
c
MAX
0.000
α
WITH
MIN
A
L
b
MILLIMETERS
MAX
A1
L1
0.10 (0.004) C
MIN
-
0.15 BSC
8o
0o
5
8o
-
5
5
R
0.004
-
0.10
-
R1
0.004
0.010
0.15
0.25
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
L2
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
4X θ1
VIEW C
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
FN8225.3
October 7, 2005