X93156 ® Data Sheet September 16, 2005 Digitally Controlled Potentiometer (XDCP™) FN8182.2 Features • Solid-state potentiometer The Intersil X93156 is a three-terminal digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by an Up/Down interface. The potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including the programming of bias voltages, LCD brightness and contrast control as well as the implementation of ladder networks. • Up/Down interface • 32 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up • 31 resistive elements - Temperature compensated - Maximum resistance tolerance of ± 25% - Terminal voltage, 0 to VCC • Low power CMOS - VCC = 2.7 V - 5.5 V - Active current, 200µA typ. - Standby current, 2µA max. • High reliability - Endurance 200,000 data changes per bit - Register data retention, 100 years • RTOTAL value = 12.5kΩ, 50kΩ • Packages - 8 Ld MSOP, TDFN - Pb-free plus anneal available (RoHS compliant) Pinouts X93156 (8 LD TDFN) TOP VIEW X93156 (8 LD MSOP) TOP VIEW 8 VCC 7 CS 3 6 RL 4 5 Rw INC 1 U/D 2 RH VSS X93156 INC 1 U/D 2 RH VSS 3 4 X93156 8 VCC 7 CS 6 RL 5 Rw **Contact factory for TDFN ordering info. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X93156 Ordering Information PART NUMBER PART MARKING X93156WM8I RTOTAL (kΩ) TEMP RANGE (°C) 12.5 -40 to +85 8 Ld MSOP -40 to +85 8 Ld MSOP (Pb-free) M8.118 -40 to +85 8 Ld MSOP M8.118 -40 to +85 8 Ld MSOP (Pb-free) M8.118 -40 to +85 8 Ld MSOP M8.118 -40 to +85 8 Ld MSOP (Pb-free) M8.118 X93156WM8IZ (See Note) X93156WM8I-2.7* (AGR) X93156WM8IZ-2.7* (See Note) X93156UM8I-2.7* (AGP) 50 X93156UM8IZ-2.7* (See Note) PACKAGE PKG. DWG. # M8.118 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add “T1” suffix for tape and reel. Block Diagram VCC (Supply Voltage) U/D INC CS 30K 5-Bit Up/Down Counter 30 29 RH Up/Down (U/D) Control and Memory Increment (INC) RH 31 5-Bit Nonvolatile Memory RW Device Select Store and Control Recall Circuitry (CS) RL 28 One of Thirty Two Decoder Transfer Gates Resistor Array RW 2 1 VCC 0 VSS (Ground) VSS RL General Detailed Pin Descriptions MSOP, TDFN SYMBOL BRIEF DESCRIPTION 1 INC Increment (INC). The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 2 U/D Up/Down (U/D). The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. 3 RH RH. The RH and RL pins of the X93156 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input. 4 VSS Ground. 5 Rw RW. The Rw pin of the X93156 is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer. 6 RL RL. The RH and RL pins of the X93156 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input. 7 CS Chip Select (CS). The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete, the X93156 will be placed in the low power standby mode until the device is selected once again. 8 VCC Supply Voltage. 2 FN8182.2 September 16, 2005 X93156 Absolute Maximum Ratings Thermal Information Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on CS, INC, U/D, RH, RL and VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6.5V Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C Maximum reflow temperature (40s) . . . . . . . . . . . . . . . . . . . . . 240°C Maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA Thermal Resistance (Typical, Note 1) θJA (°C/W) 8 Ld MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Recommended Operating Conditions Temperature Range Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V (Note 8) CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Potentiometer Specifications Over recommended operating conditions unless otherwise stated. SYMBOL RTOT VR PARAMETER TEST CONDITIONS/NOTES End to end resistance RH, RL terminal voltages MIN TYP MAX UNIT 9.375 12.5 15.625 kΩ 37.5 50 62.5 kΩ VCC V 1 mW (Note 7) 0 Power rating Noise Ref: 1kHz RW Wiper Resistance IW Wiper Current -120 (Note 6) Resolution CH/CL/CW dBV (Note 7) 1100 Ω ±0.6 mA 3 Absolute linearity (Note 2) VH(n)(actual)-VH(n)(expected) Relative linearity (Note 3) VH(n+1)-[VH(n)+MI] RTOTAL temperature coefficient (Note 7) Potentiometer capacitances See circuit #2 % ±1 MI (Note 4) ±0.5 MI (Note 4) ±35 ppm/°C 10/10/25 pF (Note 7) NOTES: 2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VH(n)(actual)-VH(n)(expected)) = ±1 Ml Maximum. n = 1 .. 29 only 3. Relative linearity is a measure of the error in step size between taps = VH(n+1)—[VH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only. 4. 1 Ml = Minimum Increment = RTOT/31. 5. Typical values are for TA = 25°C and nominal supply voltage. 6. This parameter is periodically sampled and not 100% tested 7. This parameter is not 100% tested. 8. When performing multiple write operations, VCC must not decrease by more than 150mV from it’s initial value. 3 FN8182.2 September 16, 2005 X93156 DC Electrical Specifications SYMBOL ICC1 ICC2 ISB Over recommended operating conditions unless otherwise specified. TYP (Note 5) MAX UNIT CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCYC VCC=3V 50 250 µA CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCYC VCC = 5V 200 300 µA CS = VIH, U/D = VIL or VIH and INC = VIH @ max. tWR VCC = 3V 600 µA CS = VIH, U/D = VIL or VIH and INC = VIH @ max. tWR VCC = 5V 1400 µA CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VCC = 3V 1 µA CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VCC = 5V 2 µA ±1 µA PARAMETER TEST CONDITIONS VCC active current (Increment) VCC active current (Store) (EEPROM Store) Standby supply current MIN ILI CS input leakage current VIN = VCC ILI CS input leakage current VCC = 3V, CS = 0 60 100 150 µA ILI CS input leakage current VCC = 5V, CS = 0 120 200 250 µA ILI INC, U/D input leakage current VIN = VSS to VCC ±1 µA VIH CS, INC, U/D input HIGH voltage VCC x 0.7 VCC + 0.5 V VIL CS, INC, U/D input LOW voltage -0.5 VCC x 0.1 V 10 pF CIN CS, INC, U/D input capacitance (Notes 7, 8) VCC = 3V, VIN = VSS, TA = 25°C, f = 1MHz Circuit #2 SPICE Macro Model Endurance and Data Retention PARAMETER MIN UNIT Minimum endurance 200,000 Data changes per bit Data retention 100 RTOTAL RH Years CH CL CW RL 10pF 25pF Test Circuit #1 10pF Test Point VH/RH AC Conditions of Test AC Electrical Specifications SYMBOL Input pulse levels 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V Over recommended operating conditions unless otherwise specified. PARAMETER MIN TYP MAX UNIT tCl CS to INC setup 100 ns tlD INC HIGH to U/D change 100 ns tDI U/D to INC setup 100 ns tlL INC LOW period 1 µs tlH INC HIGH period 1 µs tlC INC Inactive to CS inactive 1 µs 250 ns tCPH CS Deselect time (NO STORE) 4 FN8182.2 September 16, 2005 X93156 AC Electrical Specifications SYMBOL Over recommended operating conditions unless otherwise specified. (Continued) PARAMETER MIN TYP MAX UNIT tCPH CS Deselect time (STORE) 10 ms tCYC INC cycle time 2 µs tR , tF (Note 7) INC input rise and fall time tR VCC (Note 7) VCC power-up rate tWR 0.2 Store cycle 500 µs 10,000 V/ms 10 ms 5 A.C. Timing CS tCYC tCI tIL tIC tIH tCPHNS tCPHS 90% 90% 10% INC tID tDI tF tR U/D tIW MI RW (Note 4) Power Up and Down Requirements Up/Down (U/D) There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH and VL, i.e., VCC ≥ VH,VL. The VCC ramp rate spec is always in effect. The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Pin Descriptions RH and RL The RH and RL pins of the X93156 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input. Rw Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X93156 will be placed in the low power standby mode until the device is selected once again. The Rw pin of the X93156 is the wiper terminal of the potentiometer which is equivalent to the movable terminal of a mechanical potentiometer 5 FN8182.2 September 16, 2005 X93156 Principles of Operation There are three sections of the X93156: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a five bit counter. The output of this counter is decoded to select one of thirty two wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. In order to avoid an accidental store during power-up, CS must go HIGH with VCC during initial power-up. When left open, the CS pin is internally pulled up to VCC by an internal 30K resistor. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, or other system trim requirements. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Mode Selection CS INC U/D MODE L H Wiper Up L L Wiper Down H X Store Wiper Position X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) H Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance The system may select the X93156, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recalled the previously stored data. In order to recall the stored position of the wiper on power-up, the CS pin must be held HIGH. 6 FN8182.2 September 16, 2005 X93156 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X θ A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C MIN MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- - 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N -A- 0.65 BSC E L1 e D SYMBOL e L1 MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 7 FN8182.2 September 16, 2005 X93156 Thin Dual Flat No-Lead Plastic Package (TDFN) 2X L8.2.5x2 0.15 C A A D 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C B SYMBOL E 6 MIN 0.75 0.80 - A1 - - 0.05 - D2 // 0.10 SIDE VIEW D2 (DATUM B) C 0.08 C A3 7 8 D2/2 1 6 INDEX AREA 0.20 0.25 0.30 5, 8 1.10 7, 8 2.00 BSC 0.90 E E2 A C SEATING PLANE 0.20 REF D B NOTES 0.70 b TOP VIEW MAX A A3 INDEX AREA NOMINAL 1.00 - 2.50 BSC 1.20 e 1.30 1.40 7, 8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 8 Nd 4 2 3 Rev. 0 8/05 2 NX k NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. (DATUM A) 3. Nd refers to the number of terminals on D. E2 4. All dimensions are in millimeters. Angles are in degrees. E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. NX L N N-1 e 8 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX b 5 0.10 (Nd-1)Xe REF. M C A B 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. BOTTOM VIEW CL (A1) 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX (b) L 5 SECTION "C-C" C C e TERMINAL TIP FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN8182.2 September 16, 2005