Hybrid Kit - Evaluation Kit for Applications with HybridPACK™1 Modules

HybridPACK™
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with
HybridPACK™1 Module
Application Note
V2.5, 2012-03-30
System Engineering
Edition 2012-03-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Hybrid Kit for HybridPACK™1
Revision History: 2012-03-30, V2.5
Previous Revision: V2.4
Page
Subjects (major changes since last revision)
18
added the information for Kemet Capacitor
39
Figure 37 updated
31
Figure 25 updated
Information on Pin-Fin Version added
Trademarks of Infineon Technologies AG
A-GOLD™, BlueMoon™, COMNEON™, CONVERGATE™, COSIC™, C166™, CROSSAVE™, CanPAK™,
CIPOS™, CoolMOS™, CoolSET™, CONVERPATH™, CORECONTROL™, DAVE™, DUALFALC™, DUSLIC™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, E-GOLD™, EiceDRIVER™,
EUPEC™, ELIC™, EPIC™, FALC™, FCOS™, FLEXISLIC™, GEMINAX™, GOLDMOS™, HITFET™,
HybridPACK™, INCA™, ISAC™, ISOFACE™, IsoPACK™, IWORX™, M-GOLD™, MIPAQ™, ModSTACK™,
MUSLIC™, my-d™, NovalithIC™, OCTALFALC™, OCTAT™, OmniTune™, OmniVia™, OptiMOS™,
OPTIVERSE™, ORIGA™, PROFET™, PRO-SIL™, PrimePACK™, QUADFALC™, RASIC™, ReverSave™,
SatRIC™, SCEPTRE™, SCOUT™, S-GOLD™, SensoNor™, SEROCCO™, SICOFI™, SIEGET™,
SINDRION™, SLIC™, SMARTi™, SmartLEWIS™, SMINT™, SOCRATES™, TEMPFET™, thinQ!™,
TrueNTRY™, TriCore™, TRENCHSTOP™, VINAX™, VINETIC™, VIONTIC™, WildPass™, X-GOLD™, XMM™,
X-PMU™, XPOSYS™, XWAY™.
Other Trademarks
AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is
licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of
Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION.
MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of
Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc.,
USA. muRata™ of MURATA MANUFACTURING CO. OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™
of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™
of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™,
PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™,
WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2009-10-19
Application Note
3
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
1.1
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
How to Order Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Support for Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Board (6ED100HP1-FA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cooling Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
14
14
14
14
16
20
3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
Evaluation Driver Board for the HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Dimensions of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Mode Power Supply (SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGBT Switch-off Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Protection and Clamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Layers of Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics, Layout and Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
25
26
27
28
28
28
29
30
30
32
33
34
35
35
36
36
40
42
46
4
4.1
4.2
4.3
4.4
4.4.1
4.4.1.1
4.4.1.2
4.5
Logic Board for Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Connector (X1-SIG1) Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connector to the Driver Board (K1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration of TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Configuration of TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting Serial/Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
50
53
53
53
53
54
54
55
Application Note
4
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Table of Contents
4.6
4.7
4.8
4.9
4.10
4.11
4.11.1
4.11.2
4.11.3
4.12
4.13
4.13.1
4.13.2
4.13.3
4.13.4
Phase Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Encoder Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hall Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR SSC Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Encoder Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR Hall Sensor Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Layers for the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics, Layout and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Note
5
55
55
55
56
56
56
57
58
58
58
59
59
67
68
72
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
The Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial number in the suitcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram of Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Dimensions of the Hybrid Kit for HybridPACK™1 - front view (all dimensions are in mm). . . . . . . 13
Dimensions of the Hybrid Kit for HybridPACK™1 - side view (all dimensions are in mm) . . . . . . . 13
HybridPACK™1 IGBT Six-Pack Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
HybridPACK™1 Pin Fin IGBT Six-Pack Module (backside). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC-Link Capacitor for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Technical drawing of the DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
JSPXZ6300ZAA0K - Kemet Capacitor Version2 - thermal optimized for a cooling plate . . . . . . . . 18
Kemet Capacitor Version1 - for face-surface cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Kemet Capacitor Version2 - thermal optimized for a cooling plate. . . . . . . . . . . . . . . . . . . . . . . . . 19
Example of Water Cooling Element for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Water Cooling System Technical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Example of Water Cooling Element for HybridPACK™1 Pin Fin . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Water Cooling System Technical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Driver Board Mounted on the Top of the HybridPACK™1 Module. . . . . . . . . . . . . . . . . . . . . . . . . 24
External Connector on the Driver Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Dimensions of the Driver Board (in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PCB Mounting Stand-offs of HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hybrid Kit for the HybridPACK™1 Evaluation Driver Board Block Diagram. . . . . . . . . . . . . . . . . . 27
Schematic of the Input Logic Block of the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Maximal Switch-off Current at Different DC-Link Voltages (Gate Resistance as a Parameter) . . . 29
Temperature of Gate Resistors vs. Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Desaturation Protection and Active Clamping Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
a) Short Circuit without Active Clamp (DC Voltage=71V, Voltage Overshoot=612V)
b) With Active Clamp Function (DC Voltage=280V, Voltage Overshoot=596V) 32
Fault Output of a Single Driver IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Fault Output During: a) Normal Operation b) Operation under Short Circuit . . . . . . . . . . . . . . . . . 33
Characteristics of the Temperature Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Characteristics of the DC Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Copper and Isolation for Layers of Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Schematics Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SMPS - Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fault Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Input Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
IGBT Driver - Bottom Transistor of Phase U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IGBT Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Voltage & Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Assembly Drawing of the Driver Board (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Assembly Drawing of the Driver Board (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Driver Board - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Driver Board - Layer-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Driver Board - Layer-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Driver Board - Layer-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Driver Board - Layer-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Driver Board - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Logic Board for Hybrid Kit for the HybridPACK™1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Application Note
6
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
List of Figures
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Block Diagram of the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Connector Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage and Wrong Polarity Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HW Boot Configuration of TC1767 DIP-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Boot Configuration Switch (SW1) and Serial/Parallel Interface Select Switch (SW2) . . . . . . .
GMR SSC Interface - Proposal Using TLE5012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Picture of Possible Physical Implementation of the GMR Sensor . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the Layers for the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematics Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Debug Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connector (external) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolver Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level Shifter for Adapting Logic Levels for Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level Shifter for Adapting Logic Levels for Resolver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller TC1767 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMR SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sense of the Logic Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connector to the Driver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing of the Logic Board (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Drawing of the Logic Board (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board - Layer-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board - Layer-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board - Layer-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board - Layer-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Board - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Note
7
50
51
53
54
55
57
57
58
59
60
60
61
61
62
62
63
63
64
65
66
66
66
67
67
68
69
69
70
70
71
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Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Key Data of DC-Link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Data of DC-Link Capacitor (Kemet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Data and Characteristic Values (Typical Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board . . . . . . . . . . . . . .
External Connector Pin Assignment Logic Board v1.3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Startup Modes for TC1767 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting Serial/Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials for Logic Board for Hybrid Kit for HybridPACK™1 . . . . . . . . . . . . . . . . . . . . . . . .
Application Note
8
16
18
25
46
51
54
54
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Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Introduction
1
Introduction
The Hybrid Kit for HybridPACK™1 shown in Figure 1 was developed to support customers during their first steps
in designing applications with HybridPACK™1 IGBT module. The following chapters provide a detailed description
of the main components and their functionality. This information is intended to enable the customers to copy,
modify and qualify the design for production, according to their specific requirements.
The boards Hybrid Kit for HybridPACK™1 Evaluation Driver Board (further refered as “Driver Board” ) and
Hybrid Kit for HybridPACK™1 Logic Board (further refered as “Logic Board”) provided by Infineon
Technologies are subjected to functional testing only.
Due to their purpose the system is not subject to the same procedures regarding Returned Material Analysis
(RMA), Process Change Notification (PCN) and Product Withdraw (PWD) as regular products.
See Legal Disclaimer and Warnings for further restrictions on Infineons warranty and liability.
The current implementation of the HybridKit (e.g. electrical schematics) is for reference only. It does not cover in
general all application specific requirements. For specific recommendations on how to implement design with
HybridPACK™ and EiceDRIVER™, please contact local sales partner. More information is available on
www.infineon.com/hybrid.
1.1
How to Order Hybrid Kit for HybridPACK™1
Hybrid Kit for HybridPACK™1 and Hybrid Kit for HybridPACK™1 Evaluation Driver Board (that can be
ordered separately) have Infineon Technologies SAP numbers and can be ordered via Infineon Sales Partners.
•
SAP ordering number for Hybrid Kit for HybridPACK™1 : SP000806996
Information can also be found at the Infineon Technologies web page: www.infineon.com
Figure 1
The Hybrid Kit for HybridPACK™1
Application Note
9
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Introduction
1.2
Support for Hybrid Kit for HybridPACK™1
The new Hybrid Kits for HybridPACK™1 are labeled with a serial number inside the suitcase. That provides
better support for you and a better issue tracking for us. If you need any support with the hardware or software just
let us known your issue and your serial number and we will try to help you as best we can. Where you can find the
serial number inside the suitcase is shown on Figure 2.
Figure 2
Serial number in the suitcase
Application Note
10
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Introduction
WARNING!
Please always take care of the dead-time settings of the
driver (to avoid short circuit conditions on the IGBT
module) and always have on mind that Hybrid Kit for
HybridPACKTM1 inverter has no breaking chopper or
similar hardware protection to absorb the energy
generated during the regenerative breaking of a motor.
In any case user shall ensure that voltage, current and
temperature are monitored properly, e.g. by software or
additional supporting hardware.
Application Note
11
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
2
Design Features
The Hybrid Kit for HybridPACK™1 is made up of two PCBs (Driver Board and Logic Board) mechanically and
electrically suitable to be used with an IGBT Module HybridPACK™1 (included), a DC-link capacitor and a cooler.
All these components build a complete main inverter for (H)EV applications up to 20kW.
IGBT driver
1ED020I12-FA
IGBT driver
1ED020I12-FA
Debug
Connector
IGBT driver
1ED020I12-FA
Logic Board
Watchdog
IGBT driver
1ED020I12-FA
IGBT driver
1ED020I12-FA
IGBT driver
1ED020I12-FA
Supply
Logic
DC-voltage
measurement
(isolated)
SMPS
c
IGBT temp
mesurement
o
t
r
e
C
PWM
o
n
Vdc meas.
n
TempIGBT
c
FAULT
Signals
o
t
e
C
Vdc, Temp
o
n
n
I, U, V current
Microcontroller
TC1767
EEPROM
measurement
CAN / RS232
Level
Shifter
Encoder / Sensor
r
RST
Supply
Resolver
interface
Resolver
6ED100HP1-FA Driver Board
Connector
IGBT module HybridPACK™1
Current U
CAN RS232
A/D IO Supply
Current V
Current W
Motor
3~
Figure 3
Encoder
Resolver
Sensor
Block Diagram of Hybrid Kit for HybridPACK™1
Figure 3 show the complete block diagram for the system and the following sections provide an overview of the
single components including main features, key data, pin assignments and mechanical dimensions.
2.1
Main Features
Complete main inverter for (H)EV applications up to 20kW.
•
•
•
•
Automotive qualified IGBT module HybridPACK™1
– 650V/400A IGBT & Diode chip set
Automotive qualified Driver IC 1ED020I12-FA
– Based on coreless transformer technology
– Up to 1200 V and 2A driving capability
– VCE sat - detection
TriCore™ family 32-bit microcontroller TC1767: member of the AUDO FUTURE product family designed for
automotive applications
Possibility of different motor position interfaces: encoder, resolver and GMR (Giant Magneto resistance))
Application Note
12
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
2.2
Dimensions
Figure 4 and Figure 5 shows the dimensions of a complete Hybrid Kit for HybridPACK™1.
Figure 4
Dimensions of the Hybrid Kit for HybridPACK™1 - front view (all dimensions are in mm)
Figure 5
Dimensions of the Hybrid Kit for HybridPACK™1 - side view (all dimensions are in mm)
Application Note
13
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
2.3
Key Components
For detailed technical information about the different components please refer to the different web pages on the
Infineon Internet.
2.3.1
Driver Board (6ED100HP1-FA)
The 6ED100HP1-FA is a six channel IGBT driver board, specially designed for the HybridPACK™1 IGBT module.
The main features and a detailed description of the board, including schematics and layout, can be found in
Chapter 3.
2.3.2
Logic Board
The Logic Board contains all necessary components for the control of the system. Furthermore it offers the
connections to the motor positioning system (encoder, resolver or GMR) and to the current measurement system.
For a detailed description of the board please refer to Chapter 3.
2.3.3
HybridPACK™1
(see Figure 6) is a power module designed for mild Hybrid Electrical Vehicle (HEV) applications with a maximum
supply voltage of 450 V and a power range up to 20kW. Designed for a junction operation temperature at 175°C,
the module accommodates a six-pack configuration of 3rd generation Trench-Field-Stop IGBT and matching
emitter controlled diodes and is rated up to 400A/650V. It is based on Infineon Technologies leading
TRENCHSTOP™ IGBT Technology, which offers lowest conduction and switching losses.
HybridPACK™1 is a baseplate module and can be screwed directly to a water- or air-cooled heat sink. For a
compact inverter design the driver stage PCB can easily be soldered on top of the module. All power connections
are realized with screw terminals.
Figure 6
HybridPACK™1 IGBT Six-Pack Module
Application Note
14
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
HybridPACK™1 is also available with a Pin - Fin baseplate for direct water cooling. As the thermal resistance is
lower the module can be used for a higher power ranges (40kW). All pins and power terminals as well as the rest
of the package is the same. Therefore it is necessary to have only a different heat sink design. For detailed
technical information of the module refer to the datasheet and to the application note mounting instructions.
Figure 7
HybridPACK™1 Pin Fin IGBT Six-Pack Module (backside)
Application Note
15
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
2.3.4
DC-Link Capacitor
The power electronic capacitor B25655J4307K from the company Epcos AG (see Figure 8) is strongly
recommended (included). Table 1 shows the main features of the capacitor. For dimensions of the DC-Link
Capacitor have a look on Figure 9. Please refer to the Epcos datasheet for further details.
Figure 8
DC-Link Capacitor for HybridPACK™1
Table 1
Key Data of DC-Link Capacitor
Characteristics
Maximum ratings
Test Data
CR
300 µF ±10%
Vs
600 V
VTT
675V DC, 10 s
VR
450 V DC
î
1.2 kA
Rins ·C
≥ 10000 s
WR
30 Ws
Is
4.8 kA
tan δ (50 Hz) ≤ 8 · 10-4
Imax
80 A
(dV/dt)max
4 V/µs
Lself
25 nH
(dV/dt)s
16 V/µs
-4
tan δ0
2 · 10
Rs
0.8 mΩ
Climatic Category
0/110/21(IEC 68-1/2)
Design Data
Tmin
- 40 °C
Dimensions l × w × h 140 × 72 × 50 mm tLD
Tmax
+ 110 °C
Approx. weight
750 g
Impregnation
Resin Filled
Max. Rel. Humidity ≤ 95%
Tstg
Mean Life Expentancy
- 45 … +110°C Terminals
9 mm
Values after Test Ca, IEC 68-2
Creepage distance
(21 days, 40°C, 93% rel. humidity)
≤ 5%
9 mm
Plastic Case
-4
Δtanδ
≤ 4 ·10
Rins ·C
≥ 3000s
Application Note
300fit
Flat Copper
Clearance
ΔC/C
αFQ
15000h
16
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
Figure 9
Technical drawing of the DC-Link Capacitor
Application Note
17
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
There are also other capacitors available on the market which fit mechanicaly to the HybridPACK™1. The different
capacitors are very often vary in mechanical, thermal and electrical parameters which needs to be validated for
the dedicated application. The following example is a capacitor JSPXZ6300ZAA0K from Kemet Electronics, which
allows different mechanical design of the cooler. Please refer to the Kemet Electronics datasheet for further
details.
The power electronic capacitor JSPXZ6300ZAA0K from KEMET Electronics is a polypropylene
300µF/450V/105°C DC-Link capacitor with a low-inductive 8nH terminal. The plastic case is filled with resin for
longterm humidity protection. Version-2 (see picture) is designed for optimized usage of the cooling plate surface.
Version 1 would also fit to the Hybrid Kit (current capability needs to be evaluated for the dedicated application).
Table 2
Key Data of DC-Link Capacitor (Kemet)
Electrical Performance
Cnom
300 µF ±10%
@RT ±5°C,f=1kHz
URated
450 V DC
@105°C
Upeak
650 V
for 10s
Imax_rms
80 A
@10kHz;Tcase<105°C
Ipeak
100 A
@450VDC, 2sec.
ESL
8 nH
ESR
1 mΩ
@1kHz
DF @1kHz
0,01%
Dissipation Factor
DF @100Hz
0,001%
Dissipation Factor
Climatic Category
40/105/56(IEC 60068-1)
Design Data
Mean Life Expentancy
Tmin
- 40 °C
Dimensions l × w × h 140 × 42 × 40mm Lexp
Tmax
+ 105 °C
Approx. weight
350 g
Max. Rel. Humidity ≤ 60%
Impregnation
Resin Filled
Tstorage
Terminals
Flat Copper
0… +105°C
15000h
αFQ
300fit
Plastic Case
Test performance
UT-T
600V DC
@25°C, 10s, Voltage test between terminals
UT-C
3000VAC
@50Hz, 1min., Voltage test between terminals to case
Figure 10
JSPXZ6300ZAA0K - Kemet Capacitor Version2 - thermal optimized for a cooling plate
Application Note
18
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
Figure 11
Kemet Capacitor Version1 - for face-surface cooling
Figure 12
Kemet Capacitor Version2 - thermal optimized for a cooling plate
Application Note
19
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
2.3.5
Cooling Element
For applications requiring higher power or higher operation temperature a usage of cooling element is
recommended. Figure 13 shows the low cost water cooling system that is included in the Hybrid Kit for
HybridPACK™1 which is screwed directly to HybridPACK™1 - Figure 14 shows the technical drawings of it. A
heat sink for air cooling is also a possible solution, but it will be larger than this water heat sink.
Figure 13
Example of Water Cooling Element for HybridPACK™1
For a proper connection to a rubber hose a tailpiece should be used. A possible tailpiece could be the 0931 10 13
from Legris, for more detailed information please refer to the website of Legris Inc.
Application Note
20
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
Figure 14
Water Cooling System Technical Drawings
Application Note
21
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
The heat sink for the pin fin baseplate is more complex then the one for a standard baseplate. It is necessary to
have a grove for a seal as well as the notch for the pin fin structure. For a optimal coolant flow through the heat
sink it is recommended to follow the design from the application note mounting instructions for HybridPACK™1
Pin Fin.
Figure 15
Example of Water Cooling Element for HybridPACK™1 Pin Fin
A seal is for the given grove already available it has the order number YA-231109-JD. The seal is available with
and without knobs which avoid a loosely behavior during mounting (falling out of the grove during turning).
For the Hybrid Kit 1 with the HybridPACK™1 Pin Fin the cooler was modificated as there was not enough space
left, so the inlet and outlet are not optimal.
Application Note
22
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Design Features
Figure 16
Water Cooling System Technical Drawings
Application Note
23
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
3
Evaluation Driver Board for the HybridPACK™1
Figure 17
Driver Board Mounted on the Top of the HybridPACK™1 Module
3.1
Main Features
The Hybrid Kit for HybridPACK™1 Evaluation Driver Board offers the following features:
•
•
•
•
•
•
•
•
•
Six channel IGBT driver
Electrically and mechanically suitable for 600 V IGBT Module HybridPACK™1
Includes DC/DC power supply
Isolated voltage measurement
Short circuit protection with toff < 6 µs
Under Voltage Lockout of IGBT driver IC
Positive logic with 5 V CMOS level for PWM and Fault signals
One fault signal for each driver (LED signaling) and their combination for each leg
Design according to IEC-60664-1
Application Note
24
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
3.2
Key Data
All values given in the Table 3 (bellow) are typical values, measured at TA = 25 °C
Table 3
Key Data and Characteristic Values (Typical Values)
Parameter
Value
Unit
VSUPPLY – Voltage Supply
+[8..18]
V
VPWM – PWM Signals for Top and Bottom IGBT (Active High)
0 / +5
V
VFAULT – /FAULT Detection Output (Active Low)
0 / +5
V
IFAULT – Max. /FAULT Detection Output Load Current
10
mA
VRST – /RST Input (Active Low)
0 / +5
V
ISUPPLY – Supply Current Consumption (Idle Mode) (VSUPPLY=12V)
260
mA
VOUT – Drive Voltage Level
15/-8
V
IG – Maximum Peak Output Current
±10
A
30
W
20
kHz
tPDELAY – Propagation Delay Time
200
ns
tPDISTO – Input to Output Propagation Distortion
15
ns
tMININ – Minimum Pulse Suppression for Turn-on and Turn-off2)
30
ns
VDESAT – Desaturation Reference Level
9
V
dmax – Maximum Duty Cycle
100
%
600
V
PDC/DC – Maximum DC/DC Output Power of SMPS unit
fS – Maximum PWM Signal Frequency
1)
VCES – Maximum Collector – Emitter Voltage on IGBT
3)
TOP – Operating Temperature (Design Target)
-40…+125 °C
TSTO – Storage Temperature (Design Target)
VIORM – Maximum Repetitive Insulation Voltage
-40…+125 °C
4)
(1ED020I12-FA Driver IC)
1420
VPEAK
VISODRIVER – Maximum Insulation Test Voltage (1ED020I12-FA Driver IC)
4500
Vrms
VISOBOARD – Maximum Insulation Test Voltage (Evaluation Board)
2500
Vrms
5)
1)
2)
3)
4)
5)
The max. switching frequency for the HybridPACK™1module should be calculated separately. Limiting factors are: max.
DC/DC output power of 4.6W per channel and max. PCB board temperature measured around gate resistors of 75°C for
used FR4 material. For detailed information see Chapter 3.5.3
Minimum value tMININ given in 1ED020I12-FA IGBT driver datasheet
Maximum ambient temperature strictly depends on load and cooling conditions
1ED020I12-FA datasheet - complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01.Basic Insulation
1ED020I12-FA datasheet - complies with UL 1577
3.3
External Connector Pin Assignment
Figure 18 shows the pin assignment for the external connector (K1) on the Driver Board. The connector is a
MMS-112-01-L-DV from Samtec, proper matching parts are the TW series for PCB connection or the TCMD series
for cable connection. It includes all necessary signals to get the board into operation, that is, supply, control and
monitoring.
Application Note
25
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
1 2V
1 2V
K1
G ND_DIG
G ND_A NA1
V DC
FLT Wn
FLT V n
FLT Un
FLT n
1
3
5
7
9
11
13
15
17
19
21
23
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
GND_DIG
GND_DIG V ANA5 0
+5.0 V
T EM P_ IGB T
RST _ INn
P WM WT
P WM WB
P WM VT
P WM VB
P WM UT
P WM UB
M MS -1 1 2-0 1 -L -DV
Figure 18
External Connector on the Driver Board
Pins 1 to 6 provide the power supply. The Driver Board must be supplied with an external regulated DC power
supply. The input voltage must be kept between 8 V and 18 V and the current consumption will depend on different
factors (Logic Board, PWM frequency, etc.). Pins 7-8 provide 5 V analogue power supply which can be used to
supply different devices in case of using the Hybrid Kit for HybridPACK™1 as driver board in an inverter such as
current measurement, ADC or the motor interface.
To pins 9, 10, 15 and 19 are connected monitoring signals: DC-link voltage measurement and temperature of the
three different phases inside of the IGBT module.
Pins 12, 13, 14, 16, 17, 18, 20, 21, 22 and 23 contain the logic signals for controlling the 6 drivers on the board,
that are the PWM signals, Fault detection and Reset signal.
3.4
Mechanical Dimensions of the Driver Board
The Driver Board has placed components on both sides of the PCB. The maximum height of the Parts and the
dimensions of the PCB is shown in Figure 19
Figure 19
Dimensions of the Driver Board (in mm)
Application Note
26
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
The Driver Boards should be fastened by self taping screws and soldered to the auxiliary connectors on top of the
IGBT module. The contact joints (solder points) between PCB and module auxiliary contacts should be
mechanically relieved in order to disburden the solder connection as far as possible. Relieve of the contact points
is carried out by mounting the PCB directly onto the module at the ten mounting stand-offs (see Figure 20) using
self-tapping screws (thread forming with 2.5mm diameter) or similar assembly material. The screws should be
mounted in the sequence showed in Figure 20.
Figure 20
PCB Mounting Stand-offs of HybridPACK™1
3.5
Operation of the Driver Board
Figure 21 shows the block structure of the Driver Board. The following chapter describes these blocks in detail.
15V/-8V
15V/-8V
DC LINK
VOLTAGE
MEASUREMENT
SMPS
IGBT
Driver
UT
15V/-8V
15V/-8V (x3)
IGBT
Driver
VT
IGBT
Driver
WT
5V
5V
5V
5V
IGBT
Driver
VB
IGBT
Driver
WB
5V
5V
RESET
FAULT U
LOGIC
FAULT V
FAULT W
5V
RESET
FAULT
FAULT U
FAULT V
FAULT W
IGBT
Driver
UB
IGBT
MODUL
TEMP
12V
Connector
INPUT
LOGIC
(PWM)
IGBT MODUL TEMPERATURE
DC LINK VOLTAGE MEASUREMENT
Figure 21
Hybrid Kit for the HybridPACK™1 Evaluation Driver Board Block Diagram
Application Note
27
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
3.5.1
Switching Mode Power Supply (SMPS)
The Driver Board has an integrated DC/DC converter which generates the required secondary isolated
unsymmetrical supply voltage of +15/-8V. Top and bottom driver voltages are independently generated by using
one unipolar input voltage of 12 V.
An additional supply voltage (5V) is generated and forwarded to the external connector (K1) so it can be used to
supply external components in the system (current measurement, motor interface, etc.)
For circuit details please refer to Figure 33.
3.5.2
Input Logic
The Driver Board is a dedicated system for a six-pack HybridPACK™1 IGBT configuration - therefore it is
necessary to use 6 separated PWM signals. The schematics on Figure 22 shows the input logic block with +5V
positive logic. The block is made up of RC filters for each PWM signal in order to reduce noise. Additionally these
signals are pulled-down in order to avoid unwanted switching-on of the drivers. Please have in mind that the Hybrid
Kit for HybridPACK™1 does not provide dead time automatically (meaning that hardware alone provides no dead
time) - it is up to the user to generate the PWM signals with the correct dead time (by means of software).
R88
PWM _WT
100 R
C85
1 00p F/100 V /COG
R89
1 5k
GND_DIG1
R90
G ND_DIG1
PWM _WB
100 R
C86
1 00p F/100 V /COG
R91
1 5k
GND_DIG1
R92
G ND_DIG1
P WM WT
PWM _VT
100 R
C87
1 00p F/100 V /COG
R93
1 5k
P WM WB
P WM VT
GND_DIG1
R94
P WM VB
G ND_DIG1
P WM UT
PWM _VB
100 R
C88
1 00p F/100 V /COG
P WM UB
R95
1 5k
GND_DIG1
R96
G ND_DIG1
PWM _UT
100 R
C89
1 00p F/100 V /COG
R97
1 5k
GND_DIG1
R98
G ND_DIG1
PWM _UB
100 R
C90
1 00p F/100 V /COG
R99
1 5k
GND_DIG1
G ND_DIG1
Figure 22
Schematic of the Input Logic Block of the Driver Board
3.5.3
IGBT Switch-off Behavior
Due to the stray inductances of the system a voltage overshoots occur during the switching-off the IGBT. Such
overshoots are added to the DC-link voltage, so that the maximum blocking voltage of the IGBT or capacitor might
be exceeded causing damages in both components (DC link capacitor and IGBT module). In order to avoid such
risks an active clamping circuit is used (see Chapter 3.5.6).
Without such protection methods the maximum current would be limited by the DC-link voltage and the voltage
overshoots at switching-off. The voltage overshoots can be minimized by increasing the gate resistor, which will
reduce the di/dt value. Figure 23 shows the maximal switch-off current at different DC-link voltages for a different
values of the gate resistor. These results were obtained with the DC-link capacitor described in Chapter 2.3.4.
Application Note
28
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
900
800
700
600
Ic (A)
500
Ic nominal
400
300
200
100
0
0
50
100
150
Rgoff=2.2Ohm
200
250
Rgoff=3.8Ohm
300
350
Rgoff=5.6Ohm
Icnom
400
450
DC-Link voltage (V)
Figure 23
Maximal Switch-off Current at Different DC-Link Voltages (Gate Resistance as a Parameter)
3.5.4
Maximum Switching Frequency
The IGBT switching frequency is limited by the available power and by PCB temperature. According to theory the
power losses generated in the gate resistors are a function of a gate charge, voltage step at the driver output and
switching frequency. The energy is dissipated mainly through the PCB and raises the temperature around the gate
resistors. When the available power of the DC/DC converter is not exceeded, the limiting factor for the switching
frequency is the absolute maximum temperature for the FR4 material. The allowed operation temperature is
105 °C.
Generally the power losses generated in the gate resistors can be calculated according to Equation (1):
P dis = P RGext + P RGint = ΔV out ⋅ f S ⋅ Q ge
(1)
In Equation (1) f S represents the switching frequency, ΔV out represents the voltage step at the driver output,
P dis is the dissipated power, Q ge is the IGBT gate charge value corresponding to +15V/-8V switching operation.
This value can be approximately calculated from the datasheet value by multiplying it by 0.77, that is
Q ge = 3.31μC . Therefore the maximum frequency limited by the available power will be:
f Smax = 4.6 W ⁄ ( 23V ⋅ 3.31μC ) = 60.4 kHz
Figure 24 shows experimentally determined board temperature dependencies with switching frequency (at 25 °C
ambient temperature). From Figure 24 it can be concluded that the maximum switching frequency is limited by
PCB temperature.
Application Note
29
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
75,0
gate resistor temperature (°C)
70,0
65,0
60,0
55,0
50,0
45,0
40,0
35,0
1,0
5,0
9,0
13,0
17,0
21,0
25,0
29,0
33,0
37,0
41,0
45,0
49,0
switching frequency (kHz)
Figure 24
Temperature of Gate Resistors vs. Switching Frequency
3.5.5
Booster
Two transistors per driver IC are used to amplify the driver ICs signals. On this way the driving IGBTs are supplied
with sufficient current even if driver ICs alone can’t deliver enough current. One NPN transistor is used for
switching the IGBT on and another PNP transistor for switching the IGBT off.
The transistors are dimensioned to have enough peak current to drive HybridPACK™1 modules. Peak current can
be calculated like in Equation (2):
ΔV out
I peak = ----------------------------------------------------R Gint + R Gext + R Driver
(2)
For circuit details please refer to Figure 37.
3.5.6
Short Circuit Protection and Clamp Function
The short circuit protection of the Driver Board basically relies on the detection of a voltage level higher as 9 V on
the DESAT pin of the 1ED020I12-FA driver IC and the implemented active clamp function. Thanks to this operation
mode, the collector-emitter overvoltage, which is a result of the stray inductance and the collector current slope,
is limited. Depending on the stray inductance, the current and the DC voltage the voltage overshoot during turn
off changes. Figure 25 shows the parts of the circuit needed for the desaturation function and the active clamping
function.
Application Note
30
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
D5_ UB
D4_ UB
ZLL S 10 0 0
ZLL S 10 0 0
G ND
VP
C13 _ UB
1 00 p F/1 0 0V /CO G
G ND
R28 _ UB
D6_ UB
COL
1K
C17 _ UB
1 00 n /50 V/X 7 R
U4
17
16
/RS T
/FLT
V CC2
DES AT
13
14
15
18
12
11
19
20
IN+
IN-
O UT
CLA MP
T LS E T
RDY
V CC1
G ND1
G ND1
G ND1
G ND1
G ND2
V EE 2
V EE 2
V EE 2
V EE 2
6
3
7
8
5
4
US1 M
G ND
C15 _ UB
4 u7 /2 5V /X7 R
C16 _ UB
4 u7 /2 5V /X7 R
D9_ UB
ZLL S 10 0 0
T 1_ UB 2 1 R0 / S M P-1 R0 0 -1.0
1 R0 / S M P-1 R0 0 -1.0
1
0 R2 2 / S MP -R2 2 0-1 .0
R33 _ UB
R32 _ UB
R38 _ UB
R31 _ UB
3
4 7R_ 08 0 5_ T K1 0 0_ 1 %_ 0.1 2 5W
ZXT N20 1 0Z
T 2_ UB 3
R30 _ UB
R36 _ UB
R37 _ UB
1
1 R0 / S M P-1 R0 0 -1.0
1 R0 / S M P-1 R0 0 -1.0
2
G ND
0 R2 2 / S MP -R2 2 0-1 .0
1
2
9
10
COL
D3_ UB
S MCJ4 4 0A
D1_ UB
E S1 D
G
ZXT P 20 1 2Z
C23 _ UB
1 00 n /50 V/X 7 R
C20 _ UB
4 u7 /2 5V /X7 R
C21 _ UB
4 u7 /2 5V /X7 R
G ND
1 ED0 20 I12 -FA
G ND
VN
Figure 25
Desaturation Protection and Active Clamping Diodes
In the case of a short circuit the collector-emitter saturation voltage will rise and the driver detects the short circuit
occurrence - to protect the IGBT it has to be turned off. As a consequence of IGBT turn-off process there will occur
an voltage overshoot due to the stray inductance of the module and the DC-link. This voltage overshoot has to be
lower than the maximum IGBT blocking voltage. Therefore the Driver Board has an active clamping function
whereby the clamping will increase the voltage for the booster and also increase the voltage directly on the gate.
The typical turn-off waveform under short circuit condition and room temperature of a HybridPACK™1 module
without any additional protective functions is shown in Figure 26 a). Typical waveform under short circuit condition
with active clamp function at room temperature is shown in Figure 26 b). As it can be seen, the voltage overshoot
without active clamping at a DC voltage of 71 V is close to the maximum IGBT blocking voltage of HybridPACK™1
(650V), which could damage the devices. With active clamping the voltage overshoot can be reduced and the DC
voltage increased without damaging the IGBT module (at 280 V DC voltage can be observed voltage overshoot
of approximately 596 V, Figure 26 b). In design are implemented 440 V clamping diodes. The level of the
clamping voltage must be adjusted depending on the application.
Application Note
31
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Figure 26
a) Short Circuit without Active Clamp (DC Voltage=71V, Voltage Overshoot=612V)
b) With Active Clamp Function (DC Voltage=280V, Voltage Overshoot=596V)
3.5.7
Fault Output
When a short circuit occurs the voltage VCE is detected by the desaturation protection of the 1ED020I12-FA and
the IGBT is switched off. The fault is reported to the primary side of the driver as long as there is no reset signal
applied to the driver. The fault signal (/FLT) is active low - the schematic of design implemented in Driver Board
can be seen on Figure 27.
Application Note
32
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
V DIG 50
+5.0 V
R29 _ UB
4 k7
17
16
RST n
C14 _ UB
4 70 p F/5 0 V/X 7R
IN+
IN-
13
14
V DIG 50
+5.0 V
15
18
R34 _ UB
4 k7
12
11
19
20
FLT n
V DIG 50
+5.0 V
U4
/RS T
/FLT
IN+
INRDY
V CC1
G ND1
G ND1
G ND1
G ND1
V CC2
DES AT
O UT
CLA MP
T LS E T
G ND2
V EE 2
V EE 2
V EE 2
V EE 2
6
3
7
8
5
4
1
2
9
10
1 ED0 20 I12 FTA
C22 _ UB
1 00 n/50 V/X 7 R
G ND_DIG1
G ND_DIG1
Figure 27
Fault Output of a Single Driver IC
Short circuit occurs
Ready signal
Fault signal
UGE
a)
Figure 28
b)
Fault Output During: a) Normal Operation b) Operation under Short Circuit
The fault signal (/FLT) will be in low state if a short circuit occurs until /RST signal is pulled down.
On the Driver Board each of the drivers has its own fault signal (FAULT_UTn, FAULT_UBn, FAULT_VTn,
FAULT_VBn, FAULT_WTn, FAULT_WBn). As it can be seen in Figure 35, a LED will warn in the case of a
DESAT-FAULT condition at a IGBT. The fault signals are connected to a logic circuit and the output of this are a
combined fault and one fault for each phase, which is forwarded to the external connector (K1).
3.5.8
Temperature Measurement
The IGBT module HybridPACK™1 includes one integrated NTC (Negative Temperature Coefficient) sensor which
simplify the thermal measurements in inverters significantly.
The NTC is located on the same ceramic substrate together with the IGBT and diode chips for the middle phase.
The module is filled with silicon gel for isolation purpose and under normal operation conditions the requirements
for isolation voltages are met. The NTC isolation capability is tested with 2.5kV AC in final test for 1 minute for
100% of module production.
Application Note
33
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
The NTC is connected to the main connector K1 (pin 10) by means of the circuit showed in Figure 39. Figure 29
shows the relationship between IGBT module base plate temperature of the three phases and output voltage of
IGBT module temperature block (TEMP_IGBT, K1.10)
4,5
Temp_IGBT (V)
4,0
3,5
3,0
2,5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
module temperature (°C)
Figure 29
Characteristics of the Temperature Measurements
Note: This temperature measurement is not suitable for the short circuit or short term overload detection and
should be used only for the module protection against long term overload or malfunction of the cooling system.
3.5.9
DC Voltage Measurement
On the Hybrid Kit for HybridPACK™1 the voltage at the DC link is measured by means of a isolation amplifier
which offers the necessary galvanic isolation (see Figure 39).
The output of this circuit is connected to the external connector (Vdc, K1.9). Figure 30 shows the relationship
between DC link voltage and Vdc output signal.
Application Note
34
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
4500
4000
y = 7,2171x + 1294,4
3500
VDC (mV)
3000
2500
2000
1500
1000
500
0
0
50
100
150
200
250
300
350
400
DC-Link Voltage (V)
Figure 30
Characteristics of the DC Voltage Measurement
3.6
Switching Losses
Switching losses can be different comparing to the values given in the HybridPACK™1 IGBT module datasheet.
Main reason for this discrepancy is that switching voltages used on the Driver Board (+15V for turn-on and -8V for
turn-off) differ from HybridPACK™1 characterisation switching voltages (+15V/-15V).
Turn-on losses are expected to be close to the values of the datasheet of HybridPACK™1, but as mentioned, this
will be different for the turn-off losses. In general the turn-off losses depend on the stray inductances of the DClink and increase linear with the DC-link voltage. In the case of the Driver Board the turn-off losses do not increase
linearly because of the fact that the active clamping feature increases the turn-off losses due to decrease of the
di/dt.
3.7
Definition of Layers of Driver Board
The Driver Board was made keeping the following rules for the copper thickness and the space between different
layers shown in Figure 31.
1
Copper
1
2
1: 35 µm
2
2: 35 µm
3
3: 35 µm
4
4: 35 µm
5
5: 35 µm
6
Figure 31
6: 35 µm
3
4
5
Isolation
1-2: 0.5 mm
2-3: 0.5 mm
3-4: 0.5 mm
4-5: 0.5 mm
5-6: 0.5 mm
6
Copper and Isolation for Layers of Driver Board
Application Note
35
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
3.8
Schematics, Layout and Bill of Material
To meet the individual customer requirements and to make the Driver Board for the HybridPACK™1 module as a
platform for development or modifications, all necessary technical data like schematics, layout and components
are included in this chapter.
The current implementation of the HybridKit (e.g. electrical schematics) is for reference only. It does not cover in
general all application specific requirements. For specific recommendations on how to implement design with
HybridPACK™ and EiceDRIVER™, please contact local sales partner. More information is available on
www.infineon.com/hybrid.
3.8.1
Schematics
IGB T _DRIV E R_UT
IN+
INRST n
FLT n
S MP S
1 2V in
VP
COL
G
G ND
VN
V P1 5 _UTV N8_ UT
+15 .0 V -8 .0V
IGB T _M ODULE
COL UT
G UT
G NDUT
G ND_UT
IGB T _DRIV E R
IGB T _DRIV E R_UB
IN+
INRST n
FLT n
S MP S
VP
COL
G
G ND
VN
V P1 5 _UB V N8_ UB
+15 .0 V
-8 .0 V
G UB
G NDUB
G ND_UB
IGB T _DRIV E R
IGB T _DRIV E R_VT
CONNE CTO R
INP UT_L OG IC
P WM _UT
P WM _UB
P WM _V T
P WM _V B
P WM _WT
P WM _WB
P WM UT
P WM UB
P WM VT
P WM VB
P WM WT
P WM WB
VP
COL
G
G ND
VN
V P1 5 _V T V N8_ VT
+15 .0 V
-8 .0 V
COL VT
G VT
G NDVT
G ND_V T
IGB T _DRIV E R
IGB T _DRIV E R_VB
INP UT_L OG IC
IN+
INRST n
FLT n
RST_INn
FLTn
FLTWn
FLTVn
FLTUn
VDC
G ND_DIG1
TEMP_IGBT
12V
G ND_DIG
P WM UT
P WM UB
P WM VT
P WM VB
P WM WT
P WM WB
IN+
INRST n
FLT n
VP
COL
G
G ND
VN
V P1 5 _V B V N8_ VB
+15 .0 V
-8 .0 V
G VB
G NDVB
G ND_V B
IGB T _DRIV E R
CONNE CTO R
IGB T _DRIV E R_WT
IN+
INRST n
FLT n
VP
COL
G
G ND
VN
V P1 5 _WT V N8_ WT
+15 .0 V
-8 .0 V
COL WT
G WT
G NDWT
G ND_WT
IGB T _DRIV E R
FAUL T_ L OGIC
V P1 5 _WB V N8_ WB
+15 .0 V
-8 .0 V
G WB
G NDWB
G ND_WB
IGB T _DRIV E R
RST _ INn
FAUL T_ Un
FAUL T_ Vn
FAUL T_ Wn
FAUL T_ n
VP
COL
G
G ND
VN
FAUL T_ UT n
FAUL T_ VT n
FAULT_ WT n
POWER_VCC
IN+
INRST n
FLT n
Temp0
Temp1
IGB T _DRIV E R_WB
IGB T _M ODULE
FAUL T_UB n
FAUL T_ VB n
FAULT_ WB n
M EA SURE
RST n
T em p0
T em p1
FAUL T_ L OGIC
T EM P_IGB T
V DC
P OWER_ VCC
M EA SURE
Figure 32
Schematics Block Overview
Application Note
36
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
V P1 5_UT
+15 .0V
D4
D5
E S1 A
1k6
1k6
C895
4 u7 /25V /X7R
G ND_UT
V N8 _UT
-8.0 V
R145
R144
R143
1k6
UT_PS
C893
4 u7 /25V /X7R
C89 4
1SM B59 29B T3 G
2 2u /35 V /T4 91 V z=1 5V
+
V P1 5_WT
+15 .0V
D6
WT _ PS
E S1 A
D7
4u7/25V/X7R
1k6
R147
L2
D31
+
S L23 _3 0 V_ 2A_ SM B
G ND_DIG1
C93 6
2 2u /16 V /X7 R
G ND_DIG1
G ND_DIG1
E S1 A
C92 5
2 2u /16 V /X7 R
+
C92 6
G ND_DIG1
1k6
R162
1k6
G ND_DIG1
1k6
R167
R166
D21
+
4u7/25V/X7R4u7/25V/X7R
C912 G ND_WB
V N8_ WB
-8.0 V
V P15 _UB
+15 .0V
C91 5
C91 8
1 SM B5 9 29 B T3 G
2 2u /35 V /T4 9 1 Vz= 15V
+
V DIG 50
+5.0 V
1 206
R_S MK -R00 0
1k6
R157
1k6
1k
R156
R155
1k6
R161
R160
D19
E S1A
T ra fo _p l an ar_sm ps_ 8W_HP 1_ o pt
R17 0
C909
D18
R171
o pt
R168
C914
10n/50V/X7R
R163
4k75
UB_ PS
16
1k6
G ND_DIG1
V P1 5 _WB
+15 .0V
C91 0
1 SM B5 929B T3G
2 2u /35 V /T4 9 1 Vz= 1 5V
R174
680R/PRC221 1W TK100 1%
6
2
D17
E S1 A
10
15
G ND_DIG1
C907 G ND_V B
V N8 _VB
-8.0 V
D16
+
G ND_DIG1
L _4 7 u_ 1A_ E PCOS _ B8 2472 P
G ND_DIG1
Figure 33
WB _PS
6
9
L M3 478 MM
R15 9
5 9K
11K / 1 % / 100 p pm
C921
2 20 n F/C08 0 5F2 24K 5RA C
T LE 8 366 EV
G ND_DIG1
IPD1 44 N06 NG
R173
680R/PRC221 1W TK100 1%
B UO
G ND
4
5
Q5
100n/50V/X7R
S YNC
FB
B DS
DR
Isen
R19 7
1
6
7 R5_ 08 0 5_ T K1 00 _ 1% _0.1 25 W
3
1
G ND_DIG1
C924
220nF/220nF/C0805F224K5RAC
1
VS
EN
COM P
FA/S D
COM P
FB
A GND
P GND
R16 9
C923
8
7
3
GND_EP
GND_DIG1
IC1
G ND_DIG1
R16 5
1K5 / 1 % / 100 p pm
9
G ND_DIG1
C917
100nF/50V/C0805F104K5RACTU
R175
C922
22K / 1% / 100ppm
22nF/50V/X7R
L1
G ND_DIG1
C919
470pF/10V/X7R
G ND_DIG1
G ND_DIG1
14
5
V in
R164
0R025
2
B ZV 5 5-C18
L _47 u_ 1 A_E PCOS _ B8 2 47 2 P
C916
1uF/50V/C1206F105K5RACTU
C913
1uF/50V/C1206F105K5RACTU
UNDER_ VO L _DET E CT ION
8
7
2
3
4
5
C90 8
10n/50 V /X7 R
R158
19K6
T2
B SS 13 8 N
1
D32
100uF/12.5V/A700X107M12RATE015
1 2V _ PROT
P OWER_ UP
C911
22n/50V/X7R
3
UNDER_ VO L _DET E CT ION
IC2
G ND_DIG1
R154 8 0K 6
C904
C90 6
1 SM B5 929B T3G
2 2u /35 V /T4 9 1 Vz= 1 5V
+
1 SM B5 9 29B T3 G
2
2
4u7/25V/X7R4u7/25V/X7R
1k6
R152
D15
E S1 A
C90 5
1 00 n F/100 V /X7 R
R15 3
1 0K
V P15 _V B
+15 .0V
D13
V B_ PS
4u7/25V/X7R 4u7/25V/X7R
8
13
D14
C90 1G ND_V T
V N8_ VT
-8.0 V
4u7/25V/X7R4u7/25V/X7R
G ND_DIG1
1k6
1k6
1
D12
E S1 A
C89 9
C900
1 SM B5 9 29 B T3 G
2 2u/35 V /T4 9 1 V z= 15V
+
1k6
G ND_DIG1
+
D10
E S1A
4
7
R151
+
D9
G ND_WT
C89 8
V N8 _WT
-8.0V
V P1 5 _V T
+15.0V
V T_ PS
R150
G ND_DIG1
R146
1k6
G ND_DIG1
D11
1 SM B3 0AT 3 G
12
3
C903
47uF_25V_SVPD/ASVPD
1 2V _ PROT
B ZV 5 5-C13
R14 9
10K
C902
D8
4u7F/50V/X7R/C1210C475K5RACTU
Q4
IPD9 0P 0 3P 4L-04
C89 6
4u7 /25 V /X7 R
C89 7
1 SM B5 929 B T3G
2 2u /35 V /T49 1 V z= 1 5V
+
11
R148
T F1
1k6
1 2V i n
G ND_UB
C92 0 G ND_UB
V N8_ UB
-8.0 V
V DIG 50
0 R / SM K-R0 00
+5.0 V
R17 2
L 3 805
V ANA5 0
+5.0 V
MURAT A _B LM 21P 2 21S N
C927
1 00 n/5 0V/X 7 R
GND_DIG1
R17 6 o pt
+
C928
2 2u /16 V /X7 R
G ND_A NA1
SMPS - Power Supply
1 2V
1 2V
K1
G ND_DIG
G ND_A NA1
V DC
FLT Wn
FLT V n
FLT Un
FLT n
1
3
5
7
9
11
13
15
17
19
21
23
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
GND_DIG
GND_DIG V ANA5 0
+5.0 V
T EM P_ IGB T
RST _ INn
P WM WT
P WM WB
P WM VT
P WM VB
P WM UT
P WM UB
M MS -1 1 2-0 1 -L -DV
Figure 34
External Connector
Application Note
37
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
V DIG50
+5.0 V
RST n
R17 7
1 5K_ 060 3_ T K1 00 _ 1%_ 0.0 63 W
RST _INn
V DIG50
+5.0 V
R17 8
1 K_ 0 60 3 _T K1 00_ 1 %_ 0.0 6 3W
6
FAUL T_ UB n
R17 9
4 K7 _ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
1
4
C92 9
1 0n F_0 4 02 _ X7 R_5 0 V_ CER_o p t D22 A
BAS 16ST 6B
V DIG50
+5.0 V
2
10k
1
10k
FAUL T_ UT n
1
2
T 6A
6
3
BCR10P N
D22 B
BAS 16S
6
FAUL T_ Un
10k
5
R18 0
1 5K_ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
R18 1
10k
5
GND_DIG1
D30 A
B AS16 S
BCR10 PN
1 K_ 0 60 3 _T K1 00_ 1 %_ 0.0 6 3W
V DIG 50
+5.0 V
C93 0
1 0n F_0 4 02 _ X7 R_5 0 V_ CER_o p t
GND_DIG1
GND_DIG1
R18 2
1 5K _ 06 0 3_ T K1 00 _ 1%_ 0.063 W
VDIG50
+5.0 V
R18 3
R18 5
1 5K _ 06 0 3_ T K1 00 _ 1% _ 0.0 63 W
FAUL T_ Vn
1
10k
D23 A
B AS16 S
3
B CR10 PN
2
6
R18 6
R18 4
4 K7 _ 06 0 3_ T K1 00 _ 1% _ 0.0 63 W
10k
T 7A
10k
1
10k
FAUL T_ VT n
1 K_ 0 60 3 _T K1 0 0_1 %_ 0 .06 3W
R18 7
1 5K _ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
BCR10P N
C93 2
1 0n F_0 4 02_ X7 R_50 V_ CER_o p t
2
VDIG50
+5.0 V
5
3
T 7B
5
6
C93 1
1 0n F_0 4 02_ X7 R_50 V_ CER_oD22
pt C
B AS16 S
GND_DIG1
4
1 K_ 0 60 3 _T K1 0 0_1 %_ 0 .06 3W
VDIG50
+5.0 V
4
FAUL T_ VB n
D30 B
BAS 16S
G ND_DIG1
GND_DIG1
VDIG50
+5.0 V
R18 8
FAUL T_ Wn
3
2
T 8A
10k
4
10k
B CR10 PN
4
D23 C
B AS16 S
FAUL T_ WT n
1
10k
1 K_ 0 60 3 _T K1 0 0_1 %_ 0 .06 3W
10k
2
10k
10k
3
10k
2
10k
3
<PACKAGE>
4
T 5B
B CR18 3 S
10k
5
10k
6
<PA CKAGE >
VDIG50
+5.0 V
VDIG50
+5.0 V
T 5A
BCR18 3 S
T 4B
BCR18 3 S
10k
5
<PACKAGE>
4
1
4
1
T 3B
BCR18 3 S
10k
V DIG 50
+5.0 V
VDIG50
+5.0 V
T 4A
BCR18 3 S
1
VDIG 50
+5.0 V
VDIG 50
+5.0 V
T 3A
BCR183S
6
R18 9
4 K7 _06 0 3_ T K1 00 _ 1%_ 0.0 63
10k
5
10k
6
R19 3
2 20 R_0 6 03 _ TK 10 0 _1 %_0 .06 3 W
R194
2 20 R_0 6 03 _ TK10 0 _1 % _0 .06 3W
R19 5
2 20 R_0 6 03 _ TK 10 0 _1 %_0 .06 3 W
R19 6
2 20 R_0 6 03 _ TK 10 0 _1 %_0 .06 3 W
D24
D26
D27
D28
D29
GND_DIG1
GND_DIG1
Figure 35
GND_DIG1
G ND_DIG1
D30 C
BAS 16 S
G ND_DIG1
FAUL T_ n
4 K7_ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
<PACK AGE>
R25
R19 2
2 20 R_06 03 _ TK10 0 _1 % _0 .06 3 W 2 20 R_0 6 03 _ TK100 _1 % _0 .06 3 W
D25
R19 8
10k
3
<PA CKAGE >
<PACKA GE>
BCR10P N
V DIG 50
+5.0 V
GND_DIG1
10k
2
C93 4
1 0n F_0 4 02_ X7 R_50 V_ CER_o p t
3
GND_DIG1
R19 1
3
R19 0
1 5K _ 06 0 3_ T K1 00 _ 1%_ 0.0 63 W
T 8B
5
6
C93 3
1 0n F_0 4 02 _ X7 R_5 0 V_ CER_o p tD23 B
BAS16 S
2
1 K_ 0 60 3 _T K1 00_ 1 %_ 0.0 6 3W
4
VDIG 50
+5.0 V
5
FAUL T_ WBn
GND_DIG1
GND_DIG1
Fault Logic
R88
PWM _WT
100 R
C85
1 00p F/100 V /COG
R89
1 5k
GND_DIG1
R90
G ND_DIG1
PWM _WB
100 R
C86
1 00p F/100 V /COG
R91
1 5k
GND_DIG1
R92
G ND_DIG1
P WM WT
PWM _VT
100 R
C87
1 00p F/100 V /COG
R93
1 5k
P WM WB
P WM VT
GND_DIG1
R94
P WM VB
G ND_DIG1
P WM UT
PWM _VB
100 R
C88
1 00p F/100 V /COG
P WM UB
R95
1 5k
GND_DIG1
R96
G ND_DIG1
PWM _UT
100 R
C89
1 00p F/100 V /COG
R97
1 5k
GND_DIG1
R98
G ND_DIG1
PWM _UB
100 R
C90
1 00p F/100 V /COG
R99
1 5k
GND_DIG1
G ND_DIG1
Figure 36
Input Logic
Application Note
38
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
D5_ UB
D4_ UB
ZLL S 10 0 0
ZLL S 10 0 0
G ND
VP
C13 _ UB
1 00 p F/1 0 0V /CO G
G ND
D6_ UB
R28 _ UB
COL
1K
G ND
C15 _ UB
4 u7 /2 5V /X7 R
V DIG 50
+5.0 V
R29 _ UB
4 k7
17
16
RST n
C14 _ UB
4 70 p F/5 0 V/X 7R
13
IN+
IN-
14
V DIG 50
+5.0 V
15
18
R34 _UB
4 k7
12
11
19
20
FLT n
V DIG 50
+5.0 V
C17 _ UB
1 00 n /50 V/X 7 R
V CC2
DES AT
IN+
O UT
CLA MP
IN-
T LS E T
RDY
V CC1
G ND1
G ND1
G ND1
G ND1
G ND2
V EE 2
V EE 2
V EE 2
V EE 2
C16 _ UB
4 u7 /2 5V /X7 R
D9_ UB
ZLL S 10 0 0
T 1_ UB 2 1 R0 / S M P-1 R0 0 -1 .0
1 R0 / S M P-1 R0 0 -1 .0
1
0 R2 2 / S MP -R2 2 0-1 .0
R33 _ UB
R32 _ UB
R38 _ UB
R31 _ UB
3
4 7R_ 08 0 5_ T K1 0 0_ 1 %_ 0.1 2 5W
ZXT N20 1 0Z
T 2_ UB 3
R30 _ UB
R36 _ UB
R37 _ UB
1
1 R0 / S M P-1 R0 0 -1 .0
1 R0 / S M P-1 R0 0 -1 .0
2
G ND
0 R2 2 / S MP -R2 2 0-1 .0
U4
/RS T
/FLT
6
3
7
8
5
4
COL
D3_ UB
S MCJ4 4 0A
US1 M
D1_ UB
E S1 D
G
ZXT P 20 1 2Z
C23 _ UB
1 00 n /50 V/X 7 R
1
2
9
10
C21 _ UB
4 u7 /2 5V /X7 R
G ND
C20 _ UB
4 u7 /2 5V /X7 R
1 ED0 20 I12 -FA
G ND
C22 _ UB
1 00 n /50 V/X 7 R
VN
G ND_DIG1 G ND_DIG1
Figure 37
IGBT Driver - Bottom Transistor of Phase U
P OWER_ VCC
COL WT
COL VT
G WT
COL UT
G VT
C79
1 0n /5 0V /X7 R
GUT
R82
1 0K
G NDWT
C80
1 0n/5 0V /X7 R
R83
1 0K
C81
1 0n /5 0V /X7 R
G NDVT
R84
1 0K
GNDUT
1
P
Q 3A
P ACKA G E = 1
Q 3B
P ACKA G E = 1
Q3C
P ACKA G E = 1
6
25
22
7
9
11
8
10
12
P ha se_ W 3
P ha se_ V 4
P ha se_ U 5
24
N
13
15
17
14
16
18
T em p1
23
2
19
T em p0
N
FS4 0 0R0 6A 1 E3 _o p tFS4 0 0R0 6A 1 E3 _o p tFS4 0 0R0 6A 1 E3 _o p t
G WB
G VB
C82
1 0n /5 0V /X7 R
G NDWB
Figure 38
R85
1 0K
G UB
C83
1 0n/5 0V /X7 R
R86
1 0K
G NDVB
C84
1 0n /5 0V /X7 R
R87
1 0K
G NDUB
IGBT Module
Application Note
39
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
R4
V ANA5 0
+5.0 V
R2
5 90 K
R3
5 90 K
HV_ VB_ VD
R5
5 90 K
R6
5 90 K
R7
5 90 K
V B_ 1 3
5
4
V-
G ND_A NA1
G ND_A NA1
Vdd1
8
Vdd2
6
O UT +IN+
O UT - IN-
2
R9
3 9R
G ND_V B
3
R8
3 K9
V B_ 1 2
R10
1 58 R
V B_ 1 1
C5
1 0n /5 0V /X7 R
GND1
R12 9 o pt
6
R12
2 K / 0.1 %
R11
C6
1
50
1 0K / 0 .1 % p /50 V/C0 G
7
IC3
A CP L -7 8 2T
500V->199mV
C3
1 00 n /50 V/X 7 R
GND_V B
4
3
G ND_ANA1
5
8
V+
R15
2 K / 0.1 %
2
IN-B
OUT B
IN+B
7
T EM P_ IGB T
C2
1 00 n /50 V/X7 R
G ND_A NA1
IC4
IN-A
OUT A
IN+A
1
+5V V B
+5V
1
V ANA5 0
+5.0 V
C11 3
1 0n /5 0V /X7 R
V DC
R1
5 90 K
3 30 p F/5 0 V/COG
GND2
C1
P OWER_ VCC
4 K0 2 / 0 .1%
G ND_V B
AD8 5 52 A RZ
G ND_A NA1
G ND_V B
G ND_A NA1
V ANA5 0
+5.0 V
R13 6 0 R
R13 7
1 0K 5 /1 %
T em p1
C11 6
C89 1
1 00 n /50 V/X 7 R
1
I
Q
INH
G ND
G ND
1 u/2 5 V/X7R
4
2
5
C93 5
4 u7 _ X7 R_1 6 V_ CE R/C1 20 6 F4 7 5K 4 RA
T LE 4 29 6 -2 G V5 0
G ND_V B
C121
10n/50V/X7R
3
T em p0
+5V V B
+5V
IC6
R130
10K5/1%
V P1 5 _V B
+15 .0 V
C12 2
1 0n /5 0V /X7 R
G ND_A NA1
G ND_V B
Figure 39
DC Voltage & Temperature Measurement
3.8.2
Assembly Drawing
Application Note
40
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Figure 40
Assembly Drawing of the Driver Board (Top)
Application Note
41
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Figure 41
Assembly Drawing of the Driver Board (Bottom)
For detail information use the zoom function of your PDF viewer to zoom into the drawings on Figure 40 and
Figure 41.
3.8.3
Layout
Layout of the Driver Board is shown on Figure 42 (Top Layer), on Figure 43 (Layer-2), on Figure 44 (Layer-3),
on Figure 45 (Layer-4), on Figure 46 (Layer-5) and on Figure 47 (Bottom Layer).
Application Note
42
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Figure 42
Driver Board - Top Layer
Figure 43
Driver Board - Layer-2
Application Note
43
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Figure 44
Driver Board - Layer-3
Figure 45
Driver Board - Layer-4
Application Note
44
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Figure 46
Driver Board - Layer-5
Figure 47
Driver Board - Bottom Layer
Application Note
45
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
3.8.4
Bill of Materials
Table 4
Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board
Reference
Value / Device
Package
C1
330pF/50V/COG
C0603
C116
1u/25V/X7R
C0805
C13_WT,C13_WB,C13_VT,C13_VB,C13_UT, 100pF/100V/COG
C13_UB,C85,C86,C87,C88,C89,C90
C0603
C14_WT,C14_WB,C14_VT,C14_VB,C14_UT, 470pF/50V/X7R
C14_UB
C0603
C15_WT,C15_WB,C15_VT,C15_VB,C15_UT, 4u7/25V/X7R
C15_UB,C16_WT,C16_WB,C16_VT,C16_VB,
C16_UT,C16_UB,C20_WT,C20_WB,C20_VT,
C20_VB,C20_UT,C20_UB,C21_WT,C21_WB,
C21_VT,C21_VB,C21_UT,C21_UB,C893,C89
5,C896,C898,C899,C901,C904,C907,C909,C
912,C915,C920
C1206
C17_WT,C17_WB,C17_VT,C17_VB,C17_UT, 100n/50V/X7R
C17_UB,C22_WT,C22_WB,C22_VT,C22_VB,
C22_UT,C22_UB,C23_WT,C23_WB,C23_VT,
C23_VB,C23_UT,C23_UB,C927
C0805
C19_WT,C19_WB,C19_VT,C19_VB,C19_UT, 33pF/100V/COG
C19_UB
C0603
C2,C3,C891,C926
100n/50V/X7R
C0603
C5,C79,C80,C81,C82,C83,C84,C113,C121,C
122,C908,C914
10n/50V/X7R
C0603
C6
150p/50V/C0G
C0603
C894,C897,C900,C906,C910,C918
22u/35V/T491
C7343
C902
4u7/50V/X7R
C1210
C903
47uF/25V/ASVPD
C0810
C905
100nF/100V/X7R
C1206
C911,C922
22n/50V/X7R
C0402
C913,C916
1uF/50V/C1206F105K5
C1206
C917
100nF/50V/C0805F104K5
C0805
C919
470pF/10V/X7R
C0402
C921,C924
220nF/C0805F224K5RAC
C0805
C923
100uF/12.5V/A700X107M1 C7343
2RATE015
C925,C928,C936
22u/16V/X7R
C1210
C929,C930,C931,C932,C933,C934
10n/16V/X7R/optional
C0402
C935
4u7/16V/X7R/C1206F475
K4RA
C1206
Application Note
46
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Table 4
Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board (cont’d)
Reference
Value / Device
Package
D1_WT,D1_WB,D1_VT,D1_VB,D1_UT,D1_U
B
ES1D
DO214AC
D10_WT,D10_WB,D10_VT,D10_VB,D10_UT, MM3Z9V1T1G/optional
D10_UB
SOD323
D11
1SMB30AT3G
SMB
D22,D23,D30
BAS16S
SOT363
D24,D25,D26,D27,D28,D29
SML-512UWT86
D0603
D3_WT,D3_WB,D3_VT,D3_VB,D3_UT,D3_U
B
SMCJ440A
SMC
D31
SL23/30V/2A
DO214AA/SMB
D32
BZV55/C18
SOD80C
D4_WT,D4_WB,D4_VT,D4_VB,D4_UT,D4_U
B,
ZLLS1000
SOT23
D4,D6,D8,D10,D11,D14,D16,D18
ES1A
DO214AC
D5,D7,D10,D14,D15,D17,D19
1SMB5929BT3G
DO214AA/SMB
D6_WT,D6_WB,D6_VT,D6_VB,D6_UT,D6_U
B
GF1M
DO214AC/SMA
D8
BZV55-C13
SOD80C
IC1
TLE8366EV
SO-8-27
IC2
LM3478MM
MSOP-8
IC3
ACPL-782T
DIP-8
IC4
AD8552ARZ
SO-8
IC6
TLE4296GV50
SCT595
K1
MMS-112-01-L-DV
24POL
L1,L2
47uH/1A/B82472P
SMD 7,5x7,5
L3
MURATA_BLM21P221SN
L0805
Q3
FS400R06A1E3
HybridPACK™1
Q4
IPD90P03P4L-04
TO252
Q5
IPD144N06NG
TO252
R1,R2,R3,R5,R6,R7
590K/1%
R1206
R10
158R/1%
R0603
R11
10K 0.1%
R0603
R12,R15
2K /0.1%
R0603
R129
Optional
R0603
R130,R137
10K5/1%
R0603
R136
0R/1%
R0603
R140
226K/1%
R0603
R142
47K/1%
R0603
Application Note
47
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Table 4
Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board (cont’d)
Reference
Value / Device
Package
R143,R144,R145,R146,R147,R148,R150,R15 1K6/1%
1,R152,R156,R157,R160,R161,R162,R166,R
167,R168
R1206
R154
80K6/1%
R0603
R155
1K/1%
R1206
R158
19K6/1%
R0603
R159
59K/1%
R0603
R163
4.75 kΩ/1%
R0603
R164
0R025/1%
R2010
R165
1K5/1%
R0402
R169
11kΩ/1%
R0402
R170,R172
SMK-R000
SMK (1206)
R171,R176
optional
R1210
R173,R174
1K2/PRC221/1W/1%
R2512
R175
22K/1%
R0402
R177,R180,R182,R185,R187,R190,R89,R91,
R93,R95,R97,R99
15k/1%
R0603
R178,R181,R183,R186,R188,R191
1K/1%
R0603
R179,R184,R189,R198
4K7/1%
R0603
R197
7R5/1%/0.125W
R0805
R25,R192,R193,R194,R195,R196
220R/1%
R0603
R28_WT,R28_WB,R28_VT,R28_VB,R28_UT, 1K/1%
R28_UB
R0603
R29_WT,R29_WB,R29_VT,R29_VB,R29_UT, 4K7/1%
R29_UB
R0603
R30_WT,R30_WB,R30_VT,R30_VB,R30_UT, 1R0 / SMP-1R00-1.0
R30_UB,R32_WT,R32_WB,R32_VT,R32_VB,
R32_UT,R32_UB,R33_WT,R33_WB,R33_VT,
R33_VB,R33_UT,R33_UB,R36_WT,R36_WB,
R36_VT,R36_VB,R36_UT,R36_UB
SMP (2010)
R31_WT,R31_WB,R31_VT,R31_VB,R31_UT, 47R/1%
R31_UB
R0805
R35_WT,R35_WB,R35_VT,R35_VB,R35_UT, 0R/1%
R35_UB
R0805
R35_WT,R35_WB,R35_VT,R35_VB,R35_UT, OR/1%
R35_UB
R0805
R37_WT,R37_WB,R37_VT,R37_VB,R37_UT, 0R22 / SMP-R220-1.0
R37_UB,R38_WT,R38_WB,R38_VT,R38_VB,
R38_UT,R38_UB
SMP (2010)
R4
4K02 / 0.1%
R0603
R8
3K9/1%
R0603
Application Note
48
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Evaluation Driver Board for the HybridPACK™1
Table 4
Bill of Materials for Hybrid Kit for the HybridPACK™1 Evaluation Driver Board (cont’d)
Reference
Value / Device
Package
R82,R83,R84,R85,R86,R87,R182
10K/1%
R0603
R88,R90,R92,R94,R96,R98
100R/1%
R0603
R9
39R/1%
R0603
T1_WT,T1_WB,T1_VT,T1_VB,T1_UT,T1_UB
ZXTN2010Z
SOT89
T2
BSS138N
SOT23
T2_WT,T2_WB,T2_VT,T2_VB,T2_UT,T2_UB
ZXTP2012Z
SOT89
T3,T4,T5
BCR183S
SOT363
T6,T7,T8
BCR10PN
SOT363
TF1
Planar Transformer v2.1
TH 16pin
U16
MAX6457UKD3A-T
SOT23-5
U18,U33,U34
AD8552ARZ
SO-8
U4,U5,U6,U7,U8,U9
1ED020I12-FA
PG-DSO-20
Application Note
49
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4
Logic Board for Hybrid Kit for HybridPACK™1
Figure 48
Logic Board for Hybrid Kit for the HybridPACK™1
Logic Board (Figure 48) contains all the components for the control of the Hybrid Kit for the HybridPACK™1.
Furthermore it offers the interface for all the other elements which build a complete inverter system: motor interface
(encoder, resolver, sensors), current sense interface, communication (CAN and RS232) and additional analogue
(x3) and digital (x4) inputs/outputs. Figure 49 shows the block structure of the Logic Board and the following
chapters describe these blocks in detail.
Debug
Connector
Logic Board
Watchdog
c
o
e
n
n
Vdc meas.
TempIGBT
c
t
r
Supply
PWM
C
o
FAULT
Signals
o
e
n
n
Microcontroller
TC1767
C
Vdc, Temp
o
EEPROM
I, U, V current
measurement
CAN / RS232
Level
Shifter
t
Encoder / Sensor
r
RST
Supply
Resolver
interface
Resolver
6ED100HP1-FA Driver Board
Connector
IGBT module HybridPACK™1
Current U
CAN RS232
A/D IO Supply
Current V
Current W
Motor
3~
Encoder
Resolver
Sensor
Figure 49
Block Diagram of the Logic Board
4.1
External Connector (X1-SIG1) Pin Assignment
Connector X1-SIG1 (Harwin M80-5125042P) provides the interface to all the external systems: motor (encoder,
resolver, sensors), current sense, communication (CAN and RS232) and extra analogue and digital
inputs/outputs. Figure 50 shows the pin assignment of the connector X1-SIG1. For the description of the signals
see Table 5.
Application Note
50
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
S2
2
1
ADC_IN1
S6
4
3
ADC_IN2
S3
6
5
ADC_IN3
S1
8
7
StatorTemp
10
9
R1
R2
VANA50
GND_ANA1
I_U
I_V
I_W
12
11
14
13
16
15
18
17
20
19
22
21
iGMR_CSn+
24
23
iGMR_DATA-
26
25
28
27
30
29
iGMR_DATA+
iGMR_CLKiGMR_CLK+
CAN1_L
CAN1_H
ASC_TX
ASC_RX
GND_DIG1
+12V
+12V
GND_DIG1
GND_DIG1
GND_ANA1
DIO_1
DIO_2
DIO_3
VDIG50
GND_DIG1
iGMR_CSniGMR_Ren_DE+
Motor Interface
(Resolver)
Motor Interface
(Encoder)
Motor Interface
(Hall Sensor)
Motor Interface
(iGMR Sensor)
Phase Current
Sense
Communication
General Purpose
Ana/Dig IN/OUT
iGMR_Ren_DEPosA/iGMR_A+
PosA/iGMR_A-
Power Supply
Not Connected
PosB/iGMR_B+
32
31
34
33
36
35
PosZ/iGMR_Z+
38
37
PosZ/iGMR_Z-
40
39
PosU/iGMR_U
42
41
PosV/iGMR_V
44
43
PosW/iGMR_W
46
45
48
47
50
49
PosB/iGMR_B-
GND_DIG1
VDIG50
Harwin M80-5125042P
Figure 50
External Connector Pin Assignment
Table 5
External Connector Pin Assignment Logic Board v1.3b
Pin Number
Pin Name
Type
Description
1
ADC_IN1
I/O
General Purpose Analog I/O
2
S2
Input
Resolver Sine (high)
3
ADC_IN2
I/O
General Purpose Analog I/O
4
S6
Input
Resolver Sine (low)
5
ADC_IN3
I/O
General Purpose Analog I/O
6
S3
Input
Resolver Cosine (high)
7
StatorTemp
Input
Motor Temperature Measurement
8
S1
Input
Resolver Cosine (low)
9
GND_ANA1
Supply Analog Ground
10
R1
Output Resolver Excitation (high)
11
DIO1
I/O
12
R2
Output Resolver Excitation (low)
Application Note
General Purpose Digital I/O
51
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Table 5
External Connector Pin Assignment Logic Board v1.3b (cont’d)
Pin Number
Pin Name
Type
Description
13
DIO2
I/O
General Purpose Digital I/O
14
VANA50
Supply +5.0V Analog Power Supply
15
DIO3
I/O
16
GND_ANA1
Supply Analog Ground
17
VDIG50
Supply +5.0V Digital Power Supply
18
I_U
Input
19
GND_DIG1
Supply Digital Ground
20
I_V
Input
21
iGMR_CSn-
Output iGMR Chip Select (differential signal)
22
I_W
Input
23
iGMR_REn_DE+
Output iGMR Read Enable (differential signal)
24
iGMR_CSn+
Output iGMR Chip Select (differential signal)
25
iGMR_REn_DE-
Output iGMR Read Enable (differential signal)
26
iGMR_DATA-
I/O
iGMR Data (differential signal)
27
PosA/iGMR_A+
Input
Encoder Phase A (differential signal)
28
iGMR_DATA+
I/O
iGMR Data (differential signal)
29
PosA/iGMR_A-
Input
Encoder Phase A (differential signal)
30
iGMR_CLK-
Output iGMR SSC Clock (differential signal)
31
PosB/iGMR_B+
Input
32
iGMR_CLK+
Output iGMR SSC Clock (differential signal)
33
PosB/iGMR_B-
Input
Encoder Phase B (differential signal)
34
CAN1_L
I/O
Low line I/O CAN Signal
35
PosZ/iGMR_Z+
Input
Encoder Phase Z - index (differential signal)
36
CAN1_H
I/O
High line I/O CAN Signal
37
PosZ/iGMR_Z-
Input
Encoder Phase Z - index (differential signal)
38
ASC_TX
Output RS-232 Transmitter Output
39
PosU/iGMR_U
Input
Hall Sensor Phase U
40
ASC_RX
Input
RS-232 Receiver Input
41
PosV/iGMR_V
Input
Hall Sensor Phase V
42
GND_DIG1
Supply Digital Ground
43
PosW/iGMR_W
Input
44
KL_30_IN
Supply +12.0V Power Supply
45
GND_DIG1
Supply Digital Ground
46
KL_30_IN
Supply +12.0V Power Supply
47
VDIG50
Supply +5.0V Digital Power Supply
48
GND_DIG1
Supply Digital Ground
49
NC
NC
50
GND_DIG1
Supply Digital Ground
Application Note
General Purpose Digital I/O
Current Sense Phase U
Current Sense Phase V
Current Sense Phase W
Encoder Phase B (differential signal)
Hall Sensor Phase W
Not Connected
52
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4.2
Connector to the Driver Board (K1)
See Chapter 3.3.
4.3
Power Supply
The complete system (Driver Board and Logic Board) must to be supplied with and external regulated DC power
supply connected to connector X1-SIG1 (+12.0V on pins 44 and 46 and GND_DIG1 on pins 48 and 50) on the
Logic Board. The input voltage should be kept between 8 V and 18 V and the current consumption will vary
depending on different factors, i.e. PWM frequency.
This supply line will be forwarded to the Driver Board through the connector K1. On both boards a protection circuit
will avoid damages in case of overvoltage or wrong polarity (see Figure 51).
K L_ 30_ IN
+12 .0V
Q4
IPD90P 0 3P 4 L-0 4
K L_ 3 0
+12 .0 V
D2
D3
1 SM B3 0 AT 3
B ZV 5 5/C13
R128
1 0K
G ND_DIG1
Figure 51
GND_DIG 1
Overvoltage and Wrong Polarity Protection Circuit
The supply block (see Figure 58) generates all the necessaries supplies for the components on the logic board
(5V, 3.3 V and 1.5 V). Furthermore the 5 V (analogue and digital) are connected to the external connector (X1SIG1) for supplying external systems (i.e. current sensor).
The Logic Board use the Infineon Technologies TLE7368E Micro Controller Power Supply IC. After applying the
main power supply the IC13 will be switched-on. As soon as 5 V/3.3V/1.5V power supplies reached their correct
values the signal POWERrstn (RO_1 and RO_2 outputs of IC12) will be activated waking-up the microcontroller.
For further details of the TLE7368E please refer to the datasheet.
4.4
Microcontroller
The microcontroller block (uC block in overview given in Figure 57) contains following elements:
•
TC1767 (Figure 67) is a 32-Bit Microcontroller member of the Infineon Technologies AUDO FUTURE product
family designed for automotive applications. TriCoreTM CPU providing high-end microcontroller performance
combined with sophisticated DSP capabilities (please refer to datasheet for further details)
•
Input filter (see Figure 66): passive filters for digital and analogue signals and voltage dividers for voltage level
adaptation
•
EEPROM (Figure 68): 256kB Electrically-Erasable Programmable Read-Only Memory optimized for use in
automotive applications where low-power and low-voltage operations are essential (for more details refer to
AT25256A-10TQ-2.7 datasheet). The communication with the microcontroller is done through SSC0 interface
(high-speed synchronous serial interface, SPI-compatible)
•
RS-232 & CAN Transceivers (see Figure 65)
4.4.1
Configuration of TC1767
The TC1767 can be configured with the respect to the different boot modes and with the respect to the different
interfaces (serial/parallel) to the resolver and iGMR position sensors.
Application Note
53
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Boot Configuration of TC1767
P0
.7
P0
.6
P0
.5
P0
.4
P0
.3
P0
.2
P0
.1
P0
.0
4.4.1.1
ON
LOW
HIGH
Figure 52
1
2
3
4
5
6
7
8
HW Boot Configuration of TC1767 DIP-Switch
The picture above (Figure 52) shows the definition of the boot HW configuration switch (DIP-Switch SW1 on
Figure 67). The meaning of the switches will be described in the following Table 6.
The ON position of the switch is equal to a logical LOW at the dedicated pin.
Table 6
User Startup Modes for TC1767
CFG[7...0]
Type of Boot TC1767
11)
11XXX11X2)
Internal Start from Flash
OFF OFF X3)
010XX110
Bootstrap Loader Mode, Generic Bootloader at ON
CAN pins
10101110
Bootstrap Loader Mode, ASC Bootloader
OFF ON
OFF ON
OFF OFF OFF ON
10100110
Alternate Boot Mode, ASC Bootloader on fail
OFF ON
OFF ON
ON
1011X11X
Alternate Boot Mode, Generic Bootloader at
CAN pins on fail
OFF ON
OFF OFF X
All others
Reserved; don’t use this combination
2
3
OFF ON
4
5
6
7
8
X
X
OFF OFF X
X
X
OFF OFF ON
OFF OFF ON
OFF OFF X
1) 1 to 8 are the DIP-Switch numbers
2) The shadowed line indicates the default settings.
3) ’x’ represents the don’t care state.
4.4.1.2
Selecting Serial/Parallel Interface
DIP-4 switch (SW2 on Figure 65) is used to select serial/parallel interface for the communication with resolver or
iGMR position sensor - please refer to Table 7.
Table 7
SW2[4...1]
2)
Selecting Serial/Parallel Interface
41)
Inetrface to the Resolver/iGMR
3)
3
2
1
0000
iGMR enabled (SPI and Incremental mode)
Resolver in Parallel Mode
OFF
OFF
OFF
OFF
1111
Resolver in Serial Mode
iGMR disabled
ON
ON
ON
ON
All others
Reserved; don’t use this combination
1) 1 to 4 are the DIP-Switch numbers
2) 0 is equal to open switch, “1” is equal to closed switch
3) ’x’ represents the don’t care state.
Application Note
54
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Figure 53
The Boot Configuration Switch (SW1) and Serial/Parallel Interface Select Switch (SW2)
4.5
Watchdog
The Logic Board contains a pin-selectable watchdog timer that supervises the microcontroller activity and
signalizes when the system is operating improperly. During normal operation, the microcontroller (GPTA39)
should repeatedly toggle the watchdog input (WDI, see Figure 61) before the selected watchdog time-out period
elapses to report that the system is processing code properly. If this does not occurs, the supervisor asserts a
watchdog output (WDO) which will reset the microcontroller via PORSTn (external power-on hardware reset).
The state of the three logic control pins (SET0, SET1 and SET2) determines watchdog timing characteristics (see
table in Figure 61). The jumper J1 allows disabling the watchdog functionality in a very easy way.
4.6
Phase Current Sensing
Phase current sensing signals should be connected to the Logic Board connector X1-SIG1 to the pins I_U, I_V
and I_W (Figure 66). The Logic Board is designed to work with current transducers (not provided with the Hybrid
Kit) with voltage output proportional to the current (usually deploying Hall effect - like LEM sensors). User can take
+5V (analog) available on the X1-SIG1 pins to supply current transducers. The exact type of current transducer
will depend on many parameters in application, but usually the most important is the motor current consumption.
Please notice that if you control 3-phase balanced synchronous system it is enough to measure just 2 phases,
since the 3rd phase current can be calculated as algebraic combination out of the 2 measured currents. The
microcontroller is able to convert synchronously two phase currents, it’s recommended to do an accurate current
measurement.
4.7
Temperature Sense
The Logic Board includes a temperature sensor (IC54, LM50-CIM3) which is located on the bottoside of the board.
With the sensor it is possible to measure the ambient temperature between Logic Board and Driver Board. For
schematics and output voltage values of the circuit see Figure 70. If you need any further information about the
device please refer to the data sheet.
4.8
Resolver Interface
The Logic Board includes a 12-Bit Resolver-to-digital converter (meaning A/D converter) which integrates an onboard programmable sinusoidal oscillator that provides sine wave excitation for resolvers (pins R1 and R2 on
connector X1-SIG1). For more details please refer to the data sheet of the component (AD2S1200YST) and the
schematics of the circuit see Figure 62. With resistors (R155, R156, R157, R158, R159 and R160) user can trim
the LMH6672 (dual op-amp) output voltage values (resolver excitation). On the Logic Board is given additional
possibility to trim the resolver excitation with potentiometers (R483, R484, R485 - not populated, user should
solder them if needed). Please refer to data sheet of used resolver to trim this values properly. The resolver
response should be connected between pins S1 and S3 (sine) and S2 and S6 (cosine) on the connector X1-SIG1.
Application Note
55
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4.9
Encoder Interface
If encoder is used as a sensor for the motor position/speed sensing the following pins on connector X1-SIG1
should be connected: the phase A should be connected between pins PosA/iGMR_A+ and PosA/iGMR_A-, the
phase B should be connected between pins PosB/iGMR_B+ and PosB/iGMR_B- and phase Z (index or zero
marker) should be connected between pins PosZ/iGMR_Z+ and PosZ/iGMR_Z- .
4.10
Hall Sensor Interface
If Hall sensor is used as a sensor for the motor position/speed sensing the following pins on connector X1-SIG1
should be connected: the phase U should be connected to pin PosU/iGMR_U, the phase V should be connected
to pin PosV/iGMR_V and phase W should be connected to pin PosW/iGMR_W .
4.11
GMR Interface
As mentioned on the beginning of the Chapter 4, the Logic Board supports GMR interface by means of a bidirectional SSC (SPI compatible), encoder (or incremental) and Hall sensor interface. It is explicitly recommended
to use Infineon Technologies TLE5012 GMR-based angular sensor for rotor position sensing. The TLE 5012 is a
360° angle sensor that detects the orientation of a magnetic field. This is achieved by measuring sine and cosine
angle components with monolithic integrated Giant Magneto Resistance. For more details about TLE5012 please
refer to the data sheets on Infineon Technologies internet pages.
Application Note
56
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4.11.1
GMR SSC Interface Mode
U1
3
5
R in1 +
Ro ut 1
R in1 -
R in2 +
Ro ut 2
R in2 -
11
R4
1k
0 60 3
U2
6
VDD SC K
CSQ
DATA
C LK
I FA
I FB
1
7
13
U3
2
3
VCC
4
2
5
8
1
5
3
D O+
D in
D O-
8
16
4
7
12
8
6
R in3 +
Ro ut 3
R in3 -
R in4 +
Ro ut 4
R in4 -
2
R1
10 0R
06 03
R2
10 0R
06 03
R9
R 10
R1 1
3k 3
06 03
3 k3
0 60 3
3k 3
06 03
1
6
7
X15
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
9
R3
10 0R
14
06 03
15
VCC
EN
EN_ n
GN D
DE
RE
R ou t
R6
R7
R8
3k 3
06 03
3 k3
0 60 3
3k 3
06 03
D S9 0C 03 2BTM
G ND
TL E5 01 2
G ND
H ea de r_ 7x2
4
R5
5 4R
DS9 2LV0 10 ATM
06 03
U4
12
8
3Y
3Z
4A
4Y
4Z
10
11
14
13
VCC
G
0 60 3
3A
6
5
C6
16
4
2Y
2Z
10p /2 5V/ X7R
15
2A
2
3
06 03
0 60 3
C5
10 0n/ 16 V/X7 R/EMK1 07 B710 4KA
06 03
C4
1 00n /1 6V/ X7R /EMK10 7B7 104 KA
0 60 3
C3
10 0n/ 16 V/X7 R/ EMK1 07 B710 4KA
1 206
C2
1 0u /1 0V/X7 R/ LMK31 6B7 10 6KL
06 03
C1
Figure 54
10 0n /1 6V/ X7R/ EMK10 7B71 04 KA
9
1Y
1Z
C7
7
1A
1 0p/ 25 V/X7 R
1
G
GN D
AM26 LS3 1C DR
GMR SSC Interface - Proposal Using TLE5012
The schematics of SSC interface on the Logic Board is shown on Figure 69. Signals on connector X1-SIG that
are used for SSC interface are: iGMR_CSn+/iGMR_CSn- (Chip Select, differential signals),
iGMR_REn_DE+/iGMR_REn_DE- (Read Enable, differential signals), iGMR_DATA+/iGMR_DATA- (Serial Data,
differential signals) and iGMR_CLK+/iGMR_CLK- (SSC Clock, differential signals) - all signals are listed in
Table 5. On Figure 54is presented the schematics of possible technical solution (implemented by Infineon
Technologies System Engineering) for usage of TLE5012. The PCB with TLE5012 and a few additional
components is mounted perpendicular to the electric motor shaft - just as shown on Figure 55.
Figure 55
Picture of Possible Physical Implementation of the GMR Sensor
Application Note
57
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4.11.2
GMR Encoder Interface Mode
Infineon Technologies iGMR sensor TLE5012 can be used with encoder interface as well. This working mode is
referred as IIF Interface mode in theTLE5012 data sheet. To avoid signal integrity and EMC problems, within
Hybrid Kit it is expected that the 2 phase signals (A and B) and zero (index) signal are provided differentially. On
the connector X1_SIG (Figure 50) encoder inputs are: PosA/iGMR_A+ and PosA/iGMR_A (phase A),
PosB/iGMR_B+ and PosB/iGMR_B (phase B) and PosZ/iGMR_Z and PosZ/iGMR_Z (phase Z - index) - please
refer to the Table 5. Please refer to the TLE5012 data sheet to get iGMR sensor running in incremental mode.
4.11.3
GMR Hall Sensor Interface Mode
TLE5012 supports Hall sensor interface mode as well (iGMR emulates Hall sensor mode). For this purpose to the
connector X1-SIG inputs PosU/iGMR_U (phase U), PosV/iGMR_V (phase V) and PosW/iGMR_W (phase W)
should be connected. Please notice (on Figure 66) that the pull-up resistors to 3.3 V (R491, R492 and R493) are
already provided on the Logic Board. For more details on Hall sensor mode please refer to the TLE5012 data
sheet.
4.12
Definition of Layers for the Logic Board
The Logic Board was made keeping the following rules for the copper thickness and the space between different
layers shown in Figure 56.
1
Copper
1
2
1: 35 µm
2
2: 35 µm
3
3: 35 µm
4
4: 35 µm
5
5: 35 µm
6
Figure 56
6: 35 µm
3
4
5
Isolation
1-2: 0.5 mm
2-3: 0.5 mm
3-4: 0.5 mm
4-5: 0.5 mm
5-6: 0.5 mm
6
Definition of the Layers for the Logic Board
Application Note
58
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4.13
Schematics, Layout and Bill of Materials
To meet the individual customer requirements and to make the Logic Board for the HybridPACK™1 module as a
platform for development or modifications, all necessary technical data like schematics, layout and components
for the Logic Board are included in this chapter.
4.13.1
Schematics
OCDS1
uC
T DO
T DI
T MS
T CK
T RSTn
B RKINn
B RKOUT n
T DO
T DI
T MS
T CK
T RS Tn
B RK INn
B RKOUT n
T DO
T DI
T MS
T CK
T RSTn
B RKINn
B RKOUT n
Rese tn
Rese tn
Rese tn
WAT CHDOG
DEBUG
WDO WDI
WDI
WAT CHDOG
S UPPL Y
POWERrstn
CONNE CTO R
P osA/iG MR_ A+
P osA/iG MR_ AP osB/iG MR_ B+
P osB/iG MR_ BP osZ/iG MR_ Z+
P osZ/iG MR_ Z-
SUP PL Y
P osA /iGMR_ A+
PosA /iG MR_ AP osB /iGMR_ B+
PosB /iG MR_ BP osZ/iG MR_ Z+
PosZ/iG MR_ Z-
P osA/iG MR_ A+
P osA/iG MR_ AP osB/iG MR_ B+
P osB/iG MR_ BP osZ/iG MR_ Z+
P osZ/iG MR_ Z-
P osU/iG MR_ U
P osU/iGMR_ U
P osU/iG MR_ U
P osV/iG MR_ V
P osV /iG MR_ V
P osV/iG MR_ V
P osW/i G MR_ W
PosW/i G MR_ W
P osW/i G MR_ W
CONNE CTO R_ Drive rBo a rd
L EV E L_ SHIFTER
P WM UT n
PWM UBn
P WM VT n
P WM VB n
P WM WT n
P WM WBn
i GM R
i GM R_DAT A+
i GM R_DAT A i GM R_CLK+
i GM R_CLKi GM R_CSn +
i GM R_CSn i GM R_REn _ DE +
i GM R_REn _ DE-
i GM R_DAT A +
i GM R_DAT A i GM R_CLK +
i GM R_CLK i GM R_CSn +
i GM R_CSn i GM R_REn _ DE+
i GM R_REn _ DEI_ U
I_ V
I_ W
I_ U
I_ V
I_ W
Reso l ve r
S1
S3
S2
S6
R1
R2
A
S1
B
S3
NM
S2
S6 A D2 S 12 0 0_ SA M PL En
R1 AD2 S 12 0 0_ RES ET n
R2
AD2 S12 0 0_ CSn
A D2 S12 0 0_ SO E
A D2 S 12 0 0_ RDVEL n
A D2 S 12 0 0_ FS1
A D2 S 12 0 0_ FS2
FLT Un_ u c
FLT V n_ u c
FLT Wn _ uc
FLT n _u C
RST n _u c
P WM UT _ uC
P WM UB _ uC
P WM VT _ uC
P WM VB _ uC
P WM WT _u C
P WM WB _u C
P WM UT
PWM UB
P WM VT
P WM VB
P WM WT
PWM WB
P WM UT
P WM UB
P WM VT
P WM VB
P WM WT
P WM WB
FLT Un_ u C
FLT Vn_ u C
FLT Wn _ uC
FLT n _u C
RST _ INn _u C
FLT Un
FLT V n
FLT Wn
FLT n
RST _ INn
FLT Un
FLT V n
FLT Wn
FLT n
RST _ INn
L EV E L_ SHIFTER
i GM R
I_ U
I_ V
I_ W
CAN1 _L
CAN1 _H
A SCTX
A SCRX
S ta to rT e mp
S ta to rT e mp
FLT _ Un
FLT _ Vn
FLT _ Wn
FLT _ n
RST n
i GM R_DI_u C
i GM R_ROUT _u C
i GM R_CLK_ uC
i GM R_CS_ u C
i GM R_RE_ u C
i GM R_INDE X_ u C
CAN1 _L
CAN1 _H
A SC_ TX
A SC_ RX
CAN1 _L
CAN1 _H
A SC_ TX
ASC_ RX
S1
S3
S2
S6
R1
R2
i GM R_DI_u C
i GM R_ROUT _u C
i GM R_CLK _ uC
i GM R_CS_ u C
i GM R_RE_ u C
i GM R_INDE X_ u C
PWM UT _ uc
PWM UB_ uc
PWM VT _ uc
PWM VB_ uc
PWM WT _u c
PWM WB _u c
VDC_ uC
VDC_ uC
V DC
S ta to rT e mp
A
B
NM
A
B
NM
A D2 S12 0 0_ SA M PL En _ uC
A D2 S12 0 0_ RE SET n _u C
T EM P_ IGB T _W
T EM P_ IGBT _U
T EM P_ IGB T _V
T EM P_ HP2 _ W
T EM P_ HP2 _ U
T EM P_ HP2 _ V
T EM P_ BOARD
A D2 S12 0 0_ SA M PL E_ u C
A D2 S12 0 0_ RE SET n _u C
A D2 S12 0 0_ CS n _u C
A D2 S12 0 0_ SO E _u C
A D2 S12 0 0_ CS n _u C T EM P_ Boa rd
A D2 S12 0 0_ SO E_u C
A D2 S12 0 0_ RDVEL n _u C
A D2 S12 0 0_ FS1 _u C
A D2 S12 0 0_ FS2 _u C
CONNE CTO R_ Drive rBo a rd
T em p_ B oa rd
A D2 S12 0 0_ RDVEL n _u C
A D2 S12 0 0_ FS1 _u C
A D2 S12 0 0_ FS2 _u C
L EV E L_ SHIFTER_ RESOL V ER
A D2 S 12 0 0_ DO S
A D2 S 12 0 0_ L OT
A D2 S 12 0 0_ DB 1 1_ S O
A D2 S 12 0 0_ DB 1 0_ S CL K
AD2 S12 0 0_ DB9
AD2 S12 0 0_ DB8
AD2 S12 0 0_ DB7
AD2 S12 0 0_ DB6
AD2 S12 0 0_ DB5
AD2 S12 0 0_ DB4
AD2 S12 0 0_ DB3
AD2 S12 0 0_ DB2
AD2 S12 0 0_ DB1
AD2 S12 0 0_ DB0
Reso l ve r
A D2 S12 0 0_ DO S
A D2 S 12 0 0_ DO S
A D2 S12 0 0_ L OT
A D2 S12 0 0_ DB 1 1_ SO A D2 S 12 0 0_ L OT
A D2 S12 0 0_ DB 1 0_ SCL K A D2 S 12 0 0_ DB 1 1_ S O
A D2 S 12 0 0_ DB 1 0_ S CL K
A D2 S12 0 0_ DB 9
A D2 S 12 0 0_ DB 9
A D2 S12 0 0_ DB 8
A D2 S 12 0 0_ DB 8
A D2 S12 0 0_ DB 7
A D2 S 12 0 0_ DB 7
A D2 S12 0 0_ DB 6
A D2 S 12 0 0_ DB 6
A D2 S12 0 0_ DB 5
A D2 S 12 0 0_ DB 5
A D2 S12 0 0_ DB 4
A D2 S 12 0 0_ DB 4
A D2 S12 0 0_ DB 3
A D2 S 12 0 0_ DB 3
A D2 S12 0 0_ DB 2
A D2 S 12 0 0_ DB 2
A D2 S12 0 0_ DB 1
A D2 S 12 0 0_ DB 1
A D2 S12 0 0_ DB 0
A D2 S 12 0 0_ DB 0
E Nn
SERIAL _ PA RAL LE L _M ODE _u C
SERIAL _ PA RAL LE L _M ODE_u C
A D2 S12 0 0_ DO S _u C S ERIAL _ PA RA L LE L _M ODE_u C
A D2 S12 0 0_ DO S _u C
A D2 S12 0 0_ L OT _u C A D2 S12 0 0_ DO S_u C
A D2 S 12 0 0_ L OT _u C
AD2 S12 0 0_ DB1 1_ S O_ u C A D2 S12 0 0_ L OT _u C
A D2 S 12 0 0_ DB 1 1_ S O_ u C
A D2 S 12 0 0_ DB 1 0_ SCL K _u C A D2 S12 0 0_ DB 1 1_ SO_ u C
A D2 S 12 0 0_ DB 1 0_ S CL K _u C
A D2 S12 0 0_ DB 9 _u C A D2 S12 0 0_ DB 1 0_ SCL K_u C
AD2 S12 0 0_ DB9 _u C
A D2 S12 0 0_ DB 8 _u C A D2 S12 0 0_ DB 9 _u C
AD2 S12 0 0_ DB8 _u C
A D2 S12 0 0_ DB 7 _u C A D2 S12 0 0_ DB 8 _u C
AD2 S12 0 0_ DB7 _u C
A D2 S12 0 0_ DB 6 _u C A D2 S12 0 0_ DB 7 _u C
AD2 S12 0 0_ DB6 _u C
A D2 S12 0 0_ DB 5 _u C A D2 S12 0 0_ DB 6 _u C
AD2 S12 0 0_ DB5 _u C
A D2 S12 0 0_ DB 4 _u C A D2 S12 0 0_ DB 5 _u C
AD2 S12 0 0_ DB4 _u C
A D2 S12 0 0_ DB 3 _u C A D2 S12 0 0_ DB 4 _u C
AD2 S12 0 0_ DB3 _u C
A D2 S12 0 0_ DB 2 _u C A D2 S12 0 0_ DB 3 _u C
AD2 S12 0 0_ DB2 _u C
A D2 S12 0 0_ DB 1 _u C A D2 S12 0 0_ DB 2 _u C
AD2 S12 0 0_ DB1 _u C
A D2 S12 0 0_ DB 0 _u C A D2 S12 0 0_ DB 1 _u C
AD2 S12 0 0_ DB0 _u C
A D2 S12 0 0_ DB 0 _u C
T EM P_ BOARD
L EV E L_ SHIFTER_ RESOL V ER
A DC_ IN1
A DC_ IN2
A DC_ IN3
A DC_ IN1
A DC_ IN2
A DC_ IN3
DIO _ 1
DIO _ 2
DIO _ 3
DIO_ 1
DIO_ 2
DIO_ 3
uC
CONNE CTO R
Figure 57
Schematics Block Overview
Application Note
59
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Q _S TB Y
+1.0 V
V DIG50
+5.0 V
Q_S TB Y V DIG 33
+1.0 V
+3.3 V
V DIG 33
+3.3 V
V DIG 15
+1.5 V
D5
D6
25
WDO
RT
17
C1159
1n/16V/X7R
2
WDI
Figure 58
IN
7
3
1
8
Q2
B DP 9 49
V DIG 33
+3.3 V
G ND_DIG1
V DIG 33
+3.3 V
P OWERrstn
V re f5 0
IC5 3
+5.0 V
M AX 614 3A A SA 5 0
6
O UT
K L_ 30
+12 .0V
D2
I.C._1
I.C._8
B ZV 5 5/C13
R128
1 0K
R48 6 0 R / 0.1 %
G ND_RE F1
C1136
22u/16V/X7R/F_1463575
C86
22u/16V/X7R/F_1463575
L9
M URAT A _B L M2 1P G 22 1 SN
G ND_DIG1
Q4
IPD9 0P 0 3P 4 L-0 4
5
G ND_A NA1
G ND_DIG1
V ANA5 0
+5.0 V
G ND_A NA1
V ANA3 3
+3.3V
C11 5 7
C12 3
10u /10V /X7R
100 n /16 V/X 7 R
R113
S MK -R0 0 0 / Isab el l enh uette
K L_ 3 0_ IN
+12 .0 V
T RIM
L1
M URAT A _B L M2 1P G 22 1 SN
G ND_DIG1
R47 6
1 0K
S HDN
T EM P
G ND_DIG1
D3
1 SM B3 0 AT 3
Q _S TB Y
+1.0 V
G ND_DIG1
G ND_DIG1
GND_A NA1
Q _T 2
+5.0 V
G ND_DIG1
Q_T 1
+5.0 V
C1155
22u/16V/X7R/F_1463575
Q _T 1
+5.0 V
G ND_DIG1
C85
100n/50V/X7R
3
GND
V DIG50
+5.0 V
4
C1167
100n/50V/X7R/C0805F104K5
C1166
4.7u/50V/X7R/C1210F475K5
L 10
31
FB_ E XT
Q _T 2
+5.0 V
8
Q _T 2 7
Q _T 1 3
RO_ 1 4
RO_ 2
1
V DIG 15
+1.5 V
G ND_DIG1
2
G ND_DIG1
K L_ 3 0
+12 .0 V
M URAT A _B L M2 1P G 22 1 SN
V DIG 50
+5.0 V
V DIG 50 V DIG 33
+5.0 V
+3.3 V
4
30
2
6
32
G ND_DIG1
G ND_DIG1
C1146
4u7/10V/X7R/F_9402195
24
DRV _ EX T
S EL _ Q2
E N_ u C
E N_ IGN
G ND_DIG1
29
5
+
D1
M BRS34 0T 3
C1144
4u7/10V/X7R/F_9402195
23
9
10
28
T yp XX L
C1154
22u/16V/X7R/F_1463575
G ND_DIG1
Q _L DO1
Q _L DO2
L3
S S12 _1 A _If_ 20 V_V r S S1 2 _1A _If_20V_ V r
C1145
1u/25V/X7R/F_1637035
C2+
CCP
C11 56
2 20n /25 V/X 7 R/F_14 14 626
R47 4 1 0K
R47 5 1 0K
K L_ 30
+12.0 V
FB
IN_ LDO 2
PAD
GND_A1
GND_A2
GND_A3
GND_A4
V DIG 33
+3.3 V
B ST
C1C2-
GND_P
G ND_DIG1
C11 53
1 00n /50 V/X 7 R1 5
16
IN1
IN2
IN3
C1+
WE_74 4 77 0 94 70
C1152
100uF_35V_MAL214097001E3
C11 51
1 00n /50 V/X 7 R1 2
13
IN_ S TB Y
S EL _ ST BY
V SW
+5.4 V
R47 3
10K
C1142
4u7/10V/X7R
20
21
22
14
33
Q _S TB Y 3 5
M ON_S T BY 2 6
S W1 2 7
S W2
C1150
680n/50V/F_1414702
34
11
37
1
18
19
36
+
C92
220nF/100V/C3216X7R2A224KT5
C93
100uF_35V_MAL214097001E3
IC13
T LE 7 36 8E
C1135
22u/16V/X7R/F_1463575
K L_ 30
+12 .0V
C11 58
10u /1 0V /X7 R
G ND_A NA1
V DIG 15
+1.5V
V ANA1 5
+1.5 V
L 11
M URAT A _B L M2 1P G22 1 SN
GND_DIG1
Power Supply
V DIG 33
+3.3 V
R1
1 0K
R2 R3 R4 R5
1 0K 1 0K 1 0K 1 0K
K 3-O CDS
Rese tn
B RK OUT n
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
HEA DE R 8 X 2
T MS
T DO
T DI
T RS Tn
T CK
B RK INn
R6
1 0K
G ND_DIG1
Figure 59
JTAG Debug Connector
Application Note
60
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
G ND_A NA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R_opt
1n/50V/X7R_opt
P2
P4
P6
P8
P 10
P 12
P 14
P 16
P 18
P 20
P 22
P 24
P 26
P 28
P 30
P 32
P 34
P 36
P 38
P 40
P 42
P 44
P 46
P 48
P 50
GND_ANA1
S2
S6
S3
S 1 V ANA5 0
R1 +5.0 V
R2
I_U
I_V
I_W
i GM R_ CSn +
i GM R_ DAT A i GM R_ DAT A +
i GM R_ CLK i GM R_ CLK +
CAN1_ L
CAN1_ H
A SC_T X
A SC_RX
G ND_DIG1
C1208
1n/50V/X7R_opt
C1205
1n/50V/X7R_opt
C1207
C1204
1n/50V/X7R_opt
1n/50V/X7R_opt
C1203
1n/50V/X7R_opt
C1206
C1209
1n/50V/X7R_opt
C1202
G ND_DIG1
Harwi n M 80 -51 2 50 4 2P
C ap a ci t or s f o r E SD Pr o te c ti o n o fG ND_DIG1
uC
Figure 60
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1n/50V/X7R_opt
1n/50V/X7R C1197
1n/50V/X7R C1196
1n/50V/X7R C1195
1n/50V/X7R C1194
1n/50V/X7R C1193
1n/50V/X7R C1192
1n/50V/X7R C1191
1n/50V/X7R C1190
1n/50V/X7R C1189
1n/50V/X7R_opt C1188
1n/50V/X7R_opt C1187
GND_DIG1
i GM R_ CSn i GM R_ REn _ DE +
i GM R_ REn _ DE P osA /i G MR_ A+
P osA /i G MR_ AP osB /i G MR_ B+
P osB /i G MR_ BP osZ/iG MR_ Z+
P osZ/iG MR_ ZP osU/i G MR_ U
P osV /i G MR_ V
P osW/i G MR_ W
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
1n/50V/X7R_opt
DIO _ 1
V DIG 50 DIO _ 2
+5.0 V DIO _ 3
K2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
C11 7 7 C11 7 8 C11 7 9 C11 8 0 C11 8 1 C11 8 2 C11 8 3 C11 8 4 C11 8 5
C1201
P1
P3
P5
P7
P9
P 11
P 13
P 15
P 17
P 19
P 21
P 23
P 25
P 27
P 29
P 31
P 33
P 35
P 37
P 39
P 41
P 43
P 45
P 47
ADC_IN1
ADC_IN2
ADC_IN3
S ta to rT e mp
VDIG 50
+5.0 V
1n/50V/X7R
1n/50V/X7R
C11 7 3 C11 7 4 C11 7 5 C11 7 6
1n/50V/X7R
1n/50V/X7R
1n/50V/X7R_opt
1n/50V/X7R
1n/50V/X7R
C11 6 9 C11 7 0 C11 7 1 C11 7 2
1n/50V/X7R_opt
GND_DIG1 GND_ANA1
1n/50V/X7R
G ND_DIG1
KL_ 3 0_ IN
+12 .0V
G ND_DIG1
Connector (external)
V DIG 33
+3.3 V
s et 2
0
0
0
0
1
1
1
1
s et 1
0
0
1
1
0
0
1
1
se t 0
0
1
0
1
0
1
0
1
t de l ay , tw d
1ms
1 0 ms
3 0 ms
D is a bl e d
1 00 m s
1s
1 0s
6 0s
C12 1 0
1 00 n /1 6 V/X 7 R
R14 9
o pt
R15 0
4 K7
IC2 3
R15 1
4 K7
8
2
G ND_DIG1
G ND
WDI
NC
S ET 0
S ET 1
S ET 2 WDO
1
WDI
3
7
W\D\O\
R15 4
o pt
J1
Jum p er
2
R15 3
4 K7
MA X 63 6 9K A -T
2
1
1
4
5
6
V cc
G ND_DIG1
Figure 61
Watchdog
Application Note
61
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
V ANA5 0
+5.0 V
C116 3
G ND_A NA1
T P5
100 n/16V/X7 R
IC4 A P ACKAG E = 1
LT16 39 HS
3
V+
+
1
R10 2
2
0R
11- V 4
T estp ad _SM D_ Etti nge r
C1112
IC8
1
2
3
4
5
6
7
8
9
10
11
3
D2 S 120 0_ SO E
2A
5
VCC
1A
1Y
2Y
A D2 S 12 00_ CSn
6
4
A D2 S 12 00_ SO E n
A D2 S 12 00_ RDV EL n
A D2 S 12 00_DB 11_ S O
A D2 S 12 00_ DB 10_ SCL K
A D2 S 12 00_ DB 9
A D2 S 12 00_ DB 8
A D2 S 12 00_ DB 7
74L V C2 G04 GW
T estp ad _SM D_E tti n ge r
DVd d
RD
CS
S AM PL E
RDV EL
S OE
DB1 1/S O
DB1 0/S CLK
DB9
DB8
DB7
RES ET
FS2
FS1
L OT
DOS
DIR
NM
B
A
CPO
DGND
4
T estpad _SM D_ Etti n
R15 6
2 K4/0.1 %
G ND_A NA1
33
32
31
30
29
28
27
26
25
24
23
R15 7
390/0 .1 %
AD2S 120 0_RE S ET n
AD2S 120 0_FS2
AD2S 120 0_FS1
AD2S 120 0_L OT
AD2S 120 0_DO S
NM
B
A
R15 9
3K3 /0.1%
G ND_A NA1
R15 8
2 K4/0.1%
2
3
6
5
8
T P4
T estp ad _SM D_E tti n ge r
+Vs
IC6
R15 5
2 K4/0.1%
V ANA5 0
+5.0V
IN-1
O UT 1
IN+1
1
R2
T P3
T estp ad _SM D_E tti n ge r
IN-2
O UT 2
IN+2
7
R1
LMH66 72
G ND_A NA1
R160
2K4 /0.1%
R48 5
5 K_ pot_0,2 5W_20% _Bo urn s_3 314J_op t
AD2S1200_DB2
AD2S1200_DB1
AD2S1200_DB0
AD2S1200_DB6
AD2S1200_DB5
AD2S1200_DB4
AD2S1200_DB3
G ND_DIG1
U1
G ND_DIG1
1
1
2
2
G ND_DIG1
20pF/50V/COG
C84
20pF/50V/COG
4u7/25V/X7R
C83
HCM 49 8 .1 9 2M A BJ-UT
C82
10n/16V/X7R
C81
V DIG50
+5.0V
G ND_DIG1
Resolver Interface
1 0K
G ND_DIG1
1K
IC2
1
48
47
46
44
43
41
40
38
37
P WM WT _u C
P WM WB _u C
P WM VT _u C
P WM VB _u C
P WM UT _u C
P WM UB _u C
RST _INn _u C
36
35
33
32
30
29
27
26
FLT Un_ u C
FLT V n_ u C
FLT Wn _ uC
FLT n _u C
V DIG 33
+3.3 V
C65
1 00 n /1 6 V/X 7 R
G ND_DIG1
31
42
4
10
15
21
1 DIR
1 OE
1 A0
1 A1
1 A2
1 A3
1 A4
1 A5
1 A6
1 A7
2 A0
2 A1
2 A2
2 A3
2 A4
2 A5
2 A6
2 A7
2 DIR
2 OE
1 B0
1 B1
1 B2
1 B3
1 B4
1 B5
1 B6
1 B7
2 B0
2 B1
2 B2
2 B3
2 B4
2 B5
2 B6
2 B7
V CCA V CCB
V CCA V CCB
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
R80
G ND_DIG1
1K
G ND_DIG1
R88
R74
R75
R76
R77
R78
R79
1K
1K
1K
1K
1K
1K
V DIG50
+5.0 V
R71
R73
G ND_DIG1
10K
Figure 62
G ND_ANA1
G ND_DIG1
AD2S 120 0Y ST
12
13
14
15
16
17
18
19
20
21
22
R47 1
10K
100n /16 V/X 7R
GND
S 120 0_ SA M PL En
2
1
C76
GND_DIG1
C116 4
G ND_DIG1
IC3 0
C144
100n /25 V/X 7R
R483
5 K_ pot_0,2 5W_20% _Bo urn s_3 314J_op t
C121 7
opt
T P2
REFOUT
REFBYP
AGND
Cos
CosLO
AVdd
SinLO
Sin
AGND
EXC
EXC
V DIG 33
+3.3 V
C14 3
2 2uF/16 V/X 7R
G ND_DIG1
C121 6
opt
T estp ad _SM D_E tti n ge r
10n/16V/X7R
C79
C80
o pt
G ND_DIG1
G ND_A NA1
T P1
G ND_A NA1
L8
C1111
2 2u F/16 V/X 7 R
GND_A NA1
V DIG 50
+5.0 V
R10 9
opt
R11 0
INH
T P9
G ND_DIG1
G ND_A NA1
M URAT A _B L M21PG 221 SN
3
Q
-Vs
-
GND_A NA1
CosL O
R10 8
0R
Cos
CosLO
14
DB6
DB5
DB4
DB3
DGND
DVdd
DB2
DB1
DB0
XTALOUT
CLKIN
+
4u7/25V/X7R
13
44
43
42
41
40
39
38
37
36
35
34
12
T LE 4266 GSV10
I
4
IC4 D P ACKAG E = 1
G ND_A NA1
LT16 39 HS
T estp ad _SM D_ Etti nge r
4u7/16V/X7R
R10 7
opt
T P8
S6
C77
T estpad_ SM D_ E tti n ge r IC4 C P ACKAG E = 1
LT16 39 HS
G ND_A NA1
10
S2
+
8
Cos
R10 6
9
0R
-
2
100n/50V/X7R/C0805F104K5
V ANA5 0
+5.0V
10uF/10V/X7R
R10 5
opt
T P7
IC25
1
S in L O
R10 4
0R
-
KL_ 30
+12 .0V
C75
10n/16V/X7R
6
7
GND
GND_A NA1
IC4 B P ACKAG E = 1
LT16 39 HS
G ND_A NA1
+
SinLO
Sin
5
R484
5K_pot_0,25W_20%_Bourns_3314J_opt
T P6
T estp ad _SM D_ Etti nge r
S3
S in
R10 3
opt
10n/16V/X7R
C78
S1
P WM WT
24
25
P WM WB
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
7
18
28
34
39
45
P WM VT
P WM VB
RST _INn
1 5K
1K
R90
V DIG 50
+5.0 V
R92
P WM UT
P WM UB
FLT Un
C64
1 00 n /1 6 V/X 7 R
V DIG 50
+5.0 V
G ND_DIG1
C66
1 00 n /1 6 V/X 7 R
1K
1 5K
V DIG 50
+5.0 V
FLT V n
C68
1 00 n /1 6 V/X 7 R
1 5K
G ND_DIG1
7 4A L VC16 4 24 5 DG G
R93
R95
1K
R96
V DIG 50
+5.0 V
R98
FLT Wn
C70
1 00 n /1 6 V/X 7 R
G ND_DIG1
1K
1 5K
R99
V DIG 50
+5.0 V
R10 0
FLT n
C71
1 00 n /1 6 V/X 7 R
G ND_DIG1
Figure 63
Level Shifter for Adapting Logic Levels for Driver Board
Application Note
62
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
R49 7 0 R
E Nn
S ERIAL _ PA RA LLE L _M ODE _u C
IC2 9
R45 6 1 K
1
48
G ND_DIG1
47
46
44
43
41
40
38
37
A D2 S 12 0 0_ DB 9 _u C
A D2 S 12 0 0_ DB 8 _u C
A D2 S 12 0 0_ DB 7 _u C
A D2 S 12 0 0_ DB 6 _u C
A D2 S 12 0 0_ DB 5 _u C
A D2 S 12 0 0_ DB 1 0_ S CLK _u C
36
35
33
32
30
29
27
26
A D2 S 12 0 0_ LOT _u C
A D2 S 12 0 0_ DO S _u C
A D2 S 12 00_ DB 1 1_ SO_ u C
A D2 S 12 0 0_ DB 4 _u C
A D2 S 12 0 0_ DB 3 _u C
A D2 S 12 0 0_ DB 2 _u C
A D2 S 12 0 0_ DB 1 _u C
A D2 S 12 0 0_ DB 0 _u C
31
42
4
10
15
21
V DIG 33
+3.3 V
1 DIR
1 OE
2 DIR
2 OE
1 A0
1 A1
1 A2
1 A3
1 A4
1 A5
1 A6
1 A7
1 B0
1 B1
1 B2
1 B3
1 B4
1 B5
1 B6
1 B7
2 A0
2 A1
2 A2
2 A3
2 A4
2 A5
2 A6
2 A7
2 B0
2 B1
2 B2
2 B3
2 B4
2 B5
2 B6
2 B7
V CCA V CCB
V CCA V CCB
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
24
25
G ND_DIG1
2
3
5
6
8
9
11
12
A D2 S 120 0_DB 9
A D2 S 120 0_DB 8
A D2 S 120 0_DB 7
A D2 S 120 0_DB 6
A D2 S 120 0_DB 5
A D2 S 120 0_DB 1 0_ S CL K
13
14
16
17
19
20
22
23
A D2 S 120 0_L OT
A D2 S 120 0_DO S
A D2 S 120 0_DB 1 1_ S O
A D2 S 120 0_DB 4
A D2 S 120 0_DB 3
A D2 S 120 0_DB 2
A D2 S 120 0_DB 1
A D2 S 120 0_DB 0
7
18
28
34
39
45
V DIG 50
+5.0 V
74L V CH1 6T 24 5 DL
C11 3 2
1 00 n/16 V/X 7 R
R49 8 0 R_ o pt
G ND_DIG1
C11 3 3
1 00 n /16 V/X 7R
G ND_DIG1
Figure 64
Level Shifter for Adapting Logic Levels for Resolver IC
V DIG33
+3.3 V
L5
M URAT A _B L M2 1P 2 21 S N
Rese tn
P WM VB n
P 1_ 9
P WM WT n
GPT A27
P WM WB n
10n/16V/X7R
C105
P WM VT n
GPT A19
GND_DIG1
GPT A39
WDI
P ORST n
RST n
P 3_ 1 3
T XDCA N1
RXDCA N1
C109
T XD0 A
RXD0 A
V DC_ uC
T EM P_ IGB T _U
T EM P_ IGB T _V
T EM P_ IGB T _W
T EM P_ B oa rd
S ta to rT e mp
I_ U
I_ V
I_ W
A DC_ IN1
A DC_ IN2
A DC_ IN3
P 1_ 8
P 1_ 1 0
P 4_ 3
DIO_ 1
DIO_ 2
DIO_ 3
P 4_ 1
P 4_ 0
P 2_ 5
P 4_ 1
P 4_ 0
P 2_ 5
V DC
A N2 9
A N2 9
T EM P_ IGB T _U
T EM P_ IGB T _V
T EM P_ IGB T _W
T EM P_ B oa rd
S ta to rT e mp
A N1
A N2
A N3
A N4
A N5
A N1
A N2
A N3
A N4
A N5
I_ U
I_ V
I_ W
A N1 5
A N1 4
A N1 3
A N3 1
A N1 5
A N1 4
A N1 3
A N3 1
A DC_ IN1
A DC_ IN2
A DC_ IN3
A N1 7
A N1 8
A N1 9
A N1 7
A N1 8
A N1 9
P 5_ 0
P 5_ 1
P 5_ 2
P 5_ 3
P 5_ 4
P 5_ 5
P 5_ 6
P 5_ 7
P 5_ 8
P 5_ 9
P 5_ 1 2
P 5_ 1 3
P 5_ 1 5
P 3_ 1 0
P 3_ 1 1
P 3_ 1 2
A D2S 12 0 0_ DB 0 _u C
A D2S 12 0 0_ DB 1 _u C
A D2S 12 0 0_ DB 2 _u C
A D2S 12 0 0_ DB 3 _u C
A D2S 12 0 0_ DB 4 _u C
GND_DIG1
A D2S 12 0 0_ DB 5 _u C
A D2S 12 0 0_ DB 6 _u C
A D2S 12 0 0_ DB 7 _u C
A D2S 12 0 0_ DB 8 _u C
A D2S 12 0 0_ DB 9 _u C
R13 3
A D2S 12 0 0_ DO S _u C
5 K1
A D2S 12 0 0_ L OT _u C
A D2S 12 0 0_ RDV EL n _u C
G ND_DIG1
GND_DIG1
CAN_ TX 1
CAN_ RX 1
1
4
8
T xD
RxD
INH
A D2 S 12 0 0_ RE S ET n _u C
A D2S 12 0 0_ FS1 _u C
A D2S 12 0 0_ FS2 _u C
IC1 7
T LE 6 25 0 GV 33
CANH
CANL
B 82 7 89 C01 0 4N0 01
7
6
1
4
2
3
R13 1
6 0R
R13 2
6 0R
C11 0
4 .7n /50 V /X 7 R
G ND_DIG1
CAN1 _L
GND_DIG1
GPT A3
P 5_ 1 1
P 5_ 1 0
A D2S 12 0 0_ SA M PL E_ u C
A D2 S 12 0 0_ DB 1 1_ S O_ u C
A D2 S 12 0 0_ DB 1 0_ S CL K _u C
C114
V DIG33
+3.3 V
T XDOA
S W2
S W DIP -4 /S M
In pu t_Fil ter
R13 4
RXDOA
iGMR
A D2 S 12 0 0_ SO E _u C
S ERIAL _ PA RA L LE L _M ODE _u C
i GM R d i sa b le d : ( sw i tc h p i n 1 c l os e d ( ON ) )
S LS O1
S LS O2
P 3_ 8
P 2_ 1 2
GND_DIG1
i GM R_INDE X_ u C
i GM R_CLK _ uC
i GM R_ROUT _u C
S CL K 1
M RS T1
3
4
11
10
12
9
15
C1C2+
V-
6
C214
T 1in T 1o u t 7
T 2in T 2o u t 1 3
R1o u t R1in 8
R2o u t R2in
GND
V cc
16
C11 1
1 00 n /16 V/X 7R
C11 3
1 00 n /16 V/X 7 R
GND_DIG1
A SCTX
R13 5
1K
A SCRX
V DIG33
+3.3 V
GND_DIG1
C115
i GM R S e ri a l M od e /E n co d er Mo d e:
( sw i tc h p i n 1 o p en (O F F) ) - > i G MR _ IN D EX _ uC lo w
IC5 2
M AX 32 3 2E IPWRQ1
1
2
C1+
V+
5
1K
R es o lv e r S er i al (2 , 3, 4 i s O N )
- u C _T C 17 6 7. S CL K 1 d ri v es
- M R ST 1 a s i n pu t , d ri v en by Re s ol v er
- S E RI A L_ P AR A LL E L_ M OD E _u C i s
De f au l t i s s er i al mo d e
- A D 2S 1 20 0 _C S n_ u C
CAN1 _H
FL1
3
5
P 1_ 8
P 1_ 1 0
P 4_ 3
2
DIO_ 1
DIO_ 2
DIO_ 3
A
B
NM
C112
A
B
NM
V DIG33
+3.3V
100n/16V/X7R
P osW/iG MR_ W
V DIG50
+5.0 V
E EP RO M
C107
P osV /iG MR_ V
P osW/i G MR_ W
P 4_ 2
P 2_ 0
P 2_ 2
100n/16V/X7R
P osV /iG MR_ V
P 4_ 2
P 2_ 0
P 2_ 2
22uF/6.3V/X7R
P osU/iG MR_ U
S CL K 0
M RS T0
M TS R0
S LS O0
Vcc
V33V
P osU/iG MR_ U
P 0_ 1 2
P 0_ 1 4
P 0_ 1 1
GND
P 0_ 1 2
P 0_ 1 4
P 0_ 1 1
CSn
SCK
SI
SO
P osA /iG MR_ A+
P osA /iG MR_ AP osB /iG MR_ B+
P osB /iG MR_ BP osZ/iG MR_ Z+
P osZ/iG MR_ Z-
100n/16V/X7R
C108
INP UT_ FIL T ER
P osA /iG MR_ A+
P osA /iG MR_ AP osB /iG MR_ B+
P osB /iG MR_ BP osZ/iG MR_ Z+
P osZ/iG MR_ Z-
100n/16V/X7R
RST n
P WM UT n
P WM UB n
GPT A18
100n/16V/X7R
R10 1
1 0K
Rese tn
T RS Tn
T CK
T DI
T DO
T MS
B RK OUT n
B RK INn
Clk
GPT A8
GPT A9
EEPROM
V DIG33
+3.3 V
GPT A2 0
22uF/6.3V/X7R
T RS Tn
T CK
T DI
T DO
T MS
B RK OUT n
B RK INn
T RS Tn
T CK
T DI
T DO
T MS
B RK OUT n
B RK INn
P 1_ 5
P 1_ 6
P 1_ 7
C106
FLT _ n
FLT _ n
100n/16V/X7R
C104
IC1 6
E H2 6 45 E TT TS -20 .0 00 M
4
1
V DC
T RI
3
2
O UT GND
u c_ T C1 7 67
FLT _ Un
FLT _ Vn
FLT _ Wn
FLT _ Un
FLT _ Vn
FLT _ Wn
GND_DIG1
A D2 S 12 0 0_ CS n _u C
i GM R_CS_ u C
i GM R_RE_ u C
i GM R_DI_u C
u c_ T C1 7 67
Figure 65
Microcontroller
Application Note
63
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
V ANA5 0
+5.0 V
6 8K
R19 4
o pt
R17 7
1 0K
C18 0
1 n/5 0 V/X 7R
V ANA5 0
+5.0 V
A N2
6 8K
R20 5
R20 2
o pt
C18 3
1 n/5 0 V/X 7R
VANA5 0
R17 4
+5.0 V
1 0K
R20 8
o pt
V ANA5 0
+5.0 V
G ND_A NA1
R17 6
o pt
R19 2
o pt
R43 0
6
7
1 0p /50V /X7 R
1 00 R
C10 4 2
R43 1
10
9
1 0p /5 0V /X7 R
C11 47
1 0p /5 0V /X7 R
C11 4 8
1 0p /5 0V/X7 R
1 00 R
14
15
C11 4 9
1 0p /5 0V /X7 R
1 A+
P 0_ 1 2
1K
R18 3
2K
1Y
G ND_DIG1
3
1 B2 A+
2 B3 A+
3 B4 A+
4 B-
2Y
R18 7
5
P 0_ 1 4
1K
3Y
4Y
R19 0
2K
11
G ND_DIG1
13
R19 7
P 0_ 1 1
1K
A M2 6C3 2Q D
G ND_DIG1
A N1 9
5 1K
C17 2
1 n/5 0 V/X 7R
G+
G-
1 00 n /16 V/X 7 R
R20 1
2K
G ND_A NA1
ADC_ IN3
G ND_A NA1
T EM P_ B oa rd
2
C10 41
R19 5
1 0K
R19 9
A N4
6 8K
1 00 R
P osZ/iG MR_ ZA N1 8
C18 7
1 n/5 0 V/X 7R
R42 9
P osZ/iG MR_ Z+
C17 8
1 n/5 0 V/X 7R
4
C10 4 5
1 0p /5 0V /X7 R1 2
1
1 0p /5 0V /X7 R
P osB /iG MR_ B-
5 1K
R17 5
S ta to rT emp
P osA /iG MR_ AP osB /iG MR_ B+
G ND_A NA1
ADC_ IN2
A N3
6 8K
R18 1
o pt
C17 3
1 n/5 0 V/X 7R
R18 6
1 0K
R18 8
G ND_A NA1
T EM P_ IGB T _W
A N1 7
R17 8
5 1K
G ND_A NA1
T EM P_ IGB T _V
C10 4 0
P osA /iG MR_ A+
ADC_ IN1
C10 4 4
1 0p /5 0V /X7 R
GND
A N1
C10 4 3
1 0p /5 0V /X7 R
8
T EM P_ IGB T _U
R18 0
G ND_DIG1
IC3 3
R19 1
R19 8
V DIG 50
+5.0 V
C11 6 0
G ND_DIG1
Encoder Inputs/iGMR Inputs
(iGMR Emulates Encoder)
16
General Purpose Analogue IN
Vcc
Temperature and DC Bus Measurements
R20 3
o pt
G ND_DIG1
Hall Sensor/iGMR Inputs (iGMR Emulates Hall Sensor)
Assumed Open-Collector output from Hall sensor
C18 4
1 n/5 0 V/X 7R
G ND_A NA1
R49 1
2 K7
R49 2
2 K7
V DIG33
+3.3 V
R49 3
2 K7
A N5
R49 4
P osU/iG MR_ U
P 4_ 2
1K
D7
B AT 5 4-0 4W
C12 13
o pt
R18 4
A N2 9
V DC
6 8K
R18 5
o pt
G ND_DIG1
R49 5
C17 6
1 n/5 0 V/X 7R
P osV /iG MR_ V
P 2_ 0
1K
G ND_A NA1
D8
B AT 5 4-0 4W
C12 14
o pt
G ND_DIG1
R49 6
V ANA5 0
+5.0 V
Phase Current Sense
L 12
M URAT A _B L M2 1P G 22 1 SN
R21 5
I_ U
1 00 n /16 V/X 73R
C10 6 4
2
6 K8
3 30 0 p/1 0 V/C0G
C19 1
R47 7
6 80 0 p/1 0 V/C0G
G ND_A NA1
o pt
G ND_A NA1
6 K8
+
V+
P ACKA G E = 1
1
DIO_ 2
G ND_A NA1
IC3 1 B P ACKA G E = 1
L T1 6 39 HS
5
R22 4
+
7
C10 6 5
6
6 K8
3 30 0 p/1 0 V/C0G
0 R_ o pt
C19 4
R48 0
R47 9
R22 9
6 80 0 p/1 0 V/C0G
G ND_A NA1
o pt
0R
G ND_A NA1
6 K8
0R
R21 8
6 K8
R23 5
10
C10 6 7
9
6 K8
3 30 0 p/1 0 V/C0G
C19 6
R48 1
6 80 0 p/1 0 V/C0G
G ND_A NA1
o pt
G ND_A NA1
-
0R
R24 1
2K
G ND_DIG1
AN1 3
G ND_A NA1
12
13
Figure 66
P 4_ 3
1K
C18 2
1 00 p /50 V/X 7 R
GND_DIG1
8
R48 2
R23 9
2K
NM
P 2_ 5
R20 0
9 1K
G ND_DIG1
G ND_DIG1
R24 0
GND_DIG1
5 1K
G ND_DIG1
P 1_ 1 0
1K
C17 9
1 00 p /50 V/X 7 R
R19 6
IC3 1 C P ACKA G E = 1
L T1 6 39 HS
+
R19 3
9 1K
DIO_ 3
A N3 1
G ND_A NA1
3 K3
R23 0
I_ W
B
P 4_ 0
5 1K
A N1 4
R23 7
2K
G ND_DIG1
R23 8
R18 9
R22 8
C12 15
o pt
P 1_ 8
1K
GND_DIG1
0R
G ND_A NA1
I_ V
R23 4
A
C17 4
1 00 p /50 V/X 7 R
AN1 5
- VR47 8
R47 2
3 K3
R22 3
R18 2
9 1K
D9
BAT 5 4-0 4W
Emulated encoder outputs out of AD2S1200
P 4_ 1
5 1K
G ND_A NA1
P 2_ 2
1K
R17 9
DIO_ 1
C11 6 1
IC3 1 A
L T1 6 39 HS
4
R21 7
11
G ND_A NA1
3 K3
R21 4
P osW/i G MR_ W
General Purpose
Digital IN/OUT
IC3 1 D P ACKA GE = 1
L T1 6 39 HS
+
14
-
Input Filter
Application Note
64
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
V ANA1 5
+1.5 V
V _A REF0
V _FA RE F
V re f5 0
+5.0 V
67
66
65
64
63
62
61
36
A N1
A N2
A N3
A N4
A N5
P ackag e = 1
60
59
58
57
56
55
50
49
G ND_A NA1
G ND_A NA1
IC2 4 F
S AK -TC1 76 7 -2 5 6F1 33 HL
A na l og Inp u ts
48
A N0
A N1 6 4 7
A N1
A N1 7 4 6
A N2
A N1 8 4 5
A N3
A N1 9 4 4
A N4
A N2 0 4 3
A N5
A N2 1 4 2
A N6
A N2 2 4 1
A N7
A N2 3
40
A N8
A N2 4 3 9
A N9
A N2 5 3 8
A N1 0
A N2 6 3 7
A N1 1
A N2 7 3 5
A N1 2
A N2 8 3 4
A N1 3
A N2 9 3 3
A N1 4
A N3 0 3 2
A N1 5
A N3 1
29
A N3 2
A N3 4 2 8
A N3 3
A N3 5
G ND_A NA1
52
26
C14 9
1 00 n /16 V/X 7 R
53
25
51
27
47n/16V/X7R
C145
C147
47n/16V/X7R
C14 8
1 00 n /16 V/X 7 R
V _DDM
V _DDMF
V _DDAF
V ANA3 3
+3.3 V
V_SSM
V_SSMF
V_AGND0
V_FAGND
54
24
23
IC2 4 E
S AK -TC1 76 7 -2 5 6F1 33 HL
A na l og P owe r S up p l y
C146
V ANA3 3
+3.3 V
47n/16V/X7R
V ANA5 0
+5.0 V
G ND_RE F1
A N1 3
A N1 4
A N1 5
G ND_A NA1G ND_A NA1 G ND_A NA1
G ND_RE F1
31
30
G ND_A NA1
G ND_A NA1
G ND_A NA1
A N1 7
A N1 8
A N1 9
G PT A3
G ND_A NA1
1 45
1 46
1 47
1 48
1 66
1 67
1 73
1 74
1 49
1 50
1 51
1 52
1 68
1 69
1 75
1 76
CFG 0
CFG 1
CFG 2
CFG 3
CFG 4
CFG 5
CFG 6
CFG 7
G PT A8
G PT A9
P 0_ 1 1
P 0_ 1 2
A N2 9
P 0_ 1 4
A N3 1
G PT A1 8
G PT A1 9
G PT A2 0
P 1_ 5
P 1_ 6
P 1_ 7
P 1_ 8
P 1_ 9
P 1_ 1 0
G PT A2 7
B RK INn
P 0.0 /IN0 /HWCFG 0/O UT 0/O UT 5 6
P 0.1 /IN1 /HWCFG 1/O UT 1/O UT 5 7
P 0.2 /IN2 /HWCFG 2/O UT 2/O UT 5 8
P 0.3 /IN3 /HWCFG 3/O UT 3/O UT 5 9
P 0.4 /IN4 /HWCFG 4/O UT 4/O UT 6 0
P 0.5 /IN5 /HWCFG 5/O UT 5/O UT 6 1
P 0.6 /IN6 /HWCFG 6/REQ 2/O UT 6 /OUT6 2
P 0.7 /IN7 /HWCFG 7/REQ 3/O UT 7 /OUT6 3
P 0.8 /IN8 /OUT8 /OUT 64
P 0.9 /IN9 /OUT9 /OUT 65
P 0.1 0/IN10 /OUT 10 /OUT 66
P 0.1 1/IN11 /OUT 11 /OUT 67
P 0.1 2/IN12 /OUT 12 /OUT 68
P 0.1 3/IN13 /OUT 13 /OUT 69
P 0.1 4/IN14 /REQ 4/O UT 1 4/O UT 7 0
P 0.1 5/IN15 /REQ 5/O UT 1 5/O UT 7 1
P ackag e = 1
G ND_A NA1
P ackag e = 1
IC2 4 H
1 16
1 19
93
98
1 07
1 08
1 09
1 10
94
95
96
97
73
72
71
1 17
B RK OUT n
IC2 4 G
S AK -TC1 76 7 -2 5 6F1 33 HL
P ort 0: G PT A , S CU
P ort 1: G PT A , S SC1 , A DC0 , OCDS
IC2 4 J
IC2 4 I
P 1.0 /IN1 6/O UT 1 6/O UT 7 2/B RK IN/B RK O UT
P 1.1 /IN1 7/O UT 1 7/O UT 7 3
P 1.2 /IN1 8/O UT 1 8/O UT 7 4
P 1.3 /IN1 9/O UT 1 9/O UT 7 5
P 1.4 /IN2 0/E MG S TO P/O UT 2 0/O UT 7 6
P 1.5 /IN2 1/O UT 2 1/O UT 7 7
P 1.6 /IN2 2/O UT 2 2/O UT 7 8
P 1.7 /IN2 3/O UT 2 3/O UT 7 9
P 1.8 /IN2 4/IN48 /MT S R1 B/O UT 2 4/O UT 4 8
P 1.9 /IN2 5/IN49 /MRS T1 B/O UT 2 5/ O UT 4 9
P 1.1 0/IN26 /IN5 0 /OUT2 6 /O UT5 0 /S L SO 1 7
P 1.1 1/IN27 /IN5 1 /SCLK 1 B/O UT 2 7/O UT 5 1
P 1.1 2/IN16 /OUT 16 /AD0 EM UX 0
P 1.1 3/IN17 /OUT 17 /AD0 EM UX 1
P 1.1 4/IN18 /OUT 18 /AD0 EM UX 2
P 1.1 5/B RKIN/B RKO UT
74
75
76
77
78
79
80
81
1 64
1 60
1 61
1 62
1 63
1 65
P 2_ 0
P 2_ 2
P 2_ 5
G PT A3 9
M RS T1
S CL K 1
P 2_ 1 2
P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL
P ort 2: G PT A , S SC0 /1, ML I0 , M SC0
P 2.0 /IN3 2/O UT 3 2/O UT 2 8/T CL K 0
P 2.1 /IN3 3/T RE A DY 0 A/O UT 33 /S LS O0 3 /SL SO 1 3
P 2.2 /IN3 4/O UT 3 4/O UT 2 9/T VA L ID0 A
P 2.3 /IN3 5/O UT 3 5/O UT 3 0/T DA T A0
P 2.4 /IN3 6/RCL K 0A /OUT 36 /OUT 31
P 2.5 /IN3 7/O UT 1 10 /OUT 37 /RRE ADY0 A
P 2.6 /IN3 8/RVA L ID0 A/O UT 1 11 /OUT 38
P 2.7 /IN3 9/RDA T A0 A /O UT3 9
P 2.8 /SL S O0 4/S L SO 14 /EN0 0
P 2.9 /SL S O0 5/S L SO 15 /EN0 1
P 2.1 0/IN10 /OUT 0/M RS T 1A
P 2.1 1/IN11 /OUT 1/S CL K 1A /FCL P0 B
P 2.1 2/IN12 /OUT 2/M TS R1A /SO P0 B
P 2.1 3/IN13 /OUT 3/S LS I1 1/S DI0
P 3_ 1 0
P 3_ 1 1
P 3_ 1 2
P 3_ 1 3
RXDCA N1
T XDCA N1
P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL
Po rt 3: G PT A, A SC0 /1 , SS C0/1 , S CU, CA N
1 36
1 35
1 29
1 30
1 32
1 26
1 27
1 31
1 28
1 38
1 37
1 44
1 43
1 42
1 34
1 33
RXD0 A
T XD0 A
S CL K 0
M RS T0
M TS R0
S LS O0
S LS O1
S LS O2
P 3_ 8
P 3.0 /OUT8 4 /RX D0 A
P 3.1 /OUT8 5 /TX D0
P 3.2 /OUT8 6 /SCLK 0
P 3.3 /OUT8 7 /MRST 0
P 3.4 /OUT8 8 /MT SR0
P 3.5 /SL S O0 0/S L SO 10 /SL S O0 0 &S L SO 10
P 3.6 /SL S O0 1/S L SO 11 /SL S O0 1 &S L SO 11
P 3.7 /SL S I0 1 /OUT8 9 /S L SO 0 2& SL S O1 2
P 3.8 /SL S O0 6/O UT 9 0/T XD1
P 3.9 /OUT9 1 /RX D1 A
P 3.1 0/O UT 9 2/REQ 0
P 3.1 1/O UT 9 3/REQ 1
P 3.1 2/O UT 9 4/RXDCAN0 /RX D0 B
P 3.1 3/O UT 9 5/T XDCAN0 /T X D0
P 3.1 4/O UT 9 6/RXDCAN1 /RX D1 B
P 3.1 5/O UT 9 7/T XDCAN1 /T X D1
S AK -TC1 76 7 -2 5 6F1 33 HL
P ackag e = 1
IC2 4 L
P 4_ 0
P 4_ 1
P 4_ 2
P 4_ 3
86
87
88
90
P ort 4: G PT A , S CU
P 4.0 /IN2 8/IN52 /OUT 28 /OUT 52
P 4.1 /IN2 9/IN53 /OUT 29 /OUT 53
P 4.2 /IN3 0/IN54 /OUT 30 /OUT 54 /EX T CL K1
P 4.3 /IN3 1/IN55 /OUT 31 /OUT 55 /EX T CL K0
P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL
P ort 5: G PT A , M LI0
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
9
P 5_ 0
P 5_ 1
P 5_ 2
P 5_ 3
P 5_ 4
P 5_ 5
P 5_ 6
P 5_ 7
P 5_ 8
P 5_ 9
P 5_ 1 0
P 5_ 1 1
P 5_ 1 2
P 5_ 1 3
IC2 4 K
P 5_ 1 5
V DIG 33
+3.3 V
P 5.0 /IN2 6/IN40 /OUT 8/O UT 4 0
P 5.1 /IN2 7/IN41 /OUT 9/O UT 4 1
P 5.2 /IN2 8/IN42 /OUT 10 /OUT 42
P 5.3 /IN4 3/O UT 1 1/O UT 4 3
P 5.4 /IN2 9/IN44 /OUT 12 /OUT 44
P 5.5 /IN3 0/IN45 /OUT 13 /OUT 45
P 5.6 /IN3 1/IN46 /OUT 14 /OUT 46
P 5.7 /IN4 7/O UT 1 5/O UT 4 7
P 5.8 /OUT8 9 /RDAT A 0B
P 5.9 /OUT9 0 /RV AL ID0B
P 5.1 0/O UT 9 1/RRE A DY 0 B
P 5.1 1/O UT 9 2/RCL K 0B
P 5.1 2/O UT 9 3/S L SO 07 /TDA TA 0
P 5.1 3/S L SO 16 /T VA LID0 B
P 5.1 4/O UT 9 4/T RE A DY 0 B
P 5.1 6/O UT 9 5/T CL K 0
S W1
1 00 k CFG 7
1 00 k CFG 6
1 00 k CFG 5
1 00 k CFG 4
1 00 k CFG 3
1 00 k CFG 2
1 00 k CFG 1
1 00 k CFG 0
R49 9
R50 0
R50 1
R50 2
R50 3
R50 4
R50 5
R50 6
R16 1
R16 2
R16 3
R16 4
R16 5
R16 6
R16 7
R16 8
1K
1K
1K
1K
1K
1K
1K
1K
T yco _1 -1 57 1 98 3 -1
G ND_DIG1
P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL
V DIG 15
+1.5 V
L7
V DIG 33
+3.3 V
1
R171
4K7
B CR1 83 S
10k
6
LED_LSM676-MQ
Clk
L6
B 82 4 22 A 11 0 3K
C15 0
1 0u /1 0V /X7 R
G ND_DIG1
G ND_DIG1
10K
1 14
1 15
1 11
1 13
1 12
T RS Tn
T CK
T DI
T DO
T MS
0R_opt
P ackag e = 1
R170
V DIG 33
+3.3 V
G ND_DIG1
P ackag e = 1
G ND_DIG1
R173
10K
R172
V DIG 33
+3.3 V
R169
IC2 4 B
S AK -TC1 76 7 -2 5 6F1 33 HL
O sci l l ato r
1 02
1 05
X TA L 1
V _DDOS C 1 06
V _DDOS C3 1 04
1 03
X TA L 2
V SS OS C
220R
D4
V DIG 33
+3.3 V
P ORST n
C15 1
1 0u /1 0V /X7 R
P ACKA G E = 1
Q 6A
2
10k
IC2 4 C
S AK -TC1 76 7 -2 5 6F1 33 HL
G en e ra l Co n tro l
1 21
1 22
P ORST
E SR0
1 18
1 20
T ES TM O DE E SR1
B 82 4 22 A 11 0 3K
V DIG 33
+3.3 V
IC2 4 D
S AK -TC1 76 7 -2 5 6F1 33 HL
O CDS / JTA G Co ntro l
T RS T
T CK /DA P 0
T DI/B RK IN
T DO /DA P2 /B RK OUT
T MS /DA P1
P ackag e = 1
G ND_DIG1
G ND_DIG1
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
C158
C159
100n/16V/X7R
C157
C156
100n/16V/X7R
100n/16V/X7R
C155
C154
100n/16V/X7R
100n/16V/X7R
C153
P owe r S up p l y
V _DD
V _DD(S B )
V _DD
V _DD
V _DD
V _DD
V _DD
V _DD
V _DD
V _DDFL 3
C152
Dig i tal Ci rcu i try
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V _DDP
V _DDP
V _DDP
V _DDP
V _DDP
V _DDP
V _DDP
V _DDP
V _DDP
V _DDP
10
21
68
84
89
99
1 23
1 53
1 70
1 41
C1110
IC2 4 A
P ackag e = 1
S AK -TC1 76 7 -2 5 6F1 33 HL
12
22
70
82
85
92
101
125
140
155
172
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
C171
C170
C169
C168
C167
C166
100n/16V/X7R
100n/16V/X7R
100n/16V/X7R
C165
C164
100n/16V/X7R
C163
C160
G ND_DIG1
11
20
69
83
91
1 00
1 24
1 39
1 54
1 71
100n/16V/X7R
V DIG 15
+1.5 V
V DIG 33
+3.3 V
G ND_DIG1
V DIG 33
+3.3 V
C16 1
1 00 n /1 6 V/X 7 R
G ND_DIG1
Figure 67
Microcontroller TC1767 Pin Assignment
Application Note
65
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
V DIG 33
+3.3 V
R8
1 0K
R9
1 0K
IC1
100n/16V/X7R
C29
R7
1 0K
8
4
7
3
V CC
G ND
S CK
SI
SO
HOL D
WP
CS
6
5
2
S CK
SI
SO
1
CSn
A T2 5 25 6 A-1 0T Q -2 .7
R10
o pt
GND_DIG1
Figure 68
EEPROM
V DIG 33
+3.3 V
C11 2 7
G ND_DIG1
G ND_DIG1
C11 2 8
1 0p /16 V /X7 R
i GM R_ DAT A +
7
6
C11 2 9
i GM R_ DAT A -
4
R48 8
1K
V DIG 33
+3.3 V
R44 7
1 00 R
GND_DIG1
C11 3 0
1 0p /16 V /X7 R
G ND_DIG1
IC3 2
4
G ND_DIG1
12
G ND_DIG1
1
i GM R_ CLK _ uC
7
V DIG 33
+3.3 V
9
C11 3 1
G ND_DIG1
15
R48 9
1K
R49 0
1K
2A
1Y
2Y
E N*
Dou t1+
Din 1
Dou t1Dou t2+
Din 2
Dou t2Dou t3+
Din 3
Dou t3Dou t4+
GND
Din 4
6
Dou t4-
2
3
6
5
10
11
i GM R_ CLK +
i GM R_ CLK i GM R_ REn _ DE +
i GM R_ REn _ DE i GM R_ CSn +
i GM R_ CSn -
14
13
8
VCC
1A
7 4L V C2 G0 4 GW
GND
3
i GM R_ CS_ u C
EN
4
DS9 0 LV 03 1 A
G ND_DIG1
2
1
i GM R_ RE_ u C
5
1 00 n /1 6 V/X 7 R
IC2 8
1 00 n /1 6 V/X 7 R
16
VCC
DIN
ROUT DO/RI+
DO/RIDE
RE
Vcc
1
5
i GM R_ INDE X_ u C
DS9 2 LV 01 0
GND
2
3
i GM R_ DI_u C
i GM R_ ROUT _u C
8
1 00 n /1 6 V/X 7 R
IC2 6
G ND_DIG1
GND_DIG1 G ND_DIG1
Figure 69
GMR SSC Interface
U ni t t e mp e ra t ur e s e ns o r ( Am b ie n t)
P os i ti o n: bo t to m o f L o gi c B o ar d
T em p = 10 m V/ ° C + 5 0 0m V
T em p @ -4 0 C: +1 0 0m V
T em p @ +1 2 5C : + 1 ,7 5 0V
V ANA5 0
+5.0 V
C1211
100n/50V/X7R
IC5 4
L PF : - 3 dB @ 3 2H z
1
V CC
R48 7
V ou t
2
G ND
3
T em p_ B oa rd
2 70 K
L M5 0 CIM3
C12 1 2
2 2n /5 0V /X7 R
G ND_A NA1
Figure 70
Temperature Sense of the Logic Board
Application Note
66
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
K L_ 3 0
+12 .0 V
G ND_A NA1
GND_DIG1
V DC
FLT Wn
T EM P_ HP2 _ W
FLT V n
T EM P_ HP2 _ V
FLT Un
FLT n
1
3
5
7
9
11
13
15
17
19
21
23
K1
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
10
12
14
16
18
20
22
24
K L_ 3 0
+12 .0 V
G ND_DIG1
T EM P_ HP2 _ U
RST _ INn
P WM WT
P WM WB
P WM VT
P WM VB
P WM UT
P WM UB
T W-1 2-0 6-L -D-4 7 5-S M-A
Figure 71
Connector to the Driver Board
4.13.2
Assembly Drawing
Figure 72
Assembly Drawing of the Logic Board (Top)
Application Note
67
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Figure 73
Assembly Drawing of the Logic Board (Bottom)
For detail information use the zoom function of your PDF viewer to zoom into the drawings on Figure 72 and
Figure 73.
4.13.3
Layout
Layout of the Logic Board is shown on Figure 74 (Top Layer), on Figure 75 (Layer-2), on Figure 76 (Layer-3), on
Figure 77 (Layer-4), on Figure 78 (Layer-5) and on Figure 79 (Bottom Layer).
Application Note
68
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Figure 74
Logic Board - Top Layer
Figure 75
Logic Board - Layer-2
Application Note
69
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Figure 76
Logic Board - Layer-3
Figure 77
Logic Board - Layer-4
Application Note
70
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Figure 78
Logic Board - Layer-5
Figure 79
Logic Board - Bottom Layer
Application Note
71
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
4.13.4
Bill of Materials
Table 8
Bill of Materials for Logic Board for Hybrid Kit for HybridPACK™1
Reference
Value / Device
Package
C29,C64,C68,C70,C71,C106,C107,C109,C11 100n/16V/X7R
1,C112,C113,C114,C115,C123,C148,C149,C
152,C153,C154,C155,C156,C157,C158,C159,
C160,C161,C163,C164,C165,C166,C167,C16
8,C169,C170,C171,C1110,C1210
C0402
C65,C66,C1127,C1129,C1131,C1132,C1133, 100n/16V/X7R
C1160,C1161,C1163,C1164
C0603
C75
4u7/16V/X7R
C1206
C76,C77,C80,C81,C104
10n/16V/X7R
C0402
C78
10uF/10V/X7R
C1206
C79,C82
4u7/25V/X7R
C1206
C83,C84
20pF/50V/COG
C0402
C85,C1151,C1153
100n/50V/X7R
C0603
C86,C1135,C1136,C1154,C1155
22u/16V/X7R/F_1463575
C1210
C92
220nF/100V/C3216X7R2A2 C1206
24KT5
C93,C1152
100uF_35V_MAL21409700 C1010_CAP_Pin1_Plus
1E3
C105,C108
22uF/6.3V/X7R
C1206
C110
4.7n/50V/X7R
C0603
C143,C1111
22uF/16V/X7R
C1210
C144
100n/25V/X7R
C0603
C145,C146,C147
47n/16V/X7R
C0402
C150,C151,C1157,C1158
10u/10V/X7R
C1206
C172,C173,C176,C178,C180,C183,C184,C18 1n/50V/X7R
7,C1169,C1170,C1171,C1173,C1174,C1175,
C1176,C1177,C1178,C1179,C1180,C1183,C1
184,C1185,C1189,C1190,C1191,C1192,C119
3,C1194,C1195,C1196,C1197
C0402
C174,C179,C182
100p/50V/X7R
C0402
C191,C194,C196
6800p/10V/C0G
C0603
C1040,C1041,C1042,C1043,C1044,C1045,C1 10p/50V/X7R
147,C1148,C1149
C0603
C1064,C1065,C1067
3300p/10V/C0G
C0603
C1112,C1167
100n/50V/X7R/C0805F104
K5
C0805
C1128,C1130
10p/16V/X7R
C0603
C1142
4u7/10V/X7R
C1210
Application Note
72
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Table 8
Bill of Materials for (cont’d)Logic Board for Hybrid Kit for HybridPACK™1
Reference
Value / Device
Package
C1144,C1146
4u7/10V/X7R/F_9402195
C1206
C1145
1u/25V/X7R/F_1637035
C0603
C1150
680n/50V/F_1414702
C1206
C1156
220n/25V/X7R/F_1414626
C0603
C1159
1n/16V/X7R
C0402
C1166
4.7u/50V/X7R/C1210F475K C1210
5
C1172,C1181,C1182,C1187,C1188,C1201,C1 1n/50V/X7R_opt
202,C1203,C1204,C1205,C1206,C1207,C120
8,C1209
C0402
C1211
100n/50V/X7R
C0805
C1212
22n/50V/X7R
C0603
R10,R103,R105,R107,R109,R110,R176,R181 Opt
,R185,R192,R194,R202,R203,R208,R477,R4
80,R481,C1213,C1214,C1215,C1216,C1217
R0603
D1
MBRS340T3
SMC
D2
BZV55/C13
SOD80C_Pin1_Cathode
D3
1SMB30AT3
SMB
D4
LED_LSM676-MQ
Vishay_TLMK2300
D5,D6
SS12_1A_If_20V_Vr
DO214AC_SMA_Pin1_Cathode
D7,D8,D9
BAT54-04W
SOT323
FL1
B82789C0104N001
EPCOS_B82789C0
IC1
AT25256A-10TQ-2.7
TSSOP8
IC2
74ALVC164245DGG
TSSOP48
IC4,IC31
LT1639HS
SO14
IC6
LMH6672
SO8
IC8
AD2S1200YST
LQFP44_P0_8
IC13
TLE7368E
SO36-38
IC16
EH2645ETTTS-20.000M
Ecliptek_EH2645
IC17
TLE6250GV33
SO8
IC23
MAX6369KA-T
SOT23-8
IC24
SAK-TC1767-256F133HL
LQFP176_p0_50
IC25
TLE4266GSV10
SOT223
IC26
DS92LV010
SO8
IC28,IC30
74LVC2G04GW
SOT363
IC29
74LVCH16T245DL
SSOP48
IC32
DS90LV031A
SO16-1
IC33
AM26C32QD
SO16-1
IC52
MAX3232EIPWRQ1
TSSOP16
Application Note
73
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Table 8
Bill of Materials for (cont’d)Logic Board for Hybrid Kit for HybridPACK™1
Reference
Value / Device
Package
IC53
MAX6143AASA50
SO8
IC54
LM50CIM3
SOT23
J1
Jumper
Jumper_2way
K1
TW-12-06-L-D-475-SM-A
Samtec_TW-12-06-L-D-475-SMA
K2
Harwin M80-5125042P
Harwin_M80-5125042P
K3-OCDS
HEADER 8X2
tyco_1761686-6
L1,L8,L9,L10,L11,L12
MURATA_BLM21PG221SN L0805
L3
WE_7447709470
WE-PD_744770
L5
MURATA_BLM21P221SN
L0805
L6,L7
B82422A1103K
L1210
Q2
BDP949
SOT223
Q4
IPD90P03P4L-04
TO252-3
Q6
BCR183S
SOT363
R1,R2,R3,R4,R5,R6,R7,R8,R9,R71,R73,R173 10K
,R174,R177,R186,R195,R471,R473,R474,R4
75,R476
R0402
R74,R75,R76,R77,R78,R79,R80,R88,R92,R9
5,R98,R100,R134,R135,R161,R162,R163,R1
64,R165,R166,R167,R168,R180,R187,R197,
R234,R238,R240,R456
1K
R0402
R90,R93,R96,R99
15K
R0402
R101,R128,R169
10K
R0603
R102,R104,R106,R108,R478,R479,R482,R49 0R
7
R0603
R113
SMK-R000 / Isabellenhuette R1206
R131,R132
60R
R0603
R133
5K1
R0402
R149,R154
Opt
R0402
R150,R151,R153
4K7
R0402
R155,R156,R158,R160
2K4/0.1%
R0603
R157
390/0.1%
R0603
R159
3K3/0.1%
R0603
R170,R224,R498
0R_opt
R0603
R171
4K7
R0603
R172
220R
R0603
R175,R184,R191,R198,R205
68K
R0402
R178,R179,R188,R189,R196,R199
51K
R0402
R182,R193,R200
91K
R0402
R183,R190,R201,R237,R239,R241
2K
R0402
Application Note
74
V2.5, 2012-03-30
Hybrid Kit for HybridPACK™1
Evaluation Kit for Applications with HybridPACK™1 Module
Logic Board for Hybrid Kit for HybridPACK™1
Table 8
Bill of Materials for (cont’d)Logic Board for Hybrid Kit for HybridPACK™1
Reference
Value / Device
Package
R214,R217,R223,R228,R230,R235
6K8
R0402
R215,R218,R472
3K3
R0402
R229
0R
R0402
R429,R430,R431,R447
100R
R0603
R483,R484,R485
5K_pot_0,25W_20%_Bourn Bourns_3314J
s_3314J_opt
R486
0R / 0.1%
R0402
R487
270K
R0603
R488,R489,R490,R494,R495,R496
1K
R0603
R491,R492,R493
2K7
R0603
R499,R500,R501,R502,R503,R504,R505,R50 100k
6
R0402
SW1
Tyco_1-1571983-1
Tyco_1-1571983-1
SW2
SW DIP-4/SM
SO8
TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP9
Testpad_SMD_Ettinger
Ettinger_12_18_815_testpad
U1
HCM49 8.192MABJ-UT
Citizen_HCM49
Application Note
75
V2.5, 2012-03-30
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG