EMI4184 Common Mode Filter with ESD Protection Functional Description The EMI4184 is an integrated common mode filter providing both ESD protection and EMI filtering for high speed digital serial interfaces such as HDMI or MIPI D-PHY. The EMI4184 provides protection for two differential data line pairs in a small RoHS-compliant UDFN20 package. http://onsemi.com MARKING DIAGRAMS Features U4MG G • Highly Integrated Common Mode Filter (CMF) with ESD Protection • • • • • • provides protection and EMI reduction for systems using High Speed Serial Data Lines with cost and space savings over discrete solutions Large Differential Mode Bandwidth with Cutoff Frequency > 2 GHz High Common Mode Stop Band Attenuation: >25 dB at 700 MHz, >30 dB at 800 MHz Provides ESD Protection to IEC61000-4-2 Level 4, ±15 kV Contact Discharge Low Channel Input Capacitance Provides Superior Impedance Matching Performance Low Profile Package with Small Footprint in UDFN20 2 x 5 mm Pb−Free Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant UDFN20 CASE 517CL U4 = Specific Device Code M = Date Code G = Pb−Free Package (*Note: Microdot may be in either location) PIN CONNECTIONS Applications • HDMI/DVI Display in Mobile Phones • MIPI D-PHY (CSI-2, DSI, etc) in Mobile Phones and Digital Still Cameras ORDERING INFORMATION March, 2013 − Rev. 0 Package Shipping† EMI4184MUTAG UDFN20 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Figure 1. EMI4184 Electrical Schematic © Semiconductor Components Industries, LLC, 2013 Device 1 Publication Order Number: EMI4184/D EMI4184 PIN FUNCTION DESCRIPTION Pin Name Pin No. Type In_1+ 1 I/O CMF Channel 1+ to Connector Description In_1− 2 I/O CMF Channel 1− to Connector Out_1+ 20 I/O CMF Channel 1+ to ASIC Out_1− 19 I/O CMF Channel 1− to ASIC In_2+ 4 I/O CMF Channel 2+ to Connector In_2− 5 I/O CMF Channel 2− to Connector Out_2+ 17 I/O CMF Channel 2+ to ASIC Out_2− 16 I/O CMF Channel 2− to ASIC In_3+ 6 I/O CMF Channel 3+ to Connector In_3− 7 I/O CMF Channel 3− to Connector Out_3+ 15 I/O CMF Channel 3+ to ASIC Out_3− 14 I/O CMF Channel 3− to ASIC In_4+ 9 I/O CMF Channel 4+ to Connector In_4− 10 I/O CMF Channel 4− to Connector Out_4+ 12 I/O CMF Channel 4+ to ASIC Out_4− 11 I/O CMF Channel 4− to ASIC GND1 3, 18 GND Ground GND2 8, 13 GND Ground ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Parameter Symbol Value Unit Operating Temperature Range TOP −40 to +85 °C Storage Temperature Range TSTG −65 to +150 °C ESD Discharge IEC61000−4−2 Contact Discharge VPP ±15 kV TL 260 °C ILINE 100 mA Maximum Lead Temperature for Soldering Purposes (1/8” from Case for 10 seconds) DC Current per Line Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 EMI4184 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Test Conditions ILEAK Channel Leakage Current TA = 25°C, VIN = 5 V, GND = 0 V VF Channel Negative Voltage TA = 25°C, IF = 10 mA CIN Channel Input Capacitance to Ground (Pins 1, 2, 4, 5 to Pins 3, 8 and 6, 7, 9, 10 to Pins 8, 13) TA = 25°C, At 1 MHz, GND = 0 V, VIN = 1.65 V RCH Channel Resistance (Pins 1−20, 2−19, 4−17, 5−16, 6−15, 7−14, 9−12, 10−11) f3dB Differential Mode Cut−off Frequency Fatten VESD Min Typ 0.1 0.8 Max Unit 1.0 mA 1.5 V 1.3 pF 8.0 W 50 W Source and Load Termination 2.0 GHz Common Mode Stop Band Attenuation @ 800 MHz 30 dB ESD Protection − Peak Discharge Voltage at any channel input, in system: Contact discharge per IEC61000−4−2 standard TA = 25°C (Notes 1 and 2) Pins 1, 2, 4, 5, 6, 7, 9, 10 TLP Clamping Voltage (See Figure 12) Forward IPP = 8 A Forward IPP = 16 A Forward IPP = −8 A Forward IPP = −16 A 12 18 −6 −12 RDYN Dynamic Resistance Positive Transients Negative Transients TA = 25°C, IPP = 1 A, tP = 8/20 ms Any I/O pin to Ground; Notes 1 and 3 1.36 0.6 VRWM Reverse Working Voltage (Note 3) Breakdown Voltage IT = 1 mA; (Note 4) VCL VBR kV ±15 5.6 V V V V 5.0 V 9.0 V 1. Standard IEC61000−4−2 with CDischarge = 150 pF, RDischarge = 330, GND grounded. 2. These measurements performed with no external capacitor. 3. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at pulse test current IT. http://onsemi.com 3 EMI4184 TYPICAL CHARACTERISTICS 0 0 −1 −5 −2 −10 dB (SCC21) dB (SCC21) −3 −4 −5 −6 −15 −20 −25 −7 −30 −8 −35 −9 −40 1E5 1E6 1E7 1E8 1E9 6E9 1E5 Frequency, Hz Figure 2. Differential Mode Attenuation vs. Frequency (Zdiff = 100 W) 1E6 1E7 1E8 Frequency, Hz 1E9 Figure 3. Common Mode Attenuation vs. Frequency (Zcomm = 50 W) 0 −5 −10 dB(SDD22) dB(SDD11) −15 −20 −25 −30 −35 −40 1E5 1E6 1E7 1E8 Frequency, Hz 1E9 6E9 Figure 4. Differential Return Loss vs. Frequency (Zdiff=100 W) Figure 5. Differential Inter−Lane Cross−Coupling Figure 6. Common Mode Inter−Lane Cross−Coupling http://onsemi.com 4 6E9 EMI4184 MIPI DSI (D−PHY) Host MIPI DSI (D−PHY) Client EMI4184 Evaluation Board Figure 7. MIPI D−PHY LP Mode Test Setup Figure 8. EMI4184 MIPI D−PHY LP Mode Measured Results http://onsemi.com 5 EMI4184 EMI4184 Figure 9. EMI4184 Eye Diagram Test Setup Figure 10. EMI4184 Measured Eye Diagram @ 3.4Gbps (EVB through on left, EVB with EMI4184 on right) http://onsemi.com 6 EMI4184 TRANSMISSION LINE PULSE (TLP) MEASUREMENTS Transmission Line Pulse (TLP) provides current versus voltage (I-V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 11. TLP I-V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10 s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 12 where an 8 kV IEC61000-4-2 current waveform is compared with TLP current pulses at 8 and 16 A. A TLP curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. Typical TLP I-V curves for the EMI4184 are shown in Figure 13. L SW 50 W Coax Cable Attenuator 50 W Coax Cable ÷ IM VM 10 MW VC DUT Oscilloscope Figure 11. Simplified Schematic of a Typical TLP System Figure 12. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms Figure 13. Positive and Negative TLP Waveforms http://onsemi.com 7 EMI4184 ESD VOLTAGE CLAMPING For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor Application Notes AND8307/D and AND8308/D. IEC61000−4−2 Waveform IEC61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Oscilloscope TVS 50 W Cable 50 W Figure 14. Diagram of ESD Test Setup 100 % OF PEAK PULSE CURRENT ESD Gun PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 15. 8 x 20 ms Pulse Waveform http://onsemi.com 8 80 EMI4184 Figure 16. ESD Clamping Voltage +8 kV per IEC6100−4−2 (external to internal pin) Figure 17. ESD Clamping Voltage −8 kV per IEC6100−4−2 (external to internal pin) http://onsemi.com 9 EMI4184 PACKAGE DIMENSIONS UDFN20 5x2, 0.5P CASE 517CL ISSUE O A B D PIN ONE REFERENCE ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2X 0.10 C 2X 0.10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 E DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉÉ ÉÉ ÉÉÉ ÇÇÇ ÉÉ ÇÇ EXPOSED Cu TOP VIEW DETAIL B 0.05 C L A (A3) MOLD CMPD A3 A1 DETAIL B ALTERNATE CONSTRUCTIONS 0.05 C NOTE 4 A1 SIDE VIEW C SEATING PLANE RECOMMENDED MOUNTING FOOTPRINT* DETAIL A 1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 5.00 BSC 2.00 BSC 0.50 BSC 0.75 0.85 0.05 0.15 DIM A A1 A3 b D E e L L1 10 16X 17X 16X L PACKAGE OUTLINE 0.32 1.04 0.10 MIN 20 e e/2 BOTTOM VIEW 2.30 11 18X b 0.10 M C A B 0.05 M C 1 NOTE 3 0.44 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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