EMI7112 Product Preview EMI Filter with ESD Protection Product Description www.onsemi.com The EMI7112 is an L−C EMI filter array with ESD protection that integrates two Pi−filters (C−L−C) to suppress EMI/RFI Noise. EMI7112 includes ESD protection diodes on all input/output pins, and provides a very high level of protection for sensitive electronic components against possible electrostatic discharge (ESD). The ESD diodes connected to the filter ports safely dissipate ESD strikes of ±30 kV, which is beyond the maximum requirement of the IEC61000−4−2 international standard. WLCSP5 FC SUFFIX CASE 567KK BLOCK DIAGRAM Features • • • • • Two Channels of EMI Filtering ±30 kV ESD Protection (IEC 61000−4−2, Contact Discharge) ±30 kV ESD Protection (IEC 61000−4−2, Air Discharge) Greater than 45 dB of Attenuation at 900 MHz These Devices are Pb−Free and are RoHS Compliant A1 A3 FILTER #1 GND B2 C1 Applications C3 • Mobile Phones FILTER #2 GND B2 MAXIMUM RATINGS (TA = 25°C) Rating Symbol Value Unit ESD Discharge IEC61000−4−2 Contact Discharge Air Discharge Vpp kV RMS Current per Line ILine 350 mA Operating Temperature Range TJ −40 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature (10 second duration) TL 260 °C 30 30 MARKING DIAGRAM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 7AM 7A M = Specific Device Code = Date Code ORDERING INFORMATION Device Package Shipping† EMI7112FCTAG WLCSP5 (Pb−Free) 5000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2015 February, 2015 − Rev. P2 1 Publication Order Number: EMI7112/D EMI7112 PACKAGE/PINOUT DIAGRAMS Pin Name A1 Filter #1 Filter #1 Input/Output A3 Filter #1 Filter #1 Input/Output C1 Filter #2 Filter #2 Input/Output C3 Filter #2 Filter #2 Input/Output A B2 GND Device Ground B Top View (Bumps Down View) Orientation Marking Bottom View (Bumps Up View) C Orientation Marking + A1 7A B2 C1 + 1 2 3 C3 Description A3 Table 1. PIN DESCRIPTIONS WLCSP5 Package Table 2. ELECTRICAL OPERATING CHARACTERISTICS (TA = 25°C unless otherwise noted) Parameter Symbol VRWM Test Conditions Min Working Voltage VBR Breakdown Voltage ILEAK Channel Leakage Current RCH Channel Resistance (Pins A1 – A3, C1 – C3) Typ Max 3.0 IT = 1 mA; (Note 4) V 6.0 V 400 nA 0.35 0.8 W 250 315 VIN = 3.0 V, GND = 0 V Ct Line Capacitance VR = 0 V, f = 1 MHz f3dB Cutoff Frequency 50 W Source and Load Termination 20 MHz @ 700 MHz @ 900 MHz 40 47 dB Fatten Stop Band Attenuation VESD Insystem ESD Withstand Voltage a) Contact discharge per IEC 6100042 standard, Level 4 (External Pins) b) Contact discharge per IEC 6100042 standard, Level 1 (Internal Pins) VCL TLP Clamping Voltage 185 Unit (Notes 1 and 2) pF kV ±30 ±30 Forward IPP = 8 A Forward IPP = 16 A Forward IPP = ±8 A Forward IPP = ±16 A 9.77 11.51 −9.66 −11.67 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Standard IEC61000−4−2 with CDischarge = 150 pF, RDischarge = 330, GND grounded. 2. These measurements performed with no external capacitor. 3. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at pulse test current IT. www.onsemi.com 2 EMI7112 PERFORMANCE INFORMATION Typical Filter Performance (nominal conditions unless specified otherwise, 50 W Environment) 0 −10 −10 CROSSTALK (dB) 0 S21 (dB) −20 −30 −40 −30 −40 −50 −50 −60 1.E+07 −20 1.E+08 1.E+09 1.E+10 −60 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 FREQUENCY (Hz) FREQUENCY (Hz) Figure 1. Typical Insertion Loss Figure 2. Typical Channel to Channel Crosstalk www.onsemi.com 3 EMI7112 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger www.onsemi.com 4 25 −25 20 −20 TLP CURRENT (A) TLP CURRENT (A) EMI7112 15 10 −15 −10 −5 5 0 0 0 NOTE: 2 4 6 8 10 12 14 0 −2 −4 −6 −8 −10 −12 VC, VOLTAGE (V) VC, VOLTAGE (V) Figure 5. Positive TLP I−V Curve Figure 6. Negative TLP I−V Curve −14 TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description below for more information. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 7. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 8 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 7. Simplified Schematic of a Typical TLP System Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 5 EMI7112 PACKAGE DIMENSIONS WLCSP5, 1.26x0.89 CASE 567KK ISSUE O E A È PIN A1 REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. 4. DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER PARALLEL TO DATUM C. B D 0.10 C 2X 0.10 C 2X DIM A A1 A2 b D E e e1 TOP VIEW A2 0.10 C A 0.05 C NOTE 3 A1 C SIDE VIEW MILLIMETERS MIN MAX 0.56 0.72 0.21 0.27 0.38 REF 0.29 0.35 1.26 BSC 0.89 BSC 0.50 BSC 0.435 BSC RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE A1 PACKAGE OUTLINE e/2 5X e b 0.05 C 5X 0.32 e1 0.10 C A B C 0.87 PITCH B A 1 2 3 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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