MC74HC367A D

MC74HC367A
Hex 3-State Noninverting
Buffer with Separate 2-Bit
and 4-Bit Sections
High−Performance Silicon−Gate CMOS
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The MC74HC367A is identical in pinout to the LS367. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device is arranged into 2−bit and 4−bit sections, each having its
own active−low Output Enable. When either of the enables is high, the
affected buffer outputs are placed into high−impedance states. The
HC367A has noninverting outputs.
16
SOIC−16
D SUFFIX
CASE 751B
16
1
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
These are Pb−Free Devices
A0
2
3
4
5
HC367AG
AWLYWW
1
16
Features
•
•
•
•
•
•
MARKING
DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
16
1
HC
367A
ALYWG
G
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
Y0
PIN ASSIGNMENT
A1
A2
A3
A4
A5
OUTPUT ENABLE 1
6
7
10
9
12
11
14
13
OUTPUT
ENABLE 1
A0
Y1
Y2
Y3
Y4
Y5
15
3
14
A1
4
13
Y5
Y1
5
12
A4
A2
6
11
Y4
Y2
7
10
A3
GND
8
9
Y3
16
FUNCTION TABLE
1
OUTPUT ENABLE 2 15
2
Y0
VCC
OUTPUT
ENABLE 2
A5
1
Inputs
PIN 16 = VCC
PIN 8 = GND
Enable 1,
Enable 2
Figure 1. Logic Diagram
L
L
H
Output
A
Y
L
H
X
L
H
Z
X = don’t care
Z = high impedance
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 4
1
Publication Order Number:
MC74HC367A/D
MC74HC367A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
−0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
−0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
−65 to + 150
°C
SOIC Package
TSSOP Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 2)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
−55
+125
°C
0
0
0
0
1000
600
500
400
ns
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC367A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
− 55 to
25°C
v 85°C
v 125°C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = VCC − 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Vin = VIH
VOL
Maximum Low−Level Output
Voltage
|Iout| v 3.6 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIL
|Iout| v 20 mA
Vin = VIL
|Iout| v 3.6 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4
40
160
mA
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3
MC74HC367A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Parameter
Symbol
VCC
V
− 55 to
25°C
v 85°C
v 125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
120
60
24
20
150
75
30
26
180
90
36
31
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
175
90
35
30
220
110
44
37
265
135
53
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
3.0
4.5
6.0
190
95
38
32
240
120
48
21
285
150
57
48
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Cin
Maximum Input Capacitance
−
10
10
10
pF
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
−
15
15
15
pF
Typical @ 25°C, VCC = 5.0 V
CPD
60
Power Dissipation Capacitance (Per Buffer)
pF
SWITCHING WAVEFORMS
VCC
tr
tf
OUTPUT ENABLE
VCC
90%
50%
10%
INPUT A
tPLH
GND
tPZL
GND
tPHL
OUTPUT Y
90%
50%
10%
OUTPUT Y
50%
tPHZ
50%
Figure 2.
Figure 3.
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4
10%
VOL
90%
VOH
HIGH
IMPEDANCE
tTHL
tTLH
HIGH
IMPEDANCE
50%
tPZH
OUTPUT Y
tPLZ
MC74HC367A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
TO OTHER
BUFFERS
ONE OF 6
BUFFERS
VCC
Y
A
OUTPUT ENABLE
Figure 6. Logic Detail
ORDERING INFORMATION
Package
Shipping†
MC74HC367ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC367ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HC367ADTG
TSSOP−16
(Pb−Free)
96 Units / Tube
MC74HC367ADTR2G
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC74HC367A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
S
V
S
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
S
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
4.90
5.10 0.193 0.200
B
4.30
4.50 0.169 0.177
C
−−−
1.20
−−− 0.047
D
0.05
0.15 0.002 0.006
F
0.50
0.75 0.020 0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28 0.007
0.011
−W−
J
0.09
0.20 0.004 0.008
J1
0.09
0.16 0.004 0.006
K
0.19
0.30 0.007 0.012
K1
0.19
0.25 0.007 0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC74HC367A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
DIM
A
B
C
D
F
G
J
K
M
P
R
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HC367A/D