MC74LVX8051 D

MC74LVX8051
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVX8051 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to GND).
The LVX8051 is similar in pinout to the high−speed HC4051A and
the metal−gate MC14051B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pull−up resistors they are compatible with
LSTTL outputs.
This device has been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
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SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
VCC
X2
X1
X0
X3
A
B
C
16
15
14
13
12
11
10
9
6
7
8
Features
1
2
3
4
5
•
•
•
•
•
•
X4
X6
X
X7
X5 Enable NC GND
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC − GND) = 2.5 to 6.0 V
Digital (Control) Power Supply Range (VCC − GND) = 2.5 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: LVX8051 − 184 FETs or 46 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS
16
LVX8051G
AWLYWW
1
SOIC−16
16
LVX
8051
ALYWG
G
1
TSSOP−16
LVX8051
A
WL, L
Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 6
1
Publication Order Number:
MC74LVX8051/D
MC74LVX8051
13
X0
14
X1
15
X2
ANALOG
12
INPUTS/ X3
OUTPUTS X4 1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
FUNCTION TABLE − MC74LVX8051
Control Inputs
3
MULTIPLEXER/
DEMULTIPLEXER
COMMON
X
OUTPUT/
INPUT
PIN 16 = VCC
PIN 8 = GND
Enable
C
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
ON Channels
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
LOGIC DIAGRAM
MC74LVX8051
Single−Pole, 8−Position Plus Common Off
MAXIMUM RATINGS
Symbol
Parameter
Unit
–0.5 to +7.0
V
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage
−0.5 to VCC + 0.5
V
Vin
Digital Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
± 20
mA
500
450
mW
–65 to +150
_C
260
_C
I
(Referenced to GND)
Value
DC Current, Into or Out of Any Pin
PD
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
Tstg
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
(Referenced to GND)
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage
Vin
Digital Input Voltage (Referenced to GND)
VIO*
Static or Dynamic Voltage Across Switch
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time (Channel Select or Enable Inputs)
Max
Unit
2.5
6.0
V
0.0
VCC
V
GND
VCC
V
1.2
V
– 55
+ 85
_C
0
0
100
20
ns/V
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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2
MC74LVX8051
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec
2.5
3.0
4.5
5.5
1.50
2.10
3.15
3.85
1.50
2.10
3.15
3.85
1.50
2.10
3.15
3.85
V
VIL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec
2.5
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
Iin
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
VIS = VCC or GND; VIO = 0 V
5.5
4.0
40
160
mA
DC ELECTRICAL CHARACTERISTICS (Analog Section)
Symbol
Ron
Parameter
Maximum “ON” Resistance
Guaranteed Limit
VCC
V
–55 to 25_C
v85_C
v125_C
Unit
Vin = VIL or VIH
VIS = VCC to GND
|IS| v 10.0 mA (Figures 1, 2)
3.0
4.5
5.5
40
30
25
45
32
28
50
37
30
W
Vin = VIL or VIH
VIS = VCC or GND (Endpoints)
|IS| v 10.0 mA (Figures 1, 2)
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
Test Conditions
DRon
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or VIH
VIS = 1/2 (VCC − GND)
|IS| v 10.0 mA
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
W
Ioff
Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 3)
5.5
0.1
0.5
1.0
mA
Maximum Off−Channel
Leakage Current,
Common Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 4)
5.5
0.2
2.0
4.0
Maximum On−Channel
Leakage Current,
Channel−to−Channel
Vin = VIL or VIH;
Switch−to−Switch =
VCC or GND; (Figure 5)
5.5
0.2
2.0
4.0
Ion
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3
mA
MC74LVX8051
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
−55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
2.5
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.5
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.5
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.5
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
ns
Cin
Maximum Input Capacitance, Channel−Select or Enable Inputs
10
10
10
pF
CI/O
Maximum Capacitance
Analog I/O
35
35
35
pF
Common O/I
130
130
130
Feedthrough
1.0
1.0
1.0
(All Switches Off)
Typical @ 25°C, VCC = 5.0 V
CPD
45
Power Dissipation Capacitance (Figure 13)*
pF
* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
BW
−
Parameter
Condition
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 6)
fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain
0dBm at VOS; Increase fin Frequency Until dB
Meter Reads −3 dB;
RL = 50 W, CL = 10 pF
Off−Channel Feedthrough Isolation
(Figure 7)
fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm
at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
−
Feedthrough Noise. Channel−Select
Input to Common I/O (Figure 8)
Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL
at Setup so that IS = 0 A;
Enable = GND
RL = 600 W, CL = 50 pF
RL = 10 kW, CL = 10 pF
THD
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kW, CL = 50 pF
THD = THDmeasured − THDsource
VIS = 2.0 VPP sine wave
VIS = 4.0 VPP sine wave
VIS = 5.0 VPP sine wave
*Limits not tested. Determined by design and verified by qualification.
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4
VCC
V
Limit*
25°C
Unit
MHz
3.0
4.5
5.5
80
80
80
3.0
4.5
5.5
−50
−50
−50
3.0
4.5
5.5
−37
−37
−37
3.0
4.5
5.5
25
105
135
3.0
4.5
5.5
35
145
190
dB
mVPP
%
3.0
4.5
5.5
0.10
0.08
0.05
MC74LVX8051
Ron , ON RESISTANCE (OHMS)
40
35
30
125°C
85°C
25°C
-55°C
25
20
15
10
5
00
1.0
2.0
3.0
4.0
VIN, INPUT VOLTAGE (VOLTS)
Figure 1a. Typical On Resistance, VCC = 3.0 V
25
25
Ron , ON RESISTANCE (OHMS)
Ron , ON RESISTANCE (OHMS)
30
125°C
85°C
25°C
-55°C
20
15
10
5
0
0
1.0
2.0
3.0
4.0
20
125°C
85°C
15
25°C
-55°C
10
5
0
5.0
0
1.0
2.0
VIN, INPUT VOLTAGE (VOLTS)
Figure 1b. Typical On Resistance, VCC = 4.5 V
4.0
5.0
Figure 1c. Typical On Resistance, VCC = 5.5 V
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
-
3.0
VIN, INPUT VOLTAGE (VOLTS)
MINI COMPUTER
DC ANALYZER
+
VCC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 2. On Resistance Test Set−Up
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5
6.0
MC74LVX8051
VCC
VCC
VCC
16
GND
ANALOG I/O
OFF
A
VCC
VIH
OFF
VCC
COMMON O/I
OFF
NC
OFF
VIH
6
8
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
VCC
VCC
VCC
16
A
fin
dB
METER
ON
N/C
COMMON O/I
OFF
VOS
16
0.1mF
ON
VCC
COMMON O/I
6
8
GND
VCC
16
GND
RL
CL*
ANALOG I/O
VIL
6
6
8
8
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
VCC
VIS
VCC
VOS
16
0.1mF
fin
dB
METER
OFF
RL
Figure 6. Maximum On Channel Bandwidth,
Test Set−Up
CL*
16
RL
COMMON O/I
ON/OFF
ANALOG I/O
RL
OFF/ON
RL
RL
6
6
8
VIL or VIH
VCC
GND
CHANNEL SELECT
Vin ≤ 1 MHz
tr = tf = 3 ns
8
TEST
POINT
CL*
VCC
11
CHANNEL SELECT
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Off Channel Feedthrough Isolation,
Test Set−Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set−Up
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MC74LVX8051
VCC
VCC
16
VCC
CHANNEL
SELECT
ON/OFF
50%
COMMON O/I
ANALOG I/O
OFF/ON
GND
tPLH
TEST
POINT
CL*
tPHL
6
ANALOG
OUT
50%
8
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
VCC
16
VCC
ANALOG
IN
COMMON O/I
ANALOG I/O
ON
50%
TEST
POINT
CL*
GND
tPLH
tPHL
ANALOG
OUT
6
8
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
tf
tr
90%
50%
10%
ENABLE
tPZL
ANALOG
OUT
tPLZ
1
VCC
GND
VCC
VCC
HIGH
IMPEDANCE
10%
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
2
16
1
TEST
POINT
ON/OFF
CL*
VOL
tPHZ
ENABLE
90%
1kW
ANALOG I/O
2
50%
tPZH
ANALOG
OUT
Figure 10b. Propagation Delay, Test Set−Up
Analog In to Analog Out
VOH
50%
6
8
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set−Up
Enable to Analog Out
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MC74LVX8051
VCC
VIS
A
VCC
16
RL
fin
16
VOS
ON/OFF
ON
COMMON O/I
NC
ANALOG I/O
0.1mF
OFF/ON
OFF
RL
RL
CL*
RL
CL*
VCC
6
6
8
8
CHANNEL SELECT
11
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 13. Power Dissipation Capacitance,
Test Set−Up
0
VIS
VCC
0.1mF
fin
ON
CL*
-20
TO
DISTORTION
METER
-30
-40
dB
RL
FUNDAMENTAL FREQUENCY
-10
VOS
16
-50
DEVICE
-60
6
SOURCE
-70
8
-80
-90
*Includes all probe and jig capacitance
- 100
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set−Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not
a requirement. The only constraints on the power supplies
are that:
VCC − GND = 2 to 6 volts
When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external Germanium
or Schottky diodes (Dx) are recommended as shown in
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
VCC = +5V = logic high
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltage VCC. The positive peak analog voltage
should not exceed VCC. Similarly, the negative peak analog
voltage should not go below GND. In this example, the
difference between VCC and GND is five volts. Therefore,
using the configuration of Figure 15, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
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MC74LVX8051
VCC
+5V
16
+5V
ANALOG
SIGNAL
0V
ON
6
8
Dx
+5V
ANALOG
SIGNAL
VCC
16
Dx
Dx
GND
GND
8
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
+5V
16
+5V
ANALOG
SIGNAL
GND
ON/OFF
6
8
Dx
ON/OFF
0V
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
11
10
9
VCC
ANALOG
SIGNAL
+5V
*
R
R
11
10
9
+5V
+5V
GND
GND
16
ANALOG
SIGNAL
ON/OFF
+5V
ANALOG
SIGNAL
R
GND
+5V
6
LSTTL/NMOS
CIRCUITRY
8
* 2K ≤ R ≤ 10K
11
10
9
LSTTL/NMOS
CIRCUITRY
VHCT1GT50
BUFFERS
a. Using Pull−Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
A
11
13
LEVEL
SHIFTER
14
B
10
15
LEVEL
SHIFTER
12
C
9
1
LEVEL
SHIFTER
5
ENABLE
6
2
LEVEL
SHIFTER
4
3
Figure 18. Function Diagram, LVX8051
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9
X0
X1
X2
X3
X4
X5
X6
X7
X
MC74LVX8051
ORDERING INFORMATION
Package
Shipping†
MC74LVX8051DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVX8051DTG
TSSOP−16
(Pb−Free)
96 Units / Rail
MC74LVX8051DTR2G
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
MC74LVX8051
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
0.25 (0.010)
8
1
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74LVX8051
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
DIM
A
B
C
D
F
G
J
K
M
P
R
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74LVX8051/D