NLAS5213 D

NLAS5213
1 W RON DPST and Dual SPST
Switches
The NLAS5213A and NLAS5213B are DPST and Dual SPST
devices, respectively. They each consist of 2 single throw switches and
are both designed for audio applications within portable devices. The
NLAS5213A is controlled with a single enable pin while the
NLAS5213B has two independent enables.
Both the NLAS5213A and NLAS5213B operate over a wide VCC
range, 1.65 V to 4.5 V, and maintain a very low RON: 1.3 Max @
VCC = 4.2 V. Each is available in a choice of two packages: US8 and
UDFN8.
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MARKING
DIAGRAM
8
Features
•
•
•
•
•
•
US8
US SUFFIX
CASE 493
8
1
PST and Dual SPST Pinouts
RON: 1.3 Max @ VCC = 4.2 V
VCC Range: 1.65 V to 4.5 V
8 kV Human Body Model ESD on I/O to GND
UDFN8 or US8 Packages Available
These are Pb−Free Devices
XXMG
G
1
8
1
XX
M
G
Typical Applications
• Mobile Phones
• Portable Devices
UDFN8
MU SUFFIX
CASE 517AJ
XXM
G
= Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
APPLICATION DIAGRAM
CODEC
NLAS5213
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 2
1
Publication Order Number:
NLAS5213/D
NLAS5213
NO1
1
8
COM1
NO1
1
8
COM1
IN
2
7
GND
IN1
2
7
GND
N.C.
3
6
VCC
IN2
3
6
VCC
NO 2
4
5
COM2
NO 2
4
5
COM2
NLAS5213A
NLAS5213B
Figure 1. Functional Block Diagram Pinouts (UDFN8)
COM1
1
8
NO1 COM1
1
8
NO1
GND
2
7
IN
GND
2
7
IN1
VCC
3
6
N.C.
VCC
3
6
IN2
COM2
4
5
NO2 COM2
4
5
NO2
NLAS5213B
NLAS5213A
Figure 2. Functional Block Diagram Pinouts (US8)
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2
NLAS5213
NLAS5213A
Pin #
UDFN8
US8
Name
Direction
Description
1
8
NO1
I/O
Normally Open Signal Line of Switch 1
2
7
IN
Input
Control Input
3
6
N.C.
N/A
No Connect
4
5
NO2
I/O
Normally Open Signal Line of Switch 2
5
4
COM2
I/O
Common Signal Line of Switch 2
6
3
VCC
Input
Analog Supply Voltage
7
2
GND
Input
Ground
8
1
COM1
I/O
Common Signal Line of Switch 1
UDFN8
US8
Name
Direction
Description
1
8
NO1
I/O
Normally Open Signal Line of Switch 1
2
7
IN1
Input
Control Input of Switch 1
3
6
IN2
Input
Control Input of Switch 2
4
5
NO2
I/O
Normally Open Signal Line of Switch 2
5
4
COM2
I/O
Common Signal Line of Switch 2
6
3
VCC
Input
Analog Supply Voltage
7
2
GND
Input
Ground
8
1
COM1
I/O
Common Signal Line of Switch 1
NLAS5213B
Pin #
NLAS5213A FUNCTION TABLE
NLAS5213B FUNCTION TABLE
IN
NO1, NO2
IN
NO1, NO2
0
1
OFF
ON
0
1
OFF
ON
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3
NLAS5213
OPERATING CONDITIONS
MAXIMUM RATINGS
Symbol
Pins
Parameter
Value
Positive DC Supply Voltage
Condition
Unit
VCC
VCC
−0.5 to 5.5
V
VIS
NOx, NCx,
COMx
Analog Signal Voltage
−0.5 to VCC + 0.5
V
VIN
IN1, IN2
Control Input Voltage
−0.5 to 5.5
V
ICC
VCC
IIS_CON
NOx, NCx,
COMx
Positive DC Supply Current
Analog Signal Continues Current
±300
Closed Switch
mA
IIS_PK
NOx, NCx,
COMx
Analog Signal Peak Current
±500
10% Duty Cycle
mA
IIN
IN
Control Input Current
±20
mA
−65 to 150
ºC
TSTG
50
Storage Temperature Range
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS*
Symbol
Pins
Parameter
Value
Unit
VCC
VCC
1.65 to 4.5
V
VIS
NOx, NCx,
COMx
Analog Signal Voltage
0 to VCC
V
VIN
IN1, IN2
Control Input Voltage
0 to VCC
V
Operating Temperature Range
−40 to 85
ºC
TA
Positive DC Supply Voltage
Condition
Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable.
Typical values are listed for guidance only and are based on the particularconditions listed for each section, where applicable. These conditions
are valid for all values found in the characteristics tables unless otherwise specified in the test conditions.
ESD PROTECTION
Symbol
ESD
Parameter
Value
Human Body Model
I/O to GND
All Pins
Unit
kV
8.0
4.0
DC ELECTRICAL CHARACTERISTICS
CONTROL INPUT (Typical: T = 25°C, VCC = 3.3 V)
−40°C to +85°C
Symbol
Pins
Parameter
Test Conditions
VCC (V)
Min
Typ
Max
Unit
VIH
OE
Control Input HIGH Voltage
2.7
3.3
4.2
1.4
1.7
2.3
−
−
V
VIL
OE
Control Input LOW Voltage
2.7
3.3
4.2
−
−
0.5
0.5
0.8
V
IIN
OE
Control Input Leakage Current
1.65 − 4.5
−
−
±1.0
A
0 ≤ VIS ≤ VCC
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4
NLAS5213
SUPPLY CURRENT AND LEAKAGE (Typical: T = 25°C, VCC = 3.3 V)
−40°C to +85°C
Symbol
Pins
Parameter
Test Conditions
VCC (V)
Min
Typ
Max
1.65 − 4.5
−
−
1.0
Unit
A
3.6
−
−
10.0
A
ICC
VCC
Quiescent Supply Current
VIS = VCC or GND; ID = 0 A
ICCT
VCC
Increase in ICC per
Control Voltage
VIN = 2.6 V
OFF State Leakage
0 ≤ VIS ≤ VCC
1.65 − 4.5
−
−
±1.0
A
Power OFF Leakage Current
0 ≤ VIS ≤ VCC
0
−
−
±1.0
A
IOZ
IOFF
D+, D−
ON RESISTANCE (Typical: T = 25°C, VCC = 3.3 V)
−40°C to +85°C
VCC (V)
Min
RON
On−Resistance
ION = −100 mA
VIS = 0 to VCC
2.7
3.3
4.2
−
RFLAT
On−Resistance Flatness
ION = −100 mA
VIS = 0 to VCC
2.7
3.3
4.2
−
RON
On−Resistance Matching
ION = −100 mA
VIS = 0 to VCC
2.7
3.3
4.2
−
Symbol
Pins
Parameter
Test Conditions
Typ
Max
Unit
2.0
1.4
1.3
0.32
0.35
0.37
−
0.16
0.16
0.15
−
AC ELECTRICAL CHARACTERISTICS
TIMING/FREQUENCY (Typical: T = 25°C, VCC = 3.3 V, RL = 50 , CL = 5 pF, f = 1 MHz)
−405C to +855C
Symbol
Pins
Parameter
Test Conditions
VCC (V)
Min
Typ
Max
Unit
tON
Closed Turn−ON Time
to Open
1.65 − 4.5
−
20
−
ns
tOFF
Open to Turn−OFF Time
Closed
1.65 − 4.5
−
15
−
ns
1.65 − 4.5
−
496
−
MHz
BW
−3 dB Bandwidth
CL = 5 pF
ISOLATION (Typical: T = 25°C, VCC = 3.3 V, RL = 50 , CL = 5 pF, f = 1 MHz)
−405C to +855C
Symbol
Pins
VCC (V)
Min
Typ
Max
Unit
OIRR
Open
OFF−Isolation
1.65 − 4.5
−
−57
−
dB
XTALK
HSD+,
HSD−
Non−Adjacent Channel
Crosstalk
1.65 − 4.5
−
−97
−
dB
Parameter
Test Conditions
CAPACITANCE (Typical: T = 25°C, VCC = 3.3 V, RL = 50 , CL = 5 pF, f = 1 MHz)
−405C to +855C
Symbol
Pins
Parameter
Test Conditions
Min
Typ
Max
Unit
CIN
OE
Control Pin Input Capacitance
VCC = 0 V
−
8.5
−
pF
CON
HSD+,
to D+
ON Capacitance
VIN = 0 V
−
32
−
pF
COFF
HSD+,
HSD−
OFF Capacitance
VIS = 3.3 V; VIN = 3.3 V
−
19
−
pF
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5
NLAS5213
1.6
1.4
1.6
85°C
25°C
1.2
1.2
−40°C
RDS(on) ()
1
0.8
0.6
1
−40°C
0.8
0.6
0.4
0.4
0.2
0.2
0
0
0
0.4
0.8
1.2
1.6
2
2.4
0
0.4
0.8
1.2
1.6
2
2.4
Vin (V)
Vin (V)
Figure 3. RON @ VCC = 2.7 V
Figure 4. RON @ VCC = 3.3 V
1.4
85°C
1.2
25°C
1
RDS(on) ()
RDS(on) ()
85°C
1.4
25°C
−40°C
0.8
0.6
0.4
0.2
0
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
Vin (V)
Figure 5. RON @ VCC = 4.2 V
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6
3.6
4
2.8
3.2
NLAS5213
160
140
VCC = 4.3 V
120
ICC, (A)
100
80
60
VCC = 3.3 V
40
VCC = 2.7 V
20
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN, (V)
Figure 6. ICC vs. VIN
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
50 35 pF
tBMM
Output
50 % OF
DROOP
VOLTAGE
DROOP
Switch Select Pin
Figure 7. tBBM (Time Break−Before−Make)
VCC
Input
DUT
VCC
0.1 F
50%
0V
Output
VOUT
Open
50%
50 VOH
90%
35 pF
90%
Output
VOL
Input
tON
Figure 8. tON/tOFF
VCC
VCC
Input
DUT
Output
50%
50%
0V
50 VOUT
Open
tOFF
VOH
35 pF
Output
Input
tOFF
Figure 9. tON/tOFF
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7
10%
10%
VOL
tON
NLAS5213
50 Reference
DUT
Transmitted
Input
Output
50 Generator
50 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss
is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
ǒVVOUT
Ǔ for VIN at 100 kHz
IN
VOUT
Ǔ for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log ǒ
VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 Figure 10. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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8
NLAS5213
DEVICE ORDERING INFORMATION
Marking
Package Type
Shipping†
NLAS5213AUSG
VD
US8
(Pb−Free)
3,000 / Tape & Reel
NLAS5213AMUTAG
VD
UDFN8
(Pb−Free)
3,000 / Tape & Reel
NLAS5213BUSG
VE
US8
(Pb−Free)
3,000 / Tape & Reel
NLAS5213BMUTAG
VE
UDFN8
(Pb−Free)
3,000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NLAS5213
PACKAGE DIMENSIONS
US8
CASE 493−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).
−X−
A
8
J
−Y−
5
DETAIL E
B
L
1
4
R
S
G
P
U
C
−T−
SEATING
PLANE
H
0.10 (0.004) T
K
D
N
0.10 (0.004)
M
R 0.10 TYP
T X Y
V
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
F
DETAIL E
SOLDERING FOOTPRINT*
3.8
0.15
0.50
0.0197
1.8
0.07
0.30
0.012
1.0
0.0394
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0_
6_
5_
10 _
0.23
0.34
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.126
0_
6_
5_
10 _
0.010
0.013
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
NLAS5213
PACKAGE DIMENSIONS
UDFN8 1.8x1.2, 0.4P
CASE 517AJ−01
ISSUE O
PIN ONE
REFERENCE
ÉÉÉ
ÉÉÉ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
A B
D
0.10 C
L1
E
DETAIL A
NOTE 5
TOP VIEW
(A3)
0.05 C
DIM
A
A1
A3
b
b2
D
E
e
L
L1
L2
A
0.05 C
SIDE VIEW
e/2
(b2)
A1
e
1
C
SEATING
PLANE
DETAIL A
8X
L
4
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
0.30 REF
1.80 BSC
1.20 BSC
0.40 BSC
0.45
0.55
0.00
0.03
0.40 REF
SOLDERING FOOTPRINT*
(L2)
8
5
8X b
BOTTOM VIEW
8X
0.10
M
C A B
0.05
M
C
0.66
7X
0.22
NOTE 3
1.50
1
0.32
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NLAS5213/D